1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * pata-legacy.c - Legacy port PATA/SATA controller driver. |
4 | * Copyright 2005/2006 Red Hat, all rights reserved. |
5 | * |
6 | * An ATA driver for the legacy ATA ports. |
7 | * |
8 | * Data Sources: |
9 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com |
10 | * HT6560 series: |
11 | * Promise 20230/20620: |
12 | * http://www.ryston.cz/petr/vlb/pdc20230b.html |
13 | * http://www.ryston.cz/petr/vlb/pdc20230c.html |
14 | * http://www.ryston.cz/petr/vlb/pdc20630.html |
15 | * QDI65x0: |
16 | * http://www.ryston.cz/petr/vlb/qd6500.html |
17 | * http://www.ryston.cz/petr/vlb/qd6580.html |
18 | * |
19 | * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c |
20 | * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by |
21 | * Samuel Thibault <samuel.thibault@ens-lyon.org> |
22 | * |
23 | * Unsupported but docs exist: |
24 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 |
25 | * |
26 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found |
27 | * on PC class systems. There are three hybrid devices that are exceptions |
28 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and |
29 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". |
30 | * |
31 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ |
32 | * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A |
33 | * |
34 | * Support for the Winbond 83759A when operating in advanced mode. |
35 | * Multichip mode is not currently supported. |
36 | * |
37 | * Use the autospeed and pio_mask options with: |
38 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. |
39 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with |
40 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, |
41 | * Winbond W83759A, Promise PDC20230-B |
42 | * |
43 | * For now use autospeed and pio_mask as above with the W83759A. This may |
44 | * change. |
45 | */ |
46 | |
47 | #include <linux/async.h> |
48 | #include <linux/kernel.h> |
49 | #include <linux/module.h> |
50 | #include <linux/pci.h> |
51 | #include <linux/init.h> |
52 | #include <linux/blkdev.h> |
53 | #include <linux/delay.h> |
54 | #include <scsi/scsi_host.h> |
55 | #include <linux/ata.h> |
56 | #include <linux/libata.h> |
57 | #include <linux/platform_device.h> |
58 | |
59 | #define DRV_NAME "pata_legacy" |
60 | #define DRV_VERSION "0.6.5" |
61 | |
62 | #define NR_HOST 6 |
63 | |
64 | static int all; |
65 | module_param(all, int, 0444); |
66 | MODULE_PARM_DESC(all, |
67 | "Set to probe unclaimed pri/sec ISA port ranges even if PCI" ); |
68 | |
69 | static int probe_all; |
70 | module_param(probe_all, int, 0); |
71 | MODULE_PARM_DESC(probe_all, |
72 | "Set to probe tertiary+ ISA port ranges even if PCI" ); |
73 | |
74 | static int probe_mask = ~0; |
75 | module_param(probe_mask, int, 0); |
76 | MODULE_PARM_DESC(probe_mask, "Probe mask for legacy ISA PATA ports" ); |
77 | |
78 | static int autospeed; |
79 | module_param(autospeed, int, 0); |
80 | MODULE_PARM_DESC(autospeed, "Chip present that snoops speed changes" ); |
81 | |
82 | static int pio_mask = ATA_PIO4; |
83 | module_param(pio_mask, int, 0); |
84 | MODULE_PARM_DESC(pio_mask, "PIO range for autospeed devices" ); |
85 | |
86 | static int iordy_mask = 0xFFFFFFFF; |
87 | module_param(iordy_mask, int, 0); |
88 | MODULE_PARM_DESC(iordy_mask, "Use IORDY if available" ); |
89 | |
90 | static int ht6560a; |
91 | module_param(ht6560a, int, 0); |
92 | MODULE_PARM_DESC(ht6560a, "HT 6560A on primary 1, second 2, both 3" ); |
93 | |
94 | static int ht6560b; |
95 | module_param(ht6560b, int, 0); |
96 | MODULE_PARM_DESC(ht6560b, "HT 6560B on primary 1, secondary 2, both 3" ); |
97 | |
98 | static int opti82c611a; |
99 | module_param(opti82c611a, int, 0); |
100 | MODULE_PARM_DESC(opti82c611a, |
101 | "Opti 82c611A on primary 1, secondary 2, both 3" ); |
102 | |
103 | static int opti82c46x; |
104 | module_param(opti82c46x, int, 0); |
105 | MODULE_PARM_DESC(opti82c46x, |
106 | "Opti 82c465MV on primary 1, secondary 2, both 3" ); |
107 | |
108 | #ifdef CONFIG_PATA_QDI_MODULE |
109 | static int qdi = 1; |
110 | #else |
111 | static int qdi; |
112 | #endif |
113 | module_param(qdi, int, 0); |
114 | MODULE_PARM_DESC(qdi, "Set to probe QDI controllers" ); |
115 | |
116 | #ifdef CONFIG_PATA_WINBOND_VLB_MODULE |
117 | static int winbond = 1; |
118 | #else |
119 | static int winbond; |
120 | #endif |
121 | module_param(winbond, int, 0); |
122 | MODULE_PARM_DESC(winbond, |
123 | "Set to probe Winbond controllers, " |
124 | "give I/O port if non standard" ); |
125 | |
126 | |
127 | enum controller { |
128 | BIOS = 0, |
129 | SNOOP = 1, |
130 | PDC20230 = 2, |
131 | HT6560A = 3, |
132 | HT6560B = 4, |
133 | OPTI611A = 5, |
134 | OPTI46X = 6, |
135 | QDI6500 = 7, |
136 | QDI6580 = 8, |
137 | QDI6580DP = 9, /* Dual channel mode is different */ |
138 | W83759A = 10, |
139 | |
140 | UNKNOWN = -1 |
141 | }; |
142 | |
143 | struct legacy_data { |
144 | unsigned long timing; |
145 | u8 clock[2]; |
146 | u8 last; |
147 | int fast; |
148 | enum controller type; |
149 | struct platform_device *platform_dev; |
150 | }; |
151 | |
152 | struct legacy_probe { |
153 | unsigned char *name; |
154 | unsigned long port; |
155 | unsigned int irq; |
156 | unsigned int slot; |
157 | enum controller type; |
158 | unsigned long private; |
159 | }; |
160 | |
161 | struct legacy_controller { |
162 | const char *name; |
163 | struct ata_port_operations *ops; |
164 | unsigned int pio_mask; |
165 | unsigned int flags; |
166 | unsigned int pflags; |
167 | int (*setup)(struct platform_device *, struct legacy_probe *probe, |
168 | struct legacy_data *data); |
169 | }; |
170 | |
171 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; |
172 | |
173 | static struct legacy_probe probe_list[NR_HOST]; |
174 | static struct legacy_data legacy_data[NR_HOST]; |
175 | static struct ata_host *legacy_host[NR_HOST]; |
176 | static int nr_legacy_host; |
177 | |
178 | |
179 | /** |
180 | * legacy_probe_add - Add interface to probe list |
181 | * @port: Controller port |
182 | * @irq: IRQ number |
183 | * @type: Controller type |
184 | * @private: Controller specific info |
185 | * |
186 | * Add an entry into the probe list for ATA controllers. This is used |
187 | * to add the default ISA slots and then to build up the table |
188 | * further according to other ISA/VLB/Weird device scans |
189 | * |
190 | * An I/O port list is used to keep ordering stable and sane, as we |
191 | * don't have any good way to talk about ordering otherwise |
192 | */ |
193 | |
194 | static int legacy_probe_add(unsigned long port, unsigned int irq, |
195 | enum controller type, unsigned long private) |
196 | { |
197 | struct legacy_probe *lp = &probe_list[0]; |
198 | int i; |
199 | struct legacy_probe *free = NULL; |
200 | |
201 | for (i = 0; i < NR_HOST; i++) { |
202 | if (lp->port == 0 && free == NULL) |
203 | free = lp; |
204 | /* Matching port, or the correct slot for ordering */ |
205 | if (lp->port == port || legacy_port[i] == port) { |
206 | if (!(probe_mask & 1 << i)) |
207 | return -1; |
208 | free = lp; |
209 | break; |
210 | } |
211 | lp++; |
212 | } |
213 | if (free == NULL) { |
214 | printk(KERN_ERR "pata_legacy: Too many interfaces.\n" ); |
215 | return -1; |
216 | } |
217 | /* Fill in the entry for later probing */ |
218 | free->port = port; |
219 | free->irq = irq; |
220 | free->type = type; |
221 | free->private = private; |
222 | return 0; |
223 | } |
224 | |
225 | |
226 | /** |
227 | * legacy_set_mode - mode setting |
228 | * @link: IDE link |
229 | * @unused: Device that failed when error is returned |
230 | * |
231 | * Use a non standard set_mode function. We don't want to be tuned. |
232 | * |
233 | * The BIOS configured everything. Our job is not to fiddle. Just use |
234 | * whatever PIO the hardware is using and leave it at that. When we |
235 | * get some kind of nice user driven API for control then we can |
236 | * expand on this as per hdparm in the base kernel. |
237 | */ |
238 | |
239 | static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) |
240 | { |
241 | struct ata_device *dev; |
242 | |
243 | ata_for_each_dev(dev, link, ENABLED) { |
244 | ata_dev_info(dev, "configured for PIO\n" ); |
245 | dev->pio_mode = XFER_PIO_0; |
246 | dev->xfer_mode = XFER_PIO_0; |
247 | dev->xfer_shift = ATA_SHIFT_PIO; |
248 | dev->flags |= ATA_DFLAG_PIO; |
249 | } |
250 | return 0; |
251 | } |
252 | |
253 | static const struct scsi_host_template legacy_sht = { |
254 | ATA_PIO_SHT(DRV_NAME), |
255 | }; |
256 | |
257 | static const struct ata_port_operations legacy_base_port_ops = { |
258 | .inherits = &ata_sff_port_ops, |
259 | .cable_detect = ata_cable_40wire, |
260 | }; |
261 | |
262 | /* |
263 | * These ops are used if the user indicates the hardware |
264 | * snoops the commands to decide on the mode and handles the |
265 | * mode selection "magically" itself. Several legacy controllers |
266 | * do this. The mode range can be set if it is not 0x1F by setting |
267 | * pio_mask as well. |
268 | */ |
269 | |
270 | static struct ata_port_operations simple_port_ops = { |
271 | .inherits = &legacy_base_port_ops, |
272 | .sff_data_xfer = ata_sff_data_xfer32, |
273 | }; |
274 | |
275 | static struct ata_port_operations legacy_port_ops = { |
276 | .inherits = &legacy_base_port_ops, |
277 | .sff_data_xfer = ata_sff_data_xfer32, |
278 | .set_mode = legacy_set_mode, |
279 | }; |
280 | |
281 | /* |
282 | * Promise 20230C and 20620 support |
283 | * |
284 | * This controller supports PIO0 to PIO2. We set PIO timings |
285 | * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA |
286 | * support is weird being DMA to controller and PIO'd to the host |
287 | * and not supported. |
288 | */ |
289 | |
290 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) |
291 | { |
292 | int tries = 5; |
293 | int pio = adev->pio_mode - XFER_PIO_0; |
294 | u8 rt; |
295 | unsigned long flags; |
296 | |
297 | /* Safe as UP only. Force I/Os to occur together */ |
298 | |
299 | local_irq_save(flags); |
300 | |
301 | /* Unlock the control interface */ |
302 | do { |
303 | inb(port: 0x1F5); |
304 | outb(inb(port: 0x1F2) | 0x80, port: 0x1F2); |
305 | inb(port: 0x1F2); |
306 | inb(port: 0x3F6); |
307 | inb(port: 0x3F6); |
308 | inb(port: 0x1F2); |
309 | inb(port: 0x1F2); |
310 | } |
311 | while ((inb(port: 0x1F2) & 0x80) && --tries); |
312 | |
313 | local_irq_restore(flags); |
314 | |
315 | outb(inb(port: 0x1F4) & 0x07, port: 0x1F4); |
316 | |
317 | rt = inb(port: 0x1F3); |
318 | rt &= ~(0x07 << (3 * !adev->devno)); |
319 | if (pio) |
320 | rt |= (1 + 3 * pio) << (3 * !adev->devno); |
321 | outb(value: rt, port: 0x1F3); |
322 | |
323 | udelay(100); |
324 | outb(inb(port: 0x1F2) | 0x01, port: 0x1F2); |
325 | udelay(100); |
326 | inb(port: 0x1F5); |
327 | |
328 | } |
329 | |
330 | static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc, |
331 | unsigned char *buf, unsigned int buflen, int rw) |
332 | { |
333 | struct ata_device *dev = qc->dev; |
334 | struct ata_port *ap = dev->link->ap; |
335 | int slop = buflen & 3; |
336 | |
337 | /* 32bit I/O capable *and* we need to write a whole number of dwords */ |
338 | if (ata_id_has_dword_io(id: dev->id) && (slop == 0 || slop == 3) |
339 | && (ap->pflags & ATA_PFLAG_PIO32)) { |
340 | unsigned long flags; |
341 | |
342 | local_irq_save(flags); |
343 | |
344 | /* Perform the 32bit I/O synchronization sequence */ |
345 | ioread8(ap->ioaddr.nsect_addr); |
346 | ioread8(ap->ioaddr.nsect_addr); |
347 | ioread8(ap->ioaddr.nsect_addr); |
348 | |
349 | /* Now the data */ |
350 | if (rw == READ) |
351 | ioread32_rep(port: ap->ioaddr.data_addr, buf, count: buflen >> 2); |
352 | else |
353 | iowrite32_rep(port: ap->ioaddr.data_addr, buf, count: buflen >> 2); |
354 | |
355 | if (unlikely(slop)) { |
356 | __le32 pad = 0; |
357 | |
358 | if (rw == READ) { |
359 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
360 | memcpy(buf + buflen - slop, &pad, slop); |
361 | } else { |
362 | memcpy(&pad, buf + buflen - slop, slop); |
363 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
364 | } |
365 | buflen += 4 - slop; |
366 | } |
367 | local_irq_restore(flags); |
368 | } else |
369 | buflen = ata_sff_data_xfer32(qc, buf, buflen, rw); |
370 | |
371 | return buflen; |
372 | } |
373 | |
374 | static struct ata_port_operations pdc20230_port_ops = { |
375 | .inherits = &legacy_base_port_ops, |
376 | .set_piomode = pdc20230_set_piomode, |
377 | .sff_data_xfer = pdc_data_xfer_vlb, |
378 | }; |
379 | |
380 | /* |
381 | * Holtek 6560A support |
382 | * |
383 | * This controller supports PIO0 to PIO2 (no IORDY even though higher |
384 | * timings can be loaded). |
385 | */ |
386 | |
387 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) |
388 | { |
389 | u8 active, recover; |
390 | struct ata_timing t; |
391 | |
392 | /* Get the timing data in cycles. For now play safe at 50Mhz */ |
393 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
394 | |
395 | active = clamp_val(t.active, 2, 15); |
396 | recover = clamp_val(t.recover, 4, 15); |
397 | |
398 | inb(port: 0x3E6); |
399 | inb(port: 0x3E6); |
400 | inb(port: 0x3E6); |
401 | inb(port: 0x3E6); |
402 | |
403 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
404 | ioread8(ap->ioaddr.status_addr); |
405 | } |
406 | |
407 | static struct ata_port_operations ht6560a_port_ops = { |
408 | .inherits = &legacy_base_port_ops, |
409 | .set_piomode = ht6560a_set_piomode, |
410 | }; |
411 | |
412 | /* |
413 | * Holtek 6560B support |
414 | * |
415 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO |
416 | * setting unless we see an ATAPI device in which case we force it off. |
417 | * |
418 | * FIXME: need to implement 2nd channel support. |
419 | */ |
420 | |
421 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) |
422 | { |
423 | u8 active, recover; |
424 | struct ata_timing t; |
425 | |
426 | /* Get the timing data in cycles. For now play safe at 50Mhz */ |
427 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
428 | |
429 | active = clamp_val(t.active, 2, 15); |
430 | recover = clamp_val(t.recover, 2, 16) & 0x0F; |
431 | |
432 | inb(port: 0x3E6); |
433 | inb(port: 0x3E6); |
434 | inb(port: 0x3E6); |
435 | inb(port: 0x3E6); |
436 | |
437 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
438 | |
439 | if (adev->class != ATA_DEV_ATA) { |
440 | u8 rconf = inb(port: 0x3E6); |
441 | if (rconf & 0x24) { |
442 | rconf &= ~0x24; |
443 | outb(value: rconf, port: 0x3E6); |
444 | } |
445 | } |
446 | ioread8(ap->ioaddr.status_addr); |
447 | } |
448 | |
449 | static struct ata_port_operations ht6560b_port_ops = { |
450 | .inherits = &legacy_base_port_ops, |
451 | .set_piomode = ht6560b_set_piomode, |
452 | }; |
453 | |
454 | /* |
455 | * Opti core chipset helpers |
456 | */ |
457 | |
458 | /** |
459 | * opti_syscfg - read OPTI chipset configuration |
460 | * @reg: Configuration register to read |
461 | * |
462 | * Returns the value of an OPTI system board configuration register. |
463 | */ |
464 | |
465 | static u8 opti_syscfg(u8 reg) |
466 | { |
467 | unsigned long flags; |
468 | u8 r; |
469 | |
470 | /* Uniprocessor chipset and must force cycles adjancent */ |
471 | local_irq_save(flags); |
472 | outb(value: reg, port: 0x22); |
473 | r = inb(port: 0x24); |
474 | local_irq_restore(flags); |
475 | return r; |
476 | } |
477 | |
478 | /* |
479 | * Opti 82C611A |
480 | * |
481 | * This controller supports PIO0 to PIO3. |
482 | */ |
483 | |
484 | static void opti82c611a_set_piomode(struct ata_port *ap, |
485 | struct ata_device *adev) |
486 | { |
487 | u8 active, recover, setup; |
488 | struct ata_timing t; |
489 | struct ata_device *pair = ata_dev_pair(adev); |
490 | int clock; |
491 | int khz[4] = { 50000, 40000, 33000, 25000 }; |
492 | u8 rc; |
493 | |
494 | /* Enter configuration mode */ |
495 | ioread16(ap->ioaddr.error_addr); |
496 | ioread16(ap->ioaddr.error_addr); |
497 | iowrite8(3, ap->ioaddr.nsect_addr); |
498 | |
499 | /* Read VLB clock strapping */ |
500 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
501 | |
502 | /* Get the timing data in cycles */ |
503 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); |
504 | |
505 | /* Setup timing is shared */ |
506 | if (pair) { |
507 | struct ata_timing tp; |
508 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); |
509 | |
510 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); |
511 | } |
512 | |
513 | active = clamp_val(t.active, 2, 17) - 2; |
514 | recover = clamp_val(t.recover, 1, 16) - 1; |
515 | setup = clamp_val(t.setup, 1, 4) - 1; |
516 | |
517 | /* Select the right timing bank for write timing */ |
518 | rc = ioread8(ap->ioaddr.lbal_addr); |
519 | rc &= 0x7F; |
520 | rc |= (adev->devno << 7); |
521 | iowrite8(rc, ap->ioaddr.lbal_addr); |
522 | |
523 | /* Write the timings */ |
524 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
525 | |
526 | /* Select the right bank for read timings, also |
527 | load the shared timings for address */ |
528 | rc = ioread8(ap->ioaddr.device_addr); |
529 | rc &= 0xC0; |
530 | rc |= adev->devno; /* Index select */ |
531 | rc |= (setup << 4) | 0x04; |
532 | iowrite8(rc, ap->ioaddr.device_addr); |
533 | |
534 | /* Load the read timings */ |
535 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
536 | |
537 | /* Ensure the timing register mode is right */ |
538 | rc = ioread8(ap->ioaddr.lbal_addr); |
539 | rc &= 0x73; |
540 | rc |= 0x84; |
541 | iowrite8(rc, ap->ioaddr.lbal_addr); |
542 | |
543 | /* Exit command mode */ |
544 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
545 | } |
546 | |
547 | |
548 | static struct ata_port_operations opti82c611a_port_ops = { |
549 | .inherits = &legacy_base_port_ops, |
550 | .set_piomode = opti82c611a_set_piomode, |
551 | }; |
552 | |
553 | /* |
554 | * Opti 82C465MV |
555 | * |
556 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB |
557 | * version is dual channel but doesn't have a lot of unique registers. |
558 | */ |
559 | |
560 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) |
561 | { |
562 | u8 active, recover, setup; |
563 | struct ata_timing t; |
564 | struct ata_device *pair = ata_dev_pair(adev); |
565 | int clock; |
566 | int khz[4] = { 50000, 40000, 33000, 25000 }; |
567 | u8 rc; |
568 | u8 sysclk; |
569 | |
570 | /* Get the clock */ |
571 | sysclk = (opti_syscfg(reg: 0xAC) & 0xC0) >> 6; /* BIOS set */ |
572 | |
573 | /* Enter configuration mode */ |
574 | ioread16(ap->ioaddr.error_addr); |
575 | ioread16(ap->ioaddr.error_addr); |
576 | iowrite8(3, ap->ioaddr.nsect_addr); |
577 | |
578 | /* Read VLB clock strapping */ |
579 | clock = 1000000000 / khz[sysclk]; |
580 | |
581 | /* Get the timing data in cycles */ |
582 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); |
583 | |
584 | /* Setup timing is shared */ |
585 | if (pair) { |
586 | struct ata_timing tp; |
587 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); |
588 | |
589 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); |
590 | } |
591 | |
592 | active = clamp_val(t.active, 2, 17) - 2; |
593 | recover = clamp_val(t.recover, 1, 16) - 1; |
594 | setup = clamp_val(t.setup, 1, 4) - 1; |
595 | |
596 | /* Select the right timing bank for write timing */ |
597 | rc = ioread8(ap->ioaddr.lbal_addr); |
598 | rc &= 0x7F; |
599 | rc |= (adev->devno << 7); |
600 | iowrite8(rc, ap->ioaddr.lbal_addr); |
601 | |
602 | /* Write the timings */ |
603 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
604 | |
605 | /* Select the right bank for read timings, also |
606 | load the shared timings for address */ |
607 | rc = ioread8(ap->ioaddr.device_addr); |
608 | rc &= 0xC0; |
609 | rc |= adev->devno; /* Index select */ |
610 | rc |= (setup << 4) | 0x04; |
611 | iowrite8(rc, ap->ioaddr.device_addr); |
612 | |
613 | /* Load the read timings */ |
614 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
615 | |
616 | /* Ensure the timing register mode is right */ |
617 | rc = ioread8(ap->ioaddr.lbal_addr); |
618 | rc &= 0x73; |
619 | rc |= 0x84; |
620 | iowrite8(rc, ap->ioaddr.lbal_addr); |
621 | |
622 | /* Exit command mode */ |
623 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
624 | |
625 | /* We need to know this for quad device on the MVB */ |
626 | ap->host->private_data = ap; |
627 | } |
628 | |
629 | /** |
630 | * opti82c46x_qc_issue - command issue |
631 | * @qc: command pending |
632 | * |
633 | * Called when the libata layer is about to issue a command. We wrap |
634 | * this interface so that we can load the correct ATA timings. The |
635 | * MVB has a single set of timing registers and these are shared |
636 | * across channels. As there are two registers we really ought to |
637 | * track the last two used values as a sort of register window. For |
638 | * now we just reload on a channel switch. On the single channel |
639 | * setup this condition never fires so we do nothing extra. |
640 | * |
641 | * FIXME: dual channel needs ->serialize support |
642 | */ |
643 | |
644 | static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) |
645 | { |
646 | struct ata_port *ap = qc->ap; |
647 | struct ata_device *adev = qc->dev; |
648 | |
649 | /* If timings are set and for the wrong channel (2nd test is |
650 | due to a libata shortcoming and will eventually go I hope) */ |
651 | if (ap->host->private_data != ap->host |
652 | && ap->host->private_data != NULL) |
653 | opti82c46x_set_piomode(ap, adev); |
654 | |
655 | return ata_sff_qc_issue(qc); |
656 | } |
657 | |
658 | static struct ata_port_operations opti82c46x_port_ops = { |
659 | .inherits = &legacy_base_port_ops, |
660 | .set_piomode = opti82c46x_set_piomode, |
661 | .qc_issue = opti82c46x_qc_issue, |
662 | }; |
663 | |
664 | /** |
665 | * qdi65x0_set_piomode - PIO setup for QDI65x0 |
666 | * @ap: Port |
667 | * @adev: Device |
668 | * |
669 | * In single channel mode the 6580 has one clock per device and we can |
670 | * avoid the requirement to clock switch. We also have to load the timing |
671 | * into the right clock according to whether we are master or slave. |
672 | * |
673 | * In dual channel mode the 6580 has one clock per channel and we have |
674 | * to software clockswitch in qc_issue. |
675 | */ |
676 | |
677 | static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev) |
678 | { |
679 | struct ata_timing t; |
680 | struct legacy_data *ld_qdi = ap->host->private_data; |
681 | int active, recovery; |
682 | u8 timing; |
683 | |
684 | /* Get the timing data in cycles */ |
685 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); |
686 | |
687 | if (ld_qdi->fast) { |
688 | active = 8 - clamp_val(t.active, 1, 8); |
689 | recovery = 18 - clamp_val(t.recover, 3, 18); |
690 | } else { |
691 | active = 9 - clamp_val(t.active, 2, 9); |
692 | recovery = 15 - clamp_val(t.recover, 0, 15); |
693 | } |
694 | timing = (recovery << 4) | active | 0x08; |
695 | ld_qdi->clock[adev->devno] = timing; |
696 | |
697 | if (ld_qdi->type == QDI6580) |
698 | outb(value: timing, port: ld_qdi->timing + 2 * adev->devno); |
699 | else |
700 | outb(value: timing, port: ld_qdi->timing + 2 * ap->port_no); |
701 | |
702 | /* Clear the FIFO */ |
703 | if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA) |
704 | outb(value: 0x5F, port: (ld_qdi->timing & 0xFFF0) + 3); |
705 | } |
706 | |
707 | /** |
708 | * qdi_qc_issue - command issue |
709 | * @qc: command pending |
710 | * |
711 | * Called when the libata layer is about to issue a command. We wrap |
712 | * this interface so that we can load the correct ATA timings. |
713 | */ |
714 | |
715 | static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) |
716 | { |
717 | struct ata_port *ap = qc->ap; |
718 | struct ata_device *adev = qc->dev; |
719 | struct legacy_data *ld_qdi = ap->host->private_data; |
720 | |
721 | if (ld_qdi->clock[adev->devno] != ld_qdi->last) { |
722 | if (adev->pio_mode) { |
723 | ld_qdi->last = ld_qdi->clock[adev->devno]; |
724 | outb(value: ld_qdi->clock[adev->devno], port: ld_qdi->timing + |
725 | 2 * ap->port_no); |
726 | } |
727 | } |
728 | return ata_sff_qc_issue(qc); |
729 | } |
730 | |
731 | static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc, |
732 | unsigned char *buf, |
733 | unsigned int buflen, int rw) |
734 | { |
735 | struct ata_device *adev = qc->dev; |
736 | struct ata_port *ap = adev->link->ap; |
737 | int slop = buflen & 3; |
738 | |
739 | if (ata_id_has_dword_io(id: adev->id) && (slop == 0 || slop == 3) |
740 | && (ap->pflags & ATA_PFLAG_PIO32)) { |
741 | if (rw == WRITE) |
742 | iowrite32_rep(port: ap->ioaddr.data_addr, buf, count: buflen >> 2); |
743 | else |
744 | ioread32_rep(port: ap->ioaddr.data_addr, buf, count: buflen >> 2); |
745 | |
746 | if (unlikely(slop)) { |
747 | __le32 pad = 0; |
748 | |
749 | if (rw == WRITE) { |
750 | memcpy(&pad, buf + buflen - slop, slop); |
751 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
752 | } else { |
753 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
754 | memcpy(buf + buflen - slop, &pad, slop); |
755 | } |
756 | } |
757 | return (buflen + 3) & ~3; |
758 | } else |
759 | return ata_sff_data_xfer(qc, buf, buflen, rw); |
760 | } |
761 | |
762 | static int qdi_port(struct platform_device *dev, |
763 | struct legacy_probe *lp, struct legacy_data *ld) |
764 | { |
765 | if (devm_request_region(&dev->dev, lp->private, 4, "qdi" ) == NULL) |
766 | return -EBUSY; |
767 | ld->timing = lp->private; |
768 | return 0; |
769 | } |
770 | |
771 | static struct ata_port_operations qdi6500_port_ops = { |
772 | .inherits = &legacy_base_port_ops, |
773 | .set_piomode = qdi65x0_set_piomode, |
774 | .qc_issue = qdi_qc_issue, |
775 | .sff_data_xfer = vlb32_data_xfer, |
776 | }; |
777 | |
778 | static struct ata_port_operations qdi6580_port_ops = { |
779 | .inherits = &legacy_base_port_ops, |
780 | .set_piomode = qdi65x0_set_piomode, |
781 | .sff_data_xfer = vlb32_data_xfer, |
782 | }; |
783 | |
784 | static struct ata_port_operations qdi6580dp_port_ops = { |
785 | .inherits = &legacy_base_port_ops, |
786 | .set_piomode = qdi65x0_set_piomode, |
787 | .qc_issue = qdi_qc_issue, |
788 | .sff_data_xfer = vlb32_data_xfer, |
789 | }; |
790 | |
791 | static DEFINE_SPINLOCK(winbond_lock); |
792 | |
793 | static void winbond_writecfg(unsigned long port, u8 reg, u8 val) |
794 | { |
795 | unsigned long flags; |
796 | spin_lock_irqsave(&winbond_lock, flags); |
797 | outb(value: reg, port: port + 0x01); |
798 | outb(value: val, port: port + 0x02); |
799 | spin_unlock_irqrestore(lock: &winbond_lock, flags); |
800 | } |
801 | |
802 | static u8 winbond_readcfg(unsigned long port, u8 reg) |
803 | { |
804 | u8 val; |
805 | |
806 | unsigned long flags; |
807 | spin_lock_irqsave(&winbond_lock, flags); |
808 | outb(value: reg, port: port + 0x01); |
809 | val = inb(port: port + 0x02); |
810 | spin_unlock_irqrestore(lock: &winbond_lock, flags); |
811 | |
812 | return val; |
813 | } |
814 | |
815 | static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) |
816 | { |
817 | struct ata_timing t; |
818 | struct legacy_data *ld_winbond = ap->host->private_data; |
819 | int active, recovery; |
820 | u8 reg; |
821 | int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); |
822 | |
823 | reg = winbond_readcfg(port: ld_winbond->timing, reg: 0x81); |
824 | |
825 | /* Get the timing data in cycles */ |
826 | if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ |
827 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
828 | else |
829 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); |
830 | |
831 | active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; |
832 | recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; |
833 | timing = (active << 4) | recovery; |
834 | winbond_writecfg(port: ld_winbond->timing, reg: timing, val: reg); |
835 | |
836 | /* Load the setup timing */ |
837 | |
838 | reg = 0x35; |
839 | if (adev->class != ATA_DEV_ATA) |
840 | reg |= 0x08; /* FIFO off */ |
841 | if (!ata_pio_need_iordy(adev)) |
842 | reg |= 0x02; /* IORDY off */ |
843 | reg |= (clamp_val(t.setup, 0, 3) << 6); |
844 | winbond_writecfg(port: ld_winbond->timing, reg: timing + 1, val: reg); |
845 | } |
846 | |
847 | static int winbond_port(struct platform_device *dev, |
848 | struct legacy_probe *lp, struct legacy_data *ld) |
849 | { |
850 | if (devm_request_region(&dev->dev, lp->private, 4, "winbond" ) == NULL) |
851 | return -EBUSY; |
852 | ld->timing = lp->private; |
853 | return 0; |
854 | } |
855 | |
856 | static struct ata_port_operations winbond_port_ops = { |
857 | .inherits = &legacy_base_port_ops, |
858 | .set_piomode = winbond_set_piomode, |
859 | .sff_data_xfer = vlb32_data_xfer, |
860 | }; |
861 | |
862 | static struct legacy_controller controllers[] = { |
863 | {"BIOS" , &legacy_port_ops, ATA_PIO4, |
864 | ATA_FLAG_NO_IORDY, 0, NULL }, |
865 | {"Snooping" , &simple_port_ops, ATA_PIO4, |
866 | 0, 0, NULL }, |
867 | {"PDC20230" , &pdc20230_port_ops, ATA_PIO2, |
868 | ATA_FLAG_NO_IORDY, |
869 | ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, |
870 | {"HT6560A" , &ht6560a_port_ops, ATA_PIO2, |
871 | ATA_FLAG_NO_IORDY, 0, NULL }, |
872 | {"HT6560B" , &ht6560b_port_ops, ATA_PIO4, |
873 | ATA_FLAG_NO_IORDY, 0, NULL }, |
874 | {"OPTI82C611A" , &opti82c611a_port_ops, ATA_PIO3, |
875 | 0, 0, NULL }, |
876 | {"OPTI82C46X" , &opti82c46x_port_ops, ATA_PIO3, |
877 | 0, 0, NULL }, |
878 | {"QDI6500" , &qdi6500_port_ops, ATA_PIO2, |
879 | ATA_FLAG_NO_IORDY, |
880 | ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
881 | {"QDI6580" , &qdi6580_port_ops, ATA_PIO4, |
882 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
883 | {"QDI6580DP" , &qdi6580dp_port_ops, ATA_PIO4, |
884 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
885 | {"W83759A" , &winbond_port_ops, ATA_PIO4, |
886 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, |
887 | winbond_port } |
888 | }; |
889 | |
890 | /** |
891 | * probe_chip_type - Discover controller |
892 | * @probe: Probe entry to check |
893 | * |
894 | * Probe an ATA port and identify the type of controller. We don't |
895 | * check if the controller appears to be driveless at this point. |
896 | */ |
897 | |
898 | static __init int probe_chip_type(struct legacy_probe *probe) |
899 | { |
900 | int mask = 1 << probe->slot; |
901 | |
902 | if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { |
903 | u8 reg = winbond_readcfg(port: winbond, reg: 0x81); |
904 | reg |= 0x80; /* jumpered mode off */ |
905 | winbond_writecfg(port: winbond, reg: 0x81, val: reg); |
906 | reg = winbond_readcfg(port: winbond, reg: 0x83); |
907 | reg |= 0xF0; /* local control */ |
908 | winbond_writecfg(port: winbond, reg: 0x83, val: reg); |
909 | reg = winbond_readcfg(port: winbond, reg: 0x85); |
910 | reg |= 0xF0; /* programmable timing */ |
911 | winbond_writecfg(port: winbond, reg: 0x85, val: reg); |
912 | |
913 | reg = winbond_readcfg(port: winbond, reg: 0x81); |
914 | |
915 | if (reg & mask) |
916 | return W83759A; |
917 | } |
918 | if (probe->port == 0x1F0) { |
919 | unsigned long flags; |
920 | local_irq_save(flags); |
921 | /* Probes */ |
922 | outb(inb(port: 0x1F2) | 0x80, port: 0x1F2); |
923 | inb(port: 0x1F5); |
924 | inb(port: 0x1F2); |
925 | inb(port: 0x3F6); |
926 | inb(port: 0x3F6); |
927 | inb(port: 0x1F2); |
928 | inb(port: 0x1F2); |
929 | |
930 | if ((inb(port: 0x1F2) & 0x80) == 0) { |
931 | /* PDC20230c or 20630 ? */ |
932 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" |
933 | " detected.\n" ); |
934 | udelay(100); |
935 | inb(port: 0x1F5); |
936 | local_irq_restore(flags); |
937 | return PDC20230; |
938 | } else { |
939 | outb(value: 0x55, port: 0x1F2); |
940 | inb(port: 0x1F2); |
941 | inb(port: 0x1F2); |
942 | if (inb(port: 0x1F2) == 0x00) |
943 | printk(KERN_INFO "PDC20230-B VLB ATA " |
944 | "controller detected.\n" ); |
945 | local_irq_restore(flags); |
946 | return BIOS; |
947 | } |
948 | } |
949 | |
950 | if (ht6560a & mask) |
951 | return HT6560A; |
952 | if (ht6560b & mask) |
953 | return HT6560B; |
954 | if (opti82c611a & mask) |
955 | return OPTI611A; |
956 | if (opti82c46x & mask) |
957 | return OPTI46X; |
958 | if (autospeed & mask) |
959 | return SNOOP; |
960 | return BIOS; |
961 | } |
962 | |
963 | |
964 | /** |
965 | * legacy_init_one - attach a legacy interface |
966 | * @probe: probe record |
967 | * |
968 | * Register an ISA bus IDE interface. Such interfaces are PIO and we |
969 | * assume do not support IRQ sharing. |
970 | */ |
971 | |
972 | static __init int legacy_init_one(struct legacy_probe *probe) |
973 | { |
974 | struct legacy_controller *controller = &controllers[probe->type]; |
975 | int pio_modes = controller->pio_mask; |
976 | unsigned long io = probe->port; |
977 | u32 mask = (1 << probe->slot); |
978 | struct ata_port_operations *ops = controller->ops; |
979 | struct legacy_data *ld = &legacy_data[probe->slot]; |
980 | struct ata_host *host = NULL; |
981 | struct ata_port *ap; |
982 | struct platform_device *pdev; |
983 | struct ata_device *dev; |
984 | void __iomem *io_addr, *ctrl_addr; |
985 | u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; |
986 | int ret; |
987 | |
988 | iordy |= controller->flags; |
989 | |
990 | pdev = platform_device_register_simple(DRV_NAME, id: probe->slot, NULL, num: 0); |
991 | if (IS_ERR(ptr: pdev)) |
992 | return PTR_ERR(ptr: pdev); |
993 | |
994 | ret = -EBUSY; |
995 | if (devm_request_region(&pdev->dev, io, 8, "pata_legacy" ) == NULL || |
996 | devm_request_region(&pdev->dev, io + 0x0206, 1, |
997 | "pata_legacy" ) == NULL) |
998 | goto fail; |
999 | |
1000 | ret = -ENOMEM; |
1001 | io_addr = devm_ioport_map(dev: &pdev->dev, port: io, nr: 8); |
1002 | ctrl_addr = devm_ioport_map(dev: &pdev->dev, port: io + 0x0206, nr: 1); |
1003 | if (!io_addr || !ctrl_addr) |
1004 | goto fail; |
1005 | ld->type = probe->type; |
1006 | if (controller->setup) |
1007 | if (controller->setup(pdev, probe, ld) < 0) |
1008 | goto fail; |
1009 | host = ata_host_alloc(dev: &pdev->dev, max_ports: 1); |
1010 | if (!host) |
1011 | goto fail; |
1012 | ap = host->ports[0]; |
1013 | |
1014 | ap->ops = ops; |
1015 | ap->pio_mask = pio_modes; |
1016 | ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; |
1017 | ap->pflags |= controller->pflags; |
1018 | ap->ioaddr.cmd_addr = io_addr; |
1019 | ap->ioaddr.altstatus_addr = ctrl_addr; |
1020 | ap->ioaddr.ctl_addr = ctrl_addr; |
1021 | ata_sff_std_ports(ioaddr: &ap->ioaddr); |
1022 | ap->host->private_data = ld; |
1023 | |
1024 | ata_port_desc(ap, fmt: "cmd 0x%lx ctl 0x%lx" , io, io + 0x0206); |
1025 | |
1026 | ret = ata_host_activate(host, irq: probe->irq, irq_handler: ata_sff_interrupt, irq_flags: 0, |
1027 | sht: &legacy_sht); |
1028 | if (ret) |
1029 | goto fail; |
1030 | async_synchronize_full(); |
1031 | ld->platform_dev = pdev; |
1032 | |
1033 | /* Nothing found means we drop the port as its probably not there */ |
1034 | |
1035 | ret = -ENODEV; |
1036 | ata_for_each_dev(dev, &ap->link, ALL) { |
1037 | if (!ata_dev_absent(dev)) { |
1038 | legacy_host[probe->slot] = host; |
1039 | ld->platform_dev = pdev; |
1040 | return 0; |
1041 | } |
1042 | } |
1043 | ata_host_detach(host); |
1044 | fail: |
1045 | platform_device_unregister(pdev); |
1046 | return ret; |
1047 | } |
1048 | |
1049 | /** |
1050 | * legacy_check_special_cases - ATA special cases |
1051 | * @p: PCI device to check |
1052 | * @primary: set this if we find an ATA master |
1053 | * @secondary: set this if we find an ATA secondary |
1054 | * |
1055 | * A small number of vendors implemented early PCI ATA interfaces |
1056 | * on bridge logic without the ATA interface being PCI visible. |
1057 | * Where we have a matching PCI driver we must skip the relevant |
1058 | * device here. If we don't know about it then the legacy driver |
1059 | * is the right driver anyway. |
1060 | */ |
1061 | |
1062 | static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, |
1063 | int *secondary) |
1064 | { |
1065 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ |
1066 | if (p->vendor == 0x1078 && p->device == 0x0000) { |
1067 | *primary = *secondary = 1; |
1068 | return; |
1069 | } |
1070 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ |
1071 | if (p->vendor == 0x1078 && p->device == 0x0002) { |
1072 | *primary = *secondary = 1; |
1073 | return; |
1074 | } |
1075 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ |
1076 | if (p->vendor == 0x8086 && p->device == 0x1234) { |
1077 | u16 r; |
1078 | pci_read_config_word(dev: p, where: 0x6C, val: &r); |
1079 | if (r & 0x8000) { |
1080 | /* ATA port enabled */ |
1081 | if (r & 0x4000) |
1082 | *secondary = 1; |
1083 | else |
1084 | *primary = 1; |
1085 | } |
1086 | return; |
1087 | } |
1088 | } |
1089 | |
1090 | static __init void probe_opti_vlb(void) |
1091 | { |
1092 | /* If an OPTI 82C46X is present find out where the channels are */ |
1093 | static const char *optis[4] = { |
1094 | "3/463MV" , "5MV" , |
1095 | "5MVA" , "5MVB" |
1096 | }; |
1097 | u8 chans = 1; |
1098 | u8 ctrl = (opti_syscfg(reg: 0x30) & 0xC0) >> 6; |
1099 | |
1100 | opti82c46x = 3; /* Assume master and slave first */ |
1101 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n" , |
1102 | optis[ctrl]); |
1103 | if (ctrl == 3) |
1104 | chans = (opti_syscfg(reg: 0x3F) & 0x20) ? 2 : 1; |
1105 | ctrl = opti_syscfg(reg: 0xAC); |
1106 | /* Check enabled and this port is the 465MV port. On the |
1107 | MVB we may have two channels */ |
1108 | if (ctrl & 8) { |
1109 | if (chans == 2) { |
1110 | legacy_probe_add(port: 0x1F0, irq: 14, type: OPTI46X, private: 0); |
1111 | legacy_probe_add(port: 0x170, irq: 15, type: OPTI46X, private: 0); |
1112 | } |
1113 | if (ctrl & 4) |
1114 | legacy_probe_add(port: 0x170, irq: 15, type: OPTI46X, private: 0); |
1115 | else |
1116 | legacy_probe_add(port: 0x1F0, irq: 14, type: OPTI46X, private: 0); |
1117 | } else |
1118 | legacy_probe_add(port: 0x1F0, irq: 14, type: OPTI46X, private: 0); |
1119 | } |
1120 | |
1121 | static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) |
1122 | { |
1123 | static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; |
1124 | /* Check card type */ |
1125 | if ((r & 0xF0) == 0xC0) { |
1126 | /* QD6500: single channel */ |
1127 | if (r & 8) |
1128 | /* Disabled ? */ |
1129 | return; |
1130 | legacy_probe_add(port: ide_port[r & 0x01], irq: 14 + (r & 0x01), |
1131 | type: QDI6500, private: port); |
1132 | } |
1133 | if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { |
1134 | /* QD6580: dual channel */ |
1135 | if (!request_region(port + 2 , 2, "pata_qdi" )) { |
1136 | release_region(port, 2); |
1137 | return; |
1138 | } |
1139 | res = inb(port: port + 3); |
1140 | /* Single channel mode ? */ |
1141 | if (res & 1) |
1142 | legacy_probe_add(port: ide_port[r & 0x01], irq: 14 + (r & 0x01), |
1143 | type: QDI6580, private: port); |
1144 | else { /* Dual channel mode */ |
1145 | legacy_probe_add(port: 0x1F0, irq: 14, type: QDI6580DP, private: port); |
1146 | /* port + 0x02, r & 0x04 */ |
1147 | legacy_probe_add(port: 0x170, irq: 15, type: QDI6580DP, private: port + 2); |
1148 | } |
1149 | release_region(port + 2, 2); |
1150 | } |
1151 | } |
1152 | |
1153 | static __init void probe_qdi_vlb(void) |
1154 | { |
1155 | unsigned long flags; |
1156 | static const unsigned long qd_port[2] = { 0x30, 0xB0 }; |
1157 | int i; |
1158 | |
1159 | /* |
1160 | * Check each possible QD65xx base address |
1161 | */ |
1162 | |
1163 | for (i = 0; i < 2; i++) { |
1164 | unsigned long port = qd_port[i]; |
1165 | u8 r, res; |
1166 | |
1167 | |
1168 | if (request_region(port, 2, "pata_qdi" )) { |
1169 | /* Check for a card */ |
1170 | local_irq_save(flags); |
1171 | /* I have no h/w that needs this delay but it |
1172 | is present in the historic code */ |
1173 | r = inb(port); |
1174 | udelay(1); |
1175 | outb(value: 0x19, port); |
1176 | udelay(1); |
1177 | res = inb(port); |
1178 | udelay(1); |
1179 | outb(value: r, port); |
1180 | udelay(1); |
1181 | local_irq_restore(flags); |
1182 | |
1183 | /* Fail */ |
1184 | if (res == 0x19) { |
1185 | release_region(port, 2); |
1186 | continue; |
1187 | } |
1188 | /* Passes the presence test */ |
1189 | r = inb(port: port + 1); |
1190 | udelay(1); |
1191 | /* Check port agrees with port set */ |
1192 | if ((r & 2) >> 1 == i) |
1193 | qdi65_identify_port(r, res, port); |
1194 | release_region(port, 2); |
1195 | } |
1196 | } |
1197 | } |
1198 | |
1199 | /** |
1200 | * legacy_init - attach legacy interfaces |
1201 | * |
1202 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. |
1203 | * Right now we do not scan the ide0 and ide1 address but should do so |
1204 | * for non PCI systems or systems with no PCI IDE legacy mode devices. |
1205 | * If you fix that note there are special cases to consider like VLB |
1206 | * drivers and CS5510/20. |
1207 | */ |
1208 | |
1209 | static __init int legacy_init(void) |
1210 | { |
1211 | int i; |
1212 | int ct = 0; |
1213 | int primary = 0; |
1214 | int secondary = 0; |
1215 | int pci_present = 0; |
1216 | struct legacy_probe *pl = &probe_list[0]; |
1217 | int slot = 0; |
1218 | |
1219 | struct pci_dev *p = NULL; |
1220 | |
1221 | for_each_pci_dev(p) { |
1222 | int r; |
1223 | /* Check for any overlap of the system ATA mappings. Native |
1224 | mode controllers stuck on these addresses or some devices |
1225 | in 'raid' mode won't be found by the storage class test */ |
1226 | for (r = 0; r < 6; r++) { |
1227 | if (pci_resource_start(p, r) == 0x1f0) |
1228 | primary = 1; |
1229 | if (pci_resource_start(p, r) == 0x170) |
1230 | secondary = 1; |
1231 | } |
1232 | /* Check for special cases */ |
1233 | legacy_check_special_cases(p, primary: &primary, secondary: &secondary); |
1234 | |
1235 | /* If PCI bus is present then don't probe for tertiary |
1236 | legacy ports */ |
1237 | pci_present = 1; |
1238 | } |
1239 | |
1240 | if (winbond == 1) |
1241 | winbond = 0x130; /* Default port, alt is 1B0 */ |
1242 | |
1243 | if (primary == 0 || all) |
1244 | legacy_probe_add(port: 0x1F0, irq: 14, type: UNKNOWN, private: 0); |
1245 | if (secondary == 0 || all) |
1246 | legacy_probe_add(port: 0x170, irq: 15, type: UNKNOWN, private: 0); |
1247 | |
1248 | if (probe_all || !pci_present) { |
1249 | /* ISA/VLB extra ports */ |
1250 | legacy_probe_add(port: 0x1E8, irq: 11, type: UNKNOWN, private: 0); |
1251 | legacy_probe_add(port: 0x168, irq: 10, type: UNKNOWN, private: 0); |
1252 | legacy_probe_add(port: 0x1E0, irq: 8, type: UNKNOWN, private: 0); |
1253 | legacy_probe_add(port: 0x160, irq: 12, type: UNKNOWN, private: 0); |
1254 | } |
1255 | |
1256 | if (opti82c46x) |
1257 | probe_opti_vlb(); |
1258 | if (qdi) |
1259 | probe_qdi_vlb(); |
1260 | |
1261 | for (i = 0; i < NR_HOST; i++, pl++) { |
1262 | if (pl->port == 0) |
1263 | continue; |
1264 | if (pl->type == UNKNOWN) |
1265 | pl->type = probe_chip_type(probe: pl); |
1266 | pl->slot = slot++; |
1267 | if (legacy_init_one(probe: pl) == 0) |
1268 | ct++; |
1269 | } |
1270 | if (ct != 0) |
1271 | return 0; |
1272 | return -ENODEV; |
1273 | } |
1274 | |
1275 | static __exit void legacy_exit(void) |
1276 | { |
1277 | int i; |
1278 | |
1279 | for (i = 0; i < nr_legacy_host; i++) { |
1280 | struct legacy_data *ld = &legacy_data[i]; |
1281 | ata_host_detach(host: legacy_host[i]); |
1282 | platform_device_unregister(ld->platform_dev); |
1283 | } |
1284 | } |
1285 | |
1286 | MODULE_AUTHOR("Alan Cox" ); |
1287 | MODULE_DESCRIPTION("low-level driver for legacy ATA" ); |
1288 | MODULE_LICENSE("GPL" ); |
1289 | MODULE_VERSION(DRV_VERSION); |
1290 | MODULE_ALIAS("pata_qdi" ); |
1291 | MODULE_ALIAS("pata_winbond" ); |
1292 | |
1293 | module_init(legacy_init); |
1294 | module_exit(legacy_exit); |
1295 | |