1 | /* |
2 | * pata-legacy.c - Legacy port PATA/SATA controller driver. |
3 | * Copyright 2005/2006 Red Hat, all rights reserved. |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by |
7 | * the Free Software Foundation; either version 2, or (at your option) |
8 | * any later version. |
9 | * |
10 | * This program is distributed in the hope that it will be useful, |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
13 | * GNU General Public License for more details. |
14 | * |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; see the file COPYING. If not, write to |
17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
18 | * |
19 | * An ATA driver for the legacy ATA ports. |
20 | * |
21 | * Data Sources: |
22 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com |
23 | * HT6560 series: |
24 | * Promise 20230/20620: |
25 | * http://www.ryston.cz/petr/vlb/pdc20230b.html |
26 | * http://www.ryston.cz/petr/vlb/pdc20230c.html |
27 | * http://www.ryston.cz/petr/vlb/pdc20630.html |
28 | * QDI65x0: |
29 | * http://www.ryston.cz/petr/vlb/qd6500.html |
30 | * http://www.ryston.cz/petr/vlb/qd6580.html |
31 | * |
32 | * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c |
33 | * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by |
34 | * Samuel Thibault <samuel.thibault@ens-lyon.org> |
35 | * |
36 | * Unsupported but docs exist: |
37 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 |
38 | * |
39 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found |
40 | * on PC class systems. There are three hybrid devices that are exceptions |
41 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and |
42 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". |
43 | * |
44 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ |
45 | * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A |
46 | * |
47 | * Support for the Winbond 83759A when operating in advanced mode. |
48 | * Multichip mode is not currently supported. |
49 | * |
50 | * Use the autospeed and pio_mask options with: |
51 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. |
52 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with |
53 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, |
54 | * Winbond W83759A, Promise PDC20230-B |
55 | * |
56 | * For now use autospeed and pio_mask as above with the W83759A. This may |
57 | * change. |
58 | * |
59 | */ |
60 | |
61 | #include <linux/async.h> |
62 | #include <linux/kernel.h> |
63 | #include <linux/module.h> |
64 | #include <linux/pci.h> |
65 | #include <linux/init.h> |
66 | #include <linux/blkdev.h> |
67 | #include <linux/delay.h> |
68 | #include <scsi/scsi_host.h> |
69 | #include <linux/ata.h> |
70 | #include <linux/libata.h> |
71 | #include <linux/platform_device.h> |
72 | |
73 | #define DRV_NAME "pata_legacy" |
74 | #define DRV_VERSION "0.6.5" |
75 | |
76 | #define NR_HOST 6 |
77 | |
78 | static int all; |
79 | module_param(all, int, 0444); |
80 | MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)" ); |
81 | |
82 | enum controller { |
83 | BIOS = 0, |
84 | SNOOP = 1, |
85 | PDC20230 = 2, |
86 | HT6560A = 3, |
87 | HT6560B = 4, |
88 | OPTI611A = 5, |
89 | OPTI46X = 6, |
90 | QDI6500 = 7, |
91 | QDI6580 = 8, |
92 | QDI6580DP = 9, /* Dual channel mode is different */ |
93 | W83759A = 10, |
94 | |
95 | UNKNOWN = -1 |
96 | }; |
97 | |
98 | struct legacy_data { |
99 | unsigned long timing; |
100 | u8 clock[2]; |
101 | u8 last; |
102 | int fast; |
103 | enum controller type; |
104 | struct platform_device *platform_dev; |
105 | }; |
106 | |
107 | struct legacy_probe { |
108 | unsigned char *name; |
109 | unsigned long port; |
110 | unsigned int irq; |
111 | unsigned int slot; |
112 | enum controller type; |
113 | unsigned long private; |
114 | }; |
115 | |
116 | struct legacy_controller { |
117 | const char *name; |
118 | struct ata_port_operations *ops; |
119 | unsigned int pio_mask; |
120 | unsigned int flags; |
121 | unsigned int pflags; |
122 | int (*setup)(struct platform_device *, struct legacy_probe *probe, |
123 | struct legacy_data *data); |
124 | }; |
125 | |
126 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; |
127 | |
128 | static struct legacy_probe probe_list[NR_HOST]; |
129 | static struct legacy_data legacy_data[NR_HOST]; |
130 | static struct ata_host *legacy_host[NR_HOST]; |
131 | static int nr_legacy_host; |
132 | |
133 | |
134 | static int probe_all; /* Set to check all ISA port ranges */ |
135 | static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ |
136 | static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ |
137 | static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ |
138 | static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ |
139 | static int autospeed; /* Chip present which snoops speed changes */ |
140 | static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */ |
141 | static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ |
142 | |
143 | /* Set to probe QDI controllers */ |
144 | #ifdef CONFIG_PATA_QDI_MODULE |
145 | static int qdi = 1; |
146 | #else |
147 | static int qdi; |
148 | #endif |
149 | |
150 | #ifdef CONFIG_PATA_WINBOND_VLB_MODULE |
151 | static int winbond = 1; /* Set to probe Winbond controllers, |
152 | give I/O port if non standard */ |
153 | #else |
154 | static int winbond; /* Set to probe Winbond controllers, |
155 | give I/O port if non standard */ |
156 | #endif |
157 | |
158 | /** |
159 | * legacy_probe_add - Add interface to probe list |
160 | * @port: Controller port |
161 | * @irq: IRQ number |
162 | * @type: Controller type |
163 | * @private: Controller specific info |
164 | * |
165 | * Add an entry into the probe list for ATA controllers. This is used |
166 | * to add the default ISA slots and then to build up the table |
167 | * further according to other ISA/VLB/Weird device scans |
168 | * |
169 | * An I/O port list is used to keep ordering stable and sane, as we |
170 | * don't have any good way to talk about ordering otherwise |
171 | */ |
172 | |
173 | static int legacy_probe_add(unsigned long port, unsigned int irq, |
174 | enum controller type, unsigned long private) |
175 | { |
176 | struct legacy_probe *lp = &probe_list[0]; |
177 | int i; |
178 | struct legacy_probe *free = NULL; |
179 | |
180 | for (i = 0; i < NR_HOST; i++) { |
181 | if (lp->port == 0 && free == NULL) |
182 | free = lp; |
183 | /* Matching port, or the correct slot for ordering */ |
184 | if (lp->port == port || legacy_port[i] == port) { |
185 | free = lp; |
186 | break; |
187 | } |
188 | lp++; |
189 | } |
190 | if (free == NULL) { |
191 | printk(KERN_ERR "pata_legacy: Too many interfaces.\n" ); |
192 | return -1; |
193 | } |
194 | /* Fill in the entry for later probing */ |
195 | free->port = port; |
196 | free->irq = irq; |
197 | free->type = type; |
198 | free->private = private; |
199 | return 0; |
200 | } |
201 | |
202 | |
203 | /** |
204 | * legacy_set_mode - mode setting |
205 | * @link: IDE link |
206 | * @unused: Device that failed when error is returned |
207 | * |
208 | * Use a non standard set_mode function. We don't want to be tuned. |
209 | * |
210 | * The BIOS configured everything. Our job is not to fiddle. Just use |
211 | * whatever PIO the hardware is using and leave it at that. When we |
212 | * get some kind of nice user driven API for control then we can |
213 | * expand on this as per hdparm in the base kernel. |
214 | */ |
215 | |
216 | static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) |
217 | { |
218 | struct ata_device *dev; |
219 | |
220 | ata_for_each_dev(dev, link, ENABLED) { |
221 | ata_dev_info(dev, "configured for PIO\n" ); |
222 | dev->pio_mode = XFER_PIO_0; |
223 | dev->xfer_mode = XFER_PIO_0; |
224 | dev->xfer_shift = ATA_SHIFT_PIO; |
225 | dev->flags |= ATA_DFLAG_PIO; |
226 | } |
227 | return 0; |
228 | } |
229 | |
230 | static struct scsi_host_template legacy_sht = { |
231 | ATA_PIO_SHT(DRV_NAME), |
232 | }; |
233 | |
234 | static const struct ata_port_operations legacy_base_port_ops = { |
235 | .inherits = &ata_sff_port_ops, |
236 | .cable_detect = ata_cable_40wire, |
237 | }; |
238 | |
239 | /* |
240 | * These ops are used if the user indicates the hardware |
241 | * snoops the commands to decide on the mode and handles the |
242 | * mode selection "magically" itself. Several legacy controllers |
243 | * do this. The mode range can be set if it is not 0x1F by setting |
244 | * pio_mask as well. |
245 | */ |
246 | |
247 | static struct ata_port_operations simple_port_ops = { |
248 | .inherits = &legacy_base_port_ops, |
249 | .sff_data_xfer = ata_sff_data_xfer32, |
250 | }; |
251 | |
252 | static struct ata_port_operations legacy_port_ops = { |
253 | .inherits = &legacy_base_port_ops, |
254 | .sff_data_xfer = ata_sff_data_xfer32, |
255 | .set_mode = legacy_set_mode, |
256 | }; |
257 | |
258 | /* |
259 | * Promise 20230C and 20620 support |
260 | * |
261 | * This controller supports PIO0 to PIO2. We set PIO timings |
262 | * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA |
263 | * support is weird being DMA to controller and PIO'd to the host |
264 | * and not supported. |
265 | */ |
266 | |
267 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) |
268 | { |
269 | int tries = 5; |
270 | int pio = adev->pio_mode - XFER_PIO_0; |
271 | u8 rt; |
272 | unsigned long flags; |
273 | |
274 | /* Safe as UP only. Force I/Os to occur together */ |
275 | |
276 | local_irq_save(flags); |
277 | |
278 | /* Unlock the control interface */ |
279 | do { |
280 | inb(0x1F5); |
281 | outb(inb(0x1F2) | 0x80, 0x1F2); |
282 | inb(0x1F2); |
283 | inb(0x3F6); |
284 | inb(0x3F6); |
285 | inb(0x1F2); |
286 | inb(0x1F2); |
287 | } |
288 | while ((inb(0x1F2) & 0x80) && --tries); |
289 | |
290 | local_irq_restore(flags); |
291 | |
292 | outb(inb(0x1F4) & 0x07, 0x1F4); |
293 | |
294 | rt = inb(0x1F3); |
295 | rt &= 0x07 << (3 * adev->devno); |
296 | if (pio) |
297 | rt |= (1 + 3 * pio) << (3 * adev->devno); |
298 | |
299 | udelay(100); |
300 | outb(inb(0x1F2) | 0x01, 0x1F2); |
301 | udelay(100); |
302 | inb(0x1F5); |
303 | |
304 | } |
305 | |
306 | static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc, |
307 | unsigned char *buf, unsigned int buflen, int rw) |
308 | { |
309 | struct ata_device *dev = qc->dev; |
310 | struct ata_port *ap = dev->link->ap; |
311 | int slop = buflen & 3; |
312 | |
313 | /* 32bit I/O capable *and* we need to write a whole number of dwords */ |
314 | if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) |
315 | && (ap->pflags & ATA_PFLAG_PIO32)) { |
316 | unsigned long flags; |
317 | |
318 | local_irq_save(flags); |
319 | |
320 | /* Perform the 32bit I/O synchronization sequence */ |
321 | ioread8(ap->ioaddr.nsect_addr); |
322 | ioread8(ap->ioaddr.nsect_addr); |
323 | ioread8(ap->ioaddr.nsect_addr); |
324 | |
325 | /* Now the data */ |
326 | if (rw == READ) |
327 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
328 | else |
329 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
330 | |
331 | if (unlikely(slop)) { |
332 | __le32 pad; |
333 | if (rw == READ) { |
334 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
335 | memcpy(buf + buflen - slop, &pad, slop); |
336 | } else { |
337 | memcpy(&pad, buf + buflen - slop, slop); |
338 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
339 | } |
340 | buflen += 4 - slop; |
341 | } |
342 | local_irq_restore(flags); |
343 | } else |
344 | buflen = ata_sff_data_xfer32(qc, buf, buflen, rw); |
345 | |
346 | return buflen; |
347 | } |
348 | |
349 | static struct ata_port_operations pdc20230_port_ops = { |
350 | .inherits = &legacy_base_port_ops, |
351 | .set_piomode = pdc20230_set_piomode, |
352 | .sff_data_xfer = pdc_data_xfer_vlb, |
353 | }; |
354 | |
355 | /* |
356 | * Holtek 6560A support |
357 | * |
358 | * This controller supports PIO0 to PIO2 (no IORDY even though higher |
359 | * timings can be loaded). |
360 | */ |
361 | |
362 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) |
363 | { |
364 | u8 active, recover; |
365 | struct ata_timing t; |
366 | |
367 | /* Get the timing data in cycles. For now play safe at 50Mhz */ |
368 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
369 | |
370 | active = clamp_val(t.active, 2, 15); |
371 | recover = clamp_val(t.recover, 4, 15); |
372 | |
373 | inb(0x3E6); |
374 | inb(0x3E6); |
375 | inb(0x3E6); |
376 | inb(0x3E6); |
377 | |
378 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
379 | ioread8(ap->ioaddr.status_addr); |
380 | } |
381 | |
382 | static struct ata_port_operations ht6560a_port_ops = { |
383 | .inherits = &legacy_base_port_ops, |
384 | .set_piomode = ht6560a_set_piomode, |
385 | }; |
386 | |
387 | /* |
388 | * Holtek 6560B support |
389 | * |
390 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO |
391 | * setting unless we see an ATAPI device in which case we force it off. |
392 | * |
393 | * FIXME: need to implement 2nd channel support. |
394 | */ |
395 | |
396 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) |
397 | { |
398 | u8 active, recover; |
399 | struct ata_timing t; |
400 | |
401 | /* Get the timing data in cycles. For now play safe at 50Mhz */ |
402 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
403 | |
404 | active = clamp_val(t.active, 2, 15); |
405 | recover = clamp_val(t.recover, 2, 16) & 0x0F; |
406 | |
407 | inb(0x3E6); |
408 | inb(0x3E6); |
409 | inb(0x3E6); |
410 | inb(0x3E6); |
411 | |
412 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
413 | |
414 | if (adev->class != ATA_DEV_ATA) { |
415 | u8 rconf = inb(0x3E6); |
416 | if (rconf & 0x24) { |
417 | rconf &= ~0x24; |
418 | outb(rconf, 0x3E6); |
419 | } |
420 | } |
421 | ioread8(ap->ioaddr.status_addr); |
422 | } |
423 | |
424 | static struct ata_port_operations ht6560b_port_ops = { |
425 | .inherits = &legacy_base_port_ops, |
426 | .set_piomode = ht6560b_set_piomode, |
427 | }; |
428 | |
429 | /* |
430 | * Opti core chipset helpers |
431 | */ |
432 | |
433 | /** |
434 | * opti_syscfg - read OPTI chipset configuration |
435 | * @reg: Configuration register to read |
436 | * |
437 | * Returns the value of an OPTI system board configuration register. |
438 | */ |
439 | |
440 | static u8 opti_syscfg(u8 reg) |
441 | { |
442 | unsigned long flags; |
443 | u8 r; |
444 | |
445 | /* Uniprocessor chipset and must force cycles adjancent */ |
446 | local_irq_save(flags); |
447 | outb(reg, 0x22); |
448 | r = inb(0x24); |
449 | local_irq_restore(flags); |
450 | return r; |
451 | } |
452 | |
453 | /* |
454 | * Opti 82C611A |
455 | * |
456 | * This controller supports PIO0 to PIO3. |
457 | */ |
458 | |
459 | static void opti82c611a_set_piomode(struct ata_port *ap, |
460 | struct ata_device *adev) |
461 | { |
462 | u8 active, recover, setup; |
463 | struct ata_timing t; |
464 | struct ata_device *pair = ata_dev_pair(adev); |
465 | int clock; |
466 | int khz[4] = { 50000, 40000, 33000, 25000 }; |
467 | u8 rc; |
468 | |
469 | /* Enter configuration mode */ |
470 | ioread16(ap->ioaddr.error_addr); |
471 | ioread16(ap->ioaddr.error_addr); |
472 | iowrite8(3, ap->ioaddr.nsect_addr); |
473 | |
474 | /* Read VLB clock strapping */ |
475 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
476 | |
477 | /* Get the timing data in cycles */ |
478 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); |
479 | |
480 | /* Setup timing is shared */ |
481 | if (pair) { |
482 | struct ata_timing tp; |
483 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); |
484 | |
485 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); |
486 | } |
487 | |
488 | active = clamp_val(t.active, 2, 17) - 2; |
489 | recover = clamp_val(t.recover, 1, 16) - 1; |
490 | setup = clamp_val(t.setup, 1, 4) - 1; |
491 | |
492 | /* Select the right timing bank for write timing */ |
493 | rc = ioread8(ap->ioaddr.lbal_addr); |
494 | rc &= 0x7F; |
495 | rc |= (adev->devno << 7); |
496 | iowrite8(rc, ap->ioaddr.lbal_addr); |
497 | |
498 | /* Write the timings */ |
499 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
500 | |
501 | /* Select the right bank for read timings, also |
502 | load the shared timings for address */ |
503 | rc = ioread8(ap->ioaddr.device_addr); |
504 | rc &= 0xC0; |
505 | rc |= adev->devno; /* Index select */ |
506 | rc |= (setup << 4) | 0x04; |
507 | iowrite8(rc, ap->ioaddr.device_addr); |
508 | |
509 | /* Load the read timings */ |
510 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
511 | |
512 | /* Ensure the timing register mode is right */ |
513 | rc = ioread8(ap->ioaddr.lbal_addr); |
514 | rc &= 0x73; |
515 | rc |= 0x84; |
516 | iowrite8(rc, ap->ioaddr.lbal_addr); |
517 | |
518 | /* Exit command mode */ |
519 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
520 | } |
521 | |
522 | |
523 | static struct ata_port_operations opti82c611a_port_ops = { |
524 | .inherits = &legacy_base_port_ops, |
525 | .set_piomode = opti82c611a_set_piomode, |
526 | }; |
527 | |
528 | /* |
529 | * Opti 82C465MV |
530 | * |
531 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB |
532 | * version is dual channel but doesn't have a lot of unique registers. |
533 | */ |
534 | |
535 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) |
536 | { |
537 | u8 active, recover, setup; |
538 | struct ata_timing t; |
539 | struct ata_device *pair = ata_dev_pair(adev); |
540 | int clock; |
541 | int khz[4] = { 50000, 40000, 33000, 25000 }; |
542 | u8 rc; |
543 | u8 sysclk; |
544 | |
545 | /* Get the clock */ |
546 | sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */ |
547 | |
548 | /* Enter configuration mode */ |
549 | ioread16(ap->ioaddr.error_addr); |
550 | ioread16(ap->ioaddr.error_addr); |
551 | iowrite8(3, ap->ioaddr.nsect_addr); |
552 | |
553 | /* Read VLB clock strapping */ |
554 | clock = 1000000000 / khz[sysclk]; |
555 | |
556 | /* Get the timing data in cycles */ |
557 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); |
558 | |
559 | /* Setup timing is shared */ |
560 | if (pair) { |
561 | struct ata_timing tp; |
562 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); |
563 | |
564 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); |
565 | } |
566 | |
567 | active = clamp_val(t.active, 2, 17) - 2; |
568 | recover = clamp_val(t.recover, 1, 16) - 1; |
569 | setup = clamp_val(t.setup, 1, 4) - 1; |
570 | |
571 | /* Select the right timing bank for write timing */ |
572 | rc = ioread8(ap->ioaddr.lbal_addr); |
573 | rc &= 0x7F; |
574 | rc |= (adev->devno << 7); |
575 | iowrite8(rc, ap->ioaddr.lbal_addr); |
576 | |
577 | /* Write the timings */ |
578 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
579 | |
580 | /* Select the right bank for read timings, also |
581 | load the shared timings for address */ |
582 | rc = ioread8(ap->ioaddr.device_addr); |
583 | rc &= 0xC0; |
584 | rc |= adev->devno; /* Index select */ |
585 | rc |= (setup << 4) | 0x04; |
586 | iowrite8(rc, ap->ioaddr.device_addr); |
587 | |
588 | /* Load the read timings */ |
589 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
590 | |
591 | /* Ensure the timing register mode is right */ |
592 | rc = ioread8(ap->ioaddr.lbal_addr); |
593 | rc &= 0x73; |
594 | rc |= 0x84; |
595 | iowrite8(rc, ap->ioaddr.lbal_addr); |
596 | |
597 | /* Exit command mode */ |
598 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
599 | |
600 | /* We need to know this for quad device on the MVB */ |
601 | ap->host->private_data = ap; |
602 | } |
603 | |
604 | /** |
605 | * opt82c465mv_qc_issue - command issue |
606 | * @qc: command pending |
607 | * |
608 | * Called when the libata layer is about to issue a command. We wrap |
609 | * this interface so that we can load the correct ATA timings. The |
610 | * MVB has a single set of timing registers and these are shared |
611 | * across channels. As there are two registers we really ought to |
612 | * track the last two used values as a sort of register window. For |
613 | * now we just reload on a channel switch. On the single channel |
614 | * setup this condition never fires so we do nothing extra. |
615 | * |
616 | * FIXME: dual channel needs ->serialize support |
617 | */ |
618 | |
619 | static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) |
620 | { |
621 | struct ata_port *ap = qc->ap; |
622 | struct ata_device *adev = qc->dev; |
623 | |
624 | /* If timings are set and for the wrong channel (2nd test is |
625 | due to a libata shortcoming and will eventually go I hope) */ |
626 | if (ap->host->private_data != ap->host |
627 | && ap->host->private_data != NULL) |
628 | opti82c46x_set_piomode(ap, adev); |
629 | |
630 | return ata_sff_qc_issue(qc); |
631 | } |
632 | |
633 | static struct ata_port_operations opti82c46x_port_ops = { |
634 | .inherits = &legacy_base_port_ops, |
635 | .set_piomode = opti82c46x_set_piomode, |
636 | .qc_issue = opti82c46x_qc_issue, |
637 | }; |
638 | |
639 | /** |
640 | * qdi65x0_set_piomode - PIO setup for QDI65x0 |
641 | * @ap: Port |
642 | * @adev: Device |
643 | * |
644 | * In single channel mode the 6580 has one clock per device and we can |
645 | * avoid the requirement to clock switch. We also have to load the timing |
646 | * into the right clock according to whether we are master or slave. |
647 | * |
648 | * In dual channel mode the 6580 has one clock per channel and we have |
649 | * to software clockswitch in qc_issue. |
650 | */ |
651 | |
652 | static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev) |
653 | { |
654 | struct ata_timing t; |
655 | struct legacy_data *ld_qdi = ap->host->private_data; |
656 | int active, recovery; |
657 | u8 timing; |
658 | |
659 | /* Get the timing data in cycles */ |
660 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); |
661 | |
662 | if (ld_qdi->fast) { |
663 | active = 8 - clamp_val(t.active, 1, 8); |
664 | recovery = 18 - clamp_val(t.recover, 3, 18); |
665 | } else { |
666 | active = 9 - clamp_val(t.active, 2, 9); |
667 | recovery = 15 - clamp_val(t.recover, 0, 15); |
668 | } |
669 | timing = (recovery << 4) | active | 0x08; |
670 | ld_qdi->clock[adev->devno] = timing; |
671 | |
672 | if (ld_qdi->type == QDI6580) |
673 | outb(timing, ld_qdi->timing + 2 * adev->devno); |
674 | else |
675 | outb(timing, ld_qdi->timing + 2 * ap->port_no); |
676 | |
677 | /* Clear the FIFO */ |
678 | if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA) |
679 | outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); |
680 | } |
681 | |
682 | /** |
683 | * qdi_qc_issue - command issue |
684 | * @qc: command pending |
685 | * |
686 | * Called when the libata layer is about to issue a command. We wrap |
687 | * this interface so that we can load the correct ATA timings. |
688 | */ |
689 | |
690 | static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) |
691 | { |
692 | struct ata_port *ap = qc->ap; |
693 | struct ata_device *adev = qc->dev; |
694 | struct legacy_data *ld_qdi = ap->host->private_data; |
695 | |
696 | if (ld_qdi->clock[adev->devno] != ld_qdi->last) { |
697 | if (adev->pio_mode) { |
698 | ld_qdi->last = ld_qdi->clock[adev->devno]; |
699 | outb(ld_qdi->clock[adev->devno], ld_qdi->timing + |
700 | 2 * ap->port_no); |
701 | } |
702 | } |
703 | return ata_sff_qc_issue(qc); |
704 | } |
705 | |
706 | static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc, |
707 | unsigned char *buf, |
708 | unsigned int buflen, int rw) |
709 | { |
710 | struct ata_device *adev = qc->dev; |
711 | struct ata_port *ap = adev->link->ap; |
712 | int slop = buflen & 3; |
713 | |
714 | if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) |
715 | && (ap->pflags & ATA_PFLAG_PIO32)) { |
716 | if (rw == WRITE) |
717 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
718 | else |
719 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
720 | |
721 | if (unlikely(slop)) { |
722 | __le32 pad; |
723 | if (rw == WRITE) { |
724 | memcpy(&pad, buf + buflen - slop, slop); |
725 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
726 | } else { |
727 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
728 | memcpy(buf + buflen - slop, &pad, slop); |
729 | } |
730 | } |
731 | return (buflen + 3) & ~3; |
732 | } else |
733 | return ata_sff_data_xfer(qc, buf, buflen, rw); |
734 | } |
735 | |
736 | static int qdi_port(struct platform_device *dev, |
737 | struct legacy_probe *lp, struct legacy_data *ld) |
738 | { |
739 | if (devm_request_region(&dev->dev, lp->private, 4, "qdi" ) == NULL) |
740 | return -EBUSY; |
741 | ld->timing = lp->private; |
742 | return 0; |
743 | } |
744 | |
745 | static struct ata_port_operations qdi6500_port_ops = { |
746 | .inherits = &legacy_base_port_ops, |
747 | .set_piomode = qdi65x0_set_piomode, |
748 | .qc_issue = qdi_qc_issue, |
749 | .sff_data_xfer = vlb32_data_xfer, |
750 | }; |
751 | |
752 | static struct ata_port_operations qdi6580_port_ops = { |
753 | .inherits = &legacy_base_port_ops, |
754 | .set_piomode = qdi65x0_set_piomode, |
755 | .sff_data_xfer = vlb32_data_xfer, |
756 | }; |
757 | |
758 | static struct ata_port_operations qdi6580dp_port_ops = { |
759 | .inherits = &legacy_base_port_ops, |
760 | .set_piomode = qdi65x0_set_piomode, |
761 | .qc_issue = qdi_qc_issue, |
762 | .sff_data_xfer = vlb32_data_xfer, |
763 | }; |
764 | |
765 | static DEFINE_SPINLOCK(winbond_lock); |
766 | |
767 | static void winbond_writecfg(unsigned long port, u8 reg, u8 val) |
768 | { |
769 | unsigned long flags; |
770 | spin_lock_irqsave(&winbond_lock, flags); |
771 | outb(reg, port + 0x01); |
772 | outb(val, port + 0x02); |
773 | spin_unlock_irqrestore(&winbond_lock, flags); |
774 | } |
775 | |
776 | static u8 winbond_readcfg(unsigned long port, u8 reg) |
777 | { |
778 | u8 val; |
779 | |
780 | unsigned long flags; |
781 | spin_lock_irqsave(&winbond_lock, flags); |
782 | outb(reg, port + 0x01); |
783 | val = inb(port + 0x02); |
784 | spin_unlock_irqrestore(&winbond_lock, flags); |
785 | |
786 | return val; |
787 | } |
788 | |
789 | static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) |
790 | { |
791 | struct ata_timing t; |
792 | struct legacy_data *ld_winbond = ap->host->private_data; |
793 | int active, recovery; |
794 | u8 reg; |
795 | int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); |
796 | |
797 | reg = winbond_readcfg(ld_winbond->timing, 0x81); |
798 | |
799 | /* Get the timing data in cycles */ |
800 | if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ |
801 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
802 | else |
803 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); |
804 | |
805 | active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; |
806 | recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; |
807 | timing = (active << 4) | recovery; |
808 | winbond_writecfg(ld_winbond->timing, timing, reg); |
809 | |
810 | /* Load the setup timing */ |
811 | |
812 | reg = 0x35; |
813 | if (adev->class != ATA_DEV_ATA) |
814 | reg |= 0x08; /* FIFO off */ |
815 | if (!ata_pio_need_iordy(adev)) |
816 | reg |= 0x02; /* IORDY off */ |
817 | reg |= (clamp_val(t.setup, 0, 3) << 6); |
818 | winbond_writecfg(ld_winbond->timing, timing + 1, reg); |
819 | } |
820 | |
821 | static int winbond_port(struct platform_device *dev, |
822 | struct legacy_probe *lp, struct legacy_data *ld) |
823 | { |
824 | if (devm_request_region(&dev->dev, lp->private, 4, "winbond" ) == NULL) |
825 | return -EBUSY; |
826 | ld->timing = lp->private; |
827 | return 0; |
828 | } |
829 | |
830 | static struct ata_port_operations winbond_port_ops = { |
831 | .inherits = &legacy_base_port_ops, |
832 | .set_piomode = winbond_set_piomode, |
833 | .sff_data_xfer = vlb32_data_xfer, |
834 | }; |
835 | |
836 | static struct legacy_controller controllers[] = { |
837 | {"BIOS" , &legacy_port_ops, ATA_PIO4, |
838 | ATA_FLAG_NO_IORDY, 0, NULL }, |
839 | {"Snooping" , &simple_port_ops, ATA_PIO4, |
840 | 0, 0, NULL }, |
841 | {"PDC20230" , &pdc20230_port_ops, ATA_PIO2, |
842 | ATA_FLAG_NO_IORDY, |
843 | ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, |
844 | {"HT6560A" , &ht6560a_port_ops, ATA_PIO2, |
845 | ATA_FLAG_NO_IORDY, 0, NULL }, |
846 | {"HT6560B" , &ht6560b_port_ops, ATA_PIO4, |
847 | ATA_FLAG_NO_IORDY, 0, NULL }, |
848 | {"OPTI82C611A" , &opti82c611a_port_ops, ATA_PIO3, |
849 | 0, 0, NULL }, |
850 | {"OPTI82C46X" , &opti82c46x_port_ops, ATA_PIO3, |
851 | 0, 0, NULL }, |
852 | {"QDI6500" , &qdi6500_port_ops, ATA_PIO2, |
853 | ATA_FLAG_NO_IORDY, |
854 | ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
855 | {"QDI6580" , &qdi6580_port_ops, ATA_PIO4, |
856 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
857 | {"QDI6580DP" , &qdi6580dp_port_ops, ATA_PIO4, |
858 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
859 | {"W83759A" , &winbond_port_ops, ATA_PIO4, |
860 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, |
861 | winbond_port } |
862 | }; |
863 | |
864 | /** |
865 | * probe_chip_type - Discover controller |
866 | * @probe: Probe entry to check |
867 | * |
868 | * Probe an ATA port and identify the type of controller. We don't |
869 | * check if the controller appears to be driveless at this point. |
870 | */ |
871 | |
872 | static __init int probe_chip_type(struct legacy_probe *probe) |
873 | { |
874 | int mask = 1 << probe->slot; |
875 | |
876 | if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { |
877 | u8 reg = winbond_readcfg(winbond, 0x81); |
878 | reg |= 0x80; /* jumpered mode off */ |
879 | winbond_writecfg(winbond, 0x81, reg); |
880 | reg = winbond_readcfg(winbond, 0x83); |
881 | reg |= 0xF0; /* local control */ |
882 | winbond_writecfg(winbond, 0x83, reg); |
883 | reg = winbond_readcfg(winbond, 0x85); |
884 | reg |= 0xF0; /* programmable timing */ |
885 | winbond_writecfg(winbond, 0x85, reg); |
886 | |
887 | reg = winbond_readcfg(winbond, 0x81); |
888 | |
889 | if (reg & mask) |
890 | return W83759A; |
891 | } |
892 | if (probe->port == 0x1F0) { |
893 | unsigned long flags; |
894 | local_irq_save(flags); |
895 | /* Probes */ |
896 | outb(inb(0x1F2) | 0x80, 0x1F2); |
897 | inb(0x1F5); |
898 | inb(0x1F2); |
899 | inb(0x3F6); |
900 | inb(0x3F6); |
901 | inb(0x1F2); |
902 | inb(0x1F2); |
903 | |
904 | if ((inb(0x1F2) & 0x80) == 0) { |
905 | /* PDC20230c or 20630 ? */ |
906 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" |
907 | " detected.\n" ); |
908 | udelay(100); |
909 | inb(0x1F5); |
910 | local_irq_restore(flags); |
911 | return PDC20230; |
912 | } else { |
913 | outb(0x55, 0x1F2); |
914 | inb(0x1F2); |
915 | inb(0x1F2); |
916 | if (inb(0x1F2) == 0x00) |
917 | printk(KERN_INFO "PDC20230-B VLB ATA " |
918 | "controller detected.\n" ); |
919 | local_irq_restore(flags); |
920 | return BIOS; |
921 | } |
922 | } |
923 | |
924 | if (ht6560a & mask) |
925 | return HT6560A; |
926 | if (ht6560b & mask) |
927 | return HT6560B; |
928 | if (opti82c611a & mask) |
929 | return OPTI611A; |
930 | if (opti82c46x & mask) |
931 | return OPTI46X; |
932 | if (autospeed & mask) |
933 | return SNOOP; |
934 | return BIOS; |
935 | } |
936 | |
937 | |
938 | /** |
939 | * legacy_init_one - attach a legacy interface |
940 | * @pl: probe record |
941 | * |
942 | * Register an ISA bus IDE interface. Such interfaces are PIO and we |
943 | * assume do not support IRQ sharing. |
944 | */ |
945 | |
946 | static __init int legacy_init_one(struct legacy_probe *probe) |
947 | { |
948 | struct legacy_controller *controller = &controllers[probe->type]; |
949 | int pio_modes = controller->pio_mask; |
950 | unsigned long io = probe->port; |
951 | u32 mask = (1 << probe->slot); |
952 | struct ata_port_operations *ops = controller->ops; |
953 | struct legacy_data *ld = &legacy_data[probe->slot]; |
954 | struct ata_host *host = NULL; |
955 | struct ata_port *ap; |
956 | struct platform_device *pdev; |
957 | struct ata_device *dev; |
958 | void __iomem *io_addr, *ctrl_addr; |
959 | u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; |
960 | int ret; |
961 | |
962 | iordy |= controller->flags; |
963 | |
964 | pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); |
965 | if (IS_ERR(pdev)) |
966 | return PTR_ERR(pdev); |
967 | |
968 | ret = -EBUSY; |
969 | if (devm_request_region(&pdev->dev, io, 8, "pata_legacy" ) == NULL || |
970 | devm_request_region(&pdev->dev, io + 0x0206, 1, |
971 | "pata_legacy" ) == NULL) |
972 | goto fail; |
973 | |
974 | ret = -ENOMEM; |
975 | io_addr = devm_ioport_map(&pdev->dev, io, 8); |
976 | ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); |
977 | if (!io_addr || !ctrl_addr) |
978 | goto fail; |
979 | ld->type = probe->type; |
980 | if (controller->setup) |
981 | if (controller->setup(pdev, probe, ld) < 0) |
982 | goto fail; |
983 | host = ata_host_alloc(&pdev->dev, 1); |
984 | if (!host) |
985 | goto fail; |
986 | ap = host->ports[0]; |
987 | |
988 | ap->ops = ops; |
989 | ap->pio_mask = pio_modes; |
990 | ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; |
991 | ap->pflags |= controller->pflags; |
992 | ap->ioaddr.cmd_addr = io_addr; |
993 | ap->ioaddr.altstatus_addr = ctrl_addr; |
994 | ap->ioaddr.ctl_addr = ctrl_addr; |
995 | ata_sff_std_ports(&ap->ioaddr); |
996 | ap->host->private_data = ld; |
997 | |
998 | ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx" , io, io + 0x0206); |
999 | |
1000 | ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, |
1001 | &legacy_sht); |
1002 | if (ret) |
1003 | goto fail; |
1004 | async_synchronize_full(); |
1005 | ld->platform_dev = pdev; |
1006 | |
1007 | /* Nothing found means we drop the port as its probably not there */ |
1008 | |
1009 | ret = -ENODEV; |
1010 | ata_for_each_dev(dev, &ap->link, ALL) { |
1011 | if (!ata_dev_absent(dev)) { |
1012 | legacy_host[probe->slot] = host; |
1013 | ld->platform_dev = pdev; |
1014 | return 0; |
1015 | } |
1016 | } |
1017 | ata_host_detach(host); |
1018 | fail: |
1019 | platform_device_unregister(pdev); |
1020 | return ret; |
1021 | } |
1022 | |
1023 | /** |
1024 | * legacy_check_special_cases - ATA special cases |
1025 | * @p: PCI device to check |
1026 | * @master: set this if we find an ATA master |
1027 | * @master: set this if we find an ATA secondary |
1028 | * |
1029 | * A small number of vendors implemented early PCI ATA interfaces |
1030 | * on bridge logic without the ATA interface being PCI visible. |
1031 | * Where we have a matching PCI driver we must skip the relevant |
1032 | * device here. If we don't know about it then the legacy driver |
1033 | * is the right driver anyway. |
1034 | */ |
1035 | |
1036 | static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, |
1037 | int *secondary) |
1038 | { |
1039 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ |
1040 | if (p->vendor == 0x1078 && p->device == 0x0000) { |
1041 | *primary = *secondary = 1; |
1042 | return; |
1043 | } |
1044 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ |
1045 | if (p->vendor == 0x1078 && p->device == 0x0002) { |
1046 | *primary = *secondary = 1; |
1047 | return; |
1048 | } |
1049 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ |
1050 | if (p->vendor == 0x8086 && p->device == 0x1234) { |
1051 | u16 r; |
1052 | pci_read_config_word(p, 0x6C, &r); |
1053 | if (r & 0x8000) { |
1054 | /* ATA port enabled */ |
1055 | if (r & 0x4000) |
1056 | *secondary = 1; |
1057 | else |
1058 | *primary = 1; |
1059 | } |
1060 | return; |
1061 | } |
1062 | } |
1063 | |
1064 | static __init void probe_opti_vlb(void) |
1065 | { |
1066 | /* If an OPTI 82C46X is present find out where the channels are */ |
1067 | static const char *optis[4] = { |
1068 | "3/463MV" , "5MV" , |
1069 | "5MVA" , "5MVB" |
1070 | }; |
1071 | u8 chans = 1; |
1072 | u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; |
1073 | |
1074 | opti82c46x = 3; /* Assume master and slave first */ |
1075 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n" , |
1076 | optis[ctrl]); |
1077 | if (ctrl == 3) |
1078 | chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; |
1079 | ctrl = opti_syscfg(0xAC); |
1080 | /* Check enabled and this port is the 465MV port. On the |
1081 | MVB we may have two channels */ |
1082 | if (ctrl & 8) { |
1083 | if (chans == 2) { |
1084 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); |
1085 | legacy_probe_add(0x170, 15, OPTI46X, 0); |
1086 | } |
1087 | if (ctrl & 4) |
1088 | legacy_probe_add(0x170, 15, OPTI46X, 0); |
1089 | else |
1090 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); |
1091 | } else |
1092 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); |
1093 | } |
1094 | |
1095 | static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) |
1096 | { |
1097 | static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; |
1098 | /* Check card type */ |
1099 | if ((r & 0xF0) == 0xC0) { |
1100 | /* QD6500: single channel */ |
1101 | if (r & 8) |
1102 | /* Disabled ? */ |
1103 | return; |
1104 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), |
1105 | QDI6500, port); |
1106 | } |
1107 | if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { |
1108 | /* QD6580: dual channel */ |
1109 | if (!request_region(port + 2 , 2, "pata_qdi" )) { |
1110 | release_region(port, 2); |
1111 | return; |
1112 | } |
1113 | res = inb(port + 3); |
1114 | /* Single channel mode ? */ |
1115 | if (res & 1) |
1116 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), |
1117 | QDI6580, port); |
1118 | else { /* Dual channel mode */ |
1119 | legacy_probe_add(0x1F0, 14, QDI6580DP, port); |
1120 | /* port + 0x02, r & 0x04 */ |
1121 | legacy_probe_add(0x170, 15, QDI6580DP, port + 2); |
1122 | } |
1123 | release_region(port + 2, 2); |
1124 | } |
1125 | } |
1126 | |
1127 | static __init void probe_qdi_vlb(void) |
1128 | { |
1129 | unsigned long flags; |
1130 | static const unsigned long qd_port[2] = { 0x30, 0xB0 }; |
1131 | int i; |
1132 | |
1133 | /* |
1134 | * Check each possible QD65xx base address |
1135 | */ |
1136 | |
1137 | for (i = 0; i < 2; i++) { |
1138 | unsigned long port = qd_port[i]; |
1139 | u8 r, res; |
1140 | |
1141 | |
1142 | if (request_region(port, 2, "pata_qdi" )) { |
1143 | /* Check for a card */ |
1144 | local_irq_save(flags); |
1145 | /* I have no h/w that needs this delay but it |
1146 | is present in the historic code */ |
1147 | r = inb(port); |
1148 | udelay(1); |
1149 | outb(0x19, port); |
1150 | udelay(1); |
1151 | res = inb(port); |
1152 | udelay(1); |
1153 | outb(r, port); |
1154 | udelay(1); |
1155 | local_irq_restore(flags); |
1156 | |
1157 | /* Fail */ |
1158 | if (res == 0x19) { |
1159 | release_region(port, 2); |
1160 | continue; |
1161 | } |
1162 | /* Passes the presence test */ |
1163 | r = inb(port + 1); |
1164 | udelay(1); |
1165 | /* Check port agrees with port set */ |
1166 | if ((r & 2) >> 1 == i) |
1167 | qdi65_identify_port(r, res, port); |
1168 | release_region(port, 2); |
1169 | } |
1170 | } |
1171 | } |
1172 | |
1173 | /** |
1174 | * legacy_init - attach legacy interfaces |
1175 | * |
1176 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. |
1177 | * Right now we do not scan the ide0 and ide1 address but should do so |
1178 | * for non PCI systems or systems with no PCI IDE legacy mode devices. |
1179 | * If you fix that note there are special cases to consider like VLB |
1180 | * drivers and CS5510/20. |
1181 | */ |
1182 | |
1183 | static __init int legacy_init(void) |
1184 | { |
1185 | int i; |
1186 | int ct = 0; |
1187 | int primary = 0; |
1188 | int secondary = 0; |
1189 | int pci_present = 0; |
1190 | struct legacy_probe *pl = &probe_list[0]; |
1191 | int slot = 0; |
1192 | |
1193 | struct pci_dev *p = NULL; |
1194 | |
1195 | for_each_pci_dev(p) { |
1196 | int r; |
1197 | /* Check for any overlap of the system ATA mappings. Native |
1198 | mode controllers stuck on these addresses or some devices |
1199 | in 'raid' mode won't be found by the storage class test */ |
1200 | for (r = 0; r < 6; r++) { |
1201 | if (pci_resource_start(p, r) == 0x1f0) |
1202 | primary = 1; |
1203 | if (pci_resource_start(p, r) == 0x170) |
1204 | secondary = 1; |
1205 | } |
1206 | /* Check for special cases */ |
1207 | legacy_check_special_cases(p, &primary, &secondary); |
1208 | |
1209 | /* If PCI bus is present then don't probe for tertiary |
1210 | legacy ports */ |
1211 | pci_present = 1; |
1212 | } |
1213 | |
1214 | if (winbond == 1) |
1215 | winbond = 0x130; /* Default port, alt is 1B0 */ |
1216 | |
1217 | if (primary == 0 || all) |
1218 | legacy_probe_add(0x1F0, 14, UNKNOWN, 0); |
1219 | if (secondary == 0 || all) |
1220 | legacy_probe_add(0x170, 15, UNKNOWN, 0); |
1221 | |
1222 | if (probe_all || !pci_present) { |
1223 | /* ISA/VLB extra ports */ |
1224 | legacy_probe_add(0x1E8, 11, UNKNOWN, 0); |
1225 | legacy_probe_add(0x168, 10, UNKNOWN, 0); |
1226 | legacy_probe_add(0x1E0, 8, UNKNOWN, 0); |
1227 | legacy_probe_add(0x160, 12, UNKNOWN, 0); |
1228 | } |
1229 | |
1230 | if (opti82c46x) |
1231 | probe_opti_vlb(); |
1232 | if (qdi) |
1233 | probe_qdi_vlb(); |
1234 | |
1235 | for (i = 0; i < NR_HOST; i++, pl++) { |
1236 | if (pl->port == 0) |
1237 | continue; |
1238 | if (pl->type == UNKNOWN) |
1239 | pl->type = probe_chip_type(pl); |
1240 | pl->slot = slot++; |
1241 | if (legacy_init_one(pl) == 0) |
1242 | ct++; |
1243 | } |
1244 | if (ct != 0) |
1245 | return 0; |
1246 | return -ENODEV; |
1247 | } |
1248 | |
1249 | static __exit void legacy_exit(void) |
1250 | { |
1251 | int i; |
1252 | |
1253 | for (i = 0; i < nr_legacy_host; i++) { |
1254 | struct legacy_data *ld = &legacy_data[i]; |
1255 | ata_host_detach(legacy_host[i]); |
1256 | platform_device_unregister(ld->platform_dev); |
1257 | } |
1258 | } |
1259 | |
1260 | MODULE_AUTHOR("Alan Cox" ); |
1261 | MODULE_DESCRIPTION("low-level driver for legacy ATA" ); |
1262 | MODULE_LICENSE("GPL" ); |
1263 | MODULE_VERSION(DRV_VERSION); |
1264 | MODULE_ALIAS("pata_qdi" ); |
1265 | MODULE_ALIAS("pata_winbond" ); |
1266 | |
1267 | module_param(probe_all, int, 0); |
1268 | module_param(autospeed, int, 0); |
1269 | module_param(ht6560a, int, 0); |
1270 | module_param(ht6560b, int, 0); |
1271 | module_param(opti82c611a, int, 0); |
1272 | module_param(opti82c46x, int, 0); |
1273 | module_param(qdi, int, 0); |
1274 | module_param(winbond, int, 0); |
1275 | module_param(pio_mask, int, 0); |
1276 | module_param(iordy_mask, int, 0); |
1277 | |
1278 | module_init(legacy_init); |
1279 | module_exit(legacy_exit); |
1280 | |