1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * pata_ninja32.c - Ninja32 PATA for new ATA layer |
4 | * (C) 2007 Red Hat Inc |
5 | * |
6 | * Note: The controller like many controllers has shared timings for |
7 | * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back |
8 | * in the dma_stop function. Thus we actually don't need a set_dmamode |
9 | * method as the PIO method is always called and will set the right PIO |
10 | * timing parameters. |
11 | * |
12 | * The Ninja32 Cardbus is not a generic SFF controller. Instead it is |
13 | * laid out as follows off BAR 0. This is based upon Mark Lord's delkin |
14 | * driver and the extensive analysis done by the BSD developers, notably |
15 | * ITOH Yasufumi. |
16 | * |
17 | * Base + 0x00 IRQ Status |
18 | * Base + 0x01 IRQ control |
19 | * Base + 0x02 Chipset control |
20 | * Base + 0x03 Unknown |
21 | * Base + 0x04 VDMA and reset control + wait bits |
22 | * Base + 0x08 BMIMBA |
23 | * Base + 0x0C DMA Length |
24 | * Base + 0x10 Taskfile |
25 | * Base + 0x18 BMDMA Status ? |
26 | * Base + 0x1C |
27 | * Base + 0x1D Bus master control |
28 | * bit 0 = enable |
29 | * bit 1 = 0 write/1 read |
30 | * bit 2 = 1 sgtable |
31 | * bit 3 = go |
32 | * bit 4-6 wait bits |
33 | * bit 7 = done |
34 | * Base + 0x1E AltStatus |
35 | * Base + 0x1F timing register |
36 | */ |
37 | |
38 | #include <linux/kernel.h> |
39 | #include <linux/module.h> |
40 | #include <linux/pci.h> |
41 | #include <linux/blkdev.h> |
42 | #include <linux/delay.h> |
43 | #include <scsi/scsi_host.h> |
44 | #include <linux/libata.h> |
45 | |
46 | #define DRV_NAME "pata_ninja32" |
47 | #define DRV_VERSION "0.1.5" |
48 | |
49 | |
50 | /** |
51 | * ninja32_set_piomode - set initial PIO mode data |
52 | * @ap: ATA interface |
53 | * @adev: ATA device |
54 | * |
55 | * Called to do the PIO mode setup. Our timing registers are shared |
56 | * but we want to set the PIO timing by default. |
57 | */ |
58 | |
59 | static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev) |
60 | { |
61 | static u16 pio_timing[5] = { |
62 | 0xd6, 0x85, 0x44, 0x33, 0x13 |
63 | }; |
64 | iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0], |
65 | ap->ioaddr.bmdma_addr + 0x1f); |
66 | ap->private_data = adev; |
67 | } |
68 | |
69 | |
70 | static void ninja32_dev_select(struct ata_port *ap, unsigned int device) |
71 | { |
72 | struct ata_device *adev = &ap->link.device[device]; |
73 | if (ap->private_data != adev) { |
74 | iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f); |
75 | ata_sff_dev_select(ap, device); |
76 | ninja32_set_piomode(ap, adev); |
77 | } |
78 | } |
79 | |
80 | static const struct scsi_host_template ninja32_sht = { |
81 | ATA_BMDMA_SHT(DRV_NAME), |
82 | }; |
83 | |
84 | static struct ata_port_operations ninja32_port_ops = { |
85 | .inherits = &ata_bmdma_port_ops, |
86 | .sff_dev_select = ninja32_dev_select, |
87 | .cable_detect = ata_cable_40wire, |
88 | .set_piomode = ninja32_set_piomode, |
89 | .sff_data_xfer = ata_sff_data_xfer32 |
90 | }; |
91 | |
92 | static void ninja32_program(void __iomem *base) |
93 | { |
94 | iowrite8(0x05, base + 0x01); /* Enable interrupt lines */ |
95 | iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */ |
96 | iowrite8(0x01, base + 0x03); /* Unknown */ |
97 | iowrite8(0x20, base + 0x04); /* WAIT0 */ |
98 | iowrite8(0x8f, base + 0x05); /* Unknown */ |
99 | iowrite8(0xa4, base + 0x1c); /* Unknown */ |
100 | iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */ |
101 | } |
102 | |
103 | static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
104 | { |
105 | struct ata_host *host; |
106 | struct ata_port *ap; |
107 | void __iomem *base; |
108 | int rc; |
109 | |
110 | host = ata_host_alloc(dev: &dev->dev, max_ports: 1); |
111 | if (!host) |
112 | return -ENOMEM; |
113 | ap = host->ports[0]; |
114 | |
115 | /* Set up the PCI device */ |
116 | rc = pcim_enable_device(pdev: dev); |
117 | if (rc) |
118 | return rc; |
119 | rc = pcim_iomap_regions(pdev: dev, mask: 1 << 0, DRV_NAME); |
120 | if (rc == -EBUSY) |
121 | pcim_pin_device(pdev: dev); |
122 | if (rc) |
123 | return rc; |
124 | |
125 | host->iomap = pcim_iomap_table(pdev: dev); |
126 | rc = dma_set_mask_and_coherent(dev: &dev->dev, ATA_DMA_MASK); |
127 | if (rc) |
128 | return rc; |
129 | pci_set_master(dev); |
130 | |
131 | /* Set up the register mappings. We use the I/O mapping as only the |
132 | older chips also have MMIO on BAR 1 */ |
133 | base = host->iomap[0]; |
134 | if (!base) |
135 | return -ENOMEM; |
136 | ap->ops = &ninja32_port_ops; |
137 | ap->pio_mask = ATA_PIO4; |
138 | ap->flags |= ATA_FLAG_SLAVE_POSS; |
139 | |
140 | ap->ioaddr.cmd_addr = base + 0x10; |
141 | ap->ioaddr.ctl_addr = base + 0x1E; |
142 | ap->ioaddr.altstatus_addr = base + 0x1E; |
143 | ap->ioaddr.bmdma_addr = base; |
144 | ata_sff_std_ports(ioaddr: &ap->ioaddr); |
145 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; |
146 | |
147 | ninja32_program(base); |
148 | /* FIXME: Should we disable them at remove ? */ |
149 | return ata_host_activate(host, irq: dev->irq, irq_handler: ata_bmdma_interrupt, |
150 | IRQF_SHARED, sht: &ninja32_sht); |
151 | } |
152 | |
153 | #ifdef CONFIG_PM_SLEEP |
154 | static int ninja32_reinit_one(struct pci_dev *pdev) |
155 | { |
156 | struct ata_host *host = pci_get_drvdata(pdev); |
157 | int rc; |
158 | |
159 | rc = ata_pci_device_do_resume(pdev); |
160 | if (rc) |
161 | return rc; |
162 | ninja32_program(base: host->iomap[0]); |
163 | ata_host_resume(host); |
164 | return 0; |
165 | } |
166 | #endif |
167 | |
168 | static const struct pci_device_id ninja32[] = { |
169 | { 0x10FC, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
170 | { 0x1145, 0x8008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
171 | { 0x1145, 0xf008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
172 | { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
173 | { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
174 | { 0x1145, 0xf02C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
175 | { }, |
176 | }; |
177 | |
178 | static struct pci_driver ninja32_pci_driver = { |
179 | .name = DRV_NAME, |
180 | .id_table = ninja32, |
181 | .probe = ninja32_init_one, |
182 | .remove = ata_pci_remove_one, |
183 | #ifdef CONFIG_PM_SLEEP |
184 | .suspend = ata_pci_device_suspend, |
185 | .resume = ninja32_reinit_one, |
186 | #endif |
187 | }; |
188 | |
189 | module_pci_driver(ninja32_pci_driver); |
190 | |
191 | MODULE_AUTHOR("Alan Cox" ); |
192 | MODULE_DESCRIPTION("low-level driver for Ninja32 ATA" ); |
193 | MODULE_LICENSE("GPL" ); |
194 | MODULE_DEVICE_TABLE(pci, ninja32); |
195 | MODULE_VERSION(DRV_VERSION); |
196 | |