1/*
2 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@lxorguk.ukuu.org.uk>
5 * (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
6 *
7 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
8 *
9 * First cut with LBA48/ATAPI
10 *
11 * TODO:
12 * Channel interlock/reset on both required ?
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pci.h>
18#include <linux/blkdev.h>
19#include <linux/delay.h>
20#include <scsi/scsi_host.h>
21#include <linux/libata.h>
22
23#define DRV_NAME "pata_pdc202xx_old"
24#define DRV_VERSION "0.4.3"
25
26static int pdc2026x_cable_detect(struct ata_port *ap)
27{
28 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
29 u16 cis;
30
31 pci_read_config_word(pdev, 0x50, &cis);
32 if (cis & (1 << (10 + ap->port_no)))
33 return ATA_CBL_PATA40;
34 return ATA_CBL_PATA80;
35}
36
37static void pdc202xx_exec_command(struct ata_port *ap,
38 const struct ata_taskfile *tf)
39{
40 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
41
42 iowrite8(tf->command, ap->ioaddr.command_addr);
43 ndelay(400);
44}
45
46static bool pdc202xx_irq_check(struct ata_port *ap)
47{
48 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
49 unsigned long master = pci_resource_start(pdev, 4);
50 u8 sc1d = inb(master + 0x1d);
51
52 if (ap->port_no) {
53 /*
54 * bit 7: error, bit 6: interrupting,
55 * bit 5: FIFO full, bit 4: FIFO empty
56 */
57 return sc1d & 0x40;
58 } else {
59 /*
60 * bit 3: error, bit 2: interrupting,
61 * bit 1: FIFO full, bit 0: FIFO empty
62 */
63 return sc1d & 0x04;
64 }
65}
66
67/**
68 * pdc202xx_configure_piomode - set chip PIO timing
69 * @ap: ATA interface
70 * @adev: ATA device
71 * @pio: PIO mode
72 *
73 * Called to do the PIO mode setup. Our timing registers are shared
74 * so a configure_dmamode call will undo any work we do here and vice
75 * versa
76 */
77
78static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
79{
80 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
81 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
82 static u16 pio_timing[5] = {
83 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
84 };
85 u8 r_ap, r_bp;
86
87 pci_read_config_byte(pdev, port, &r_ap);
88 pci_read_config_byte(pdev, port + 1, &r_bp);
89 r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
90 r_bp &= ~0x1F;
91 r_ap |= (pio_timing[pio] >> 8);
92 r_bp |= (pio_timing[pio] & 0xFF);
93
94 if (ata_pio_need_iordy(adev))
95 r_ap |= 0x20; /* IORDY enable */
96 if (adev->class == ATA_DEV_ATA)
97 r_ap |= 0x10; /* FIFO enable */
98 pci_write_config_byte(pdev, port, r_ap);
99 pci_write_config_byte(pdev, port + 1, r_bp);
100}
101
102/**
103 * pdc202xx_set_piomode - set initial PIO mode data
104 * @ap: ATA interface
105 * @adev: ATA device
106 *
107 * Called to do the PIO mode setup. Our timing registers are shared
108 * but we want to set the PIO timing by default.
109 */
110
111static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
112{
113 pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
114}
115
116/**
117 * pdc202xx_configure_dmamode - set DMA mode in chip
118 * @ap: ATA interface
119 * @adev: ATA device
120 *
121 * Load DMA cycle times into the chip ready for a DMA transfer
122 * to occur.
123 */
124
125static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
126{
127 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
128 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
129 static u8 udma_timing[6][2] = {
130 { 0x60, 0x03 }, /* 33 Mhz Clock */
131 { 0x40, 0x02 },
132 { 0x20, 0x01 },
133 { 0x40, 0x02 }, /* 66 Mhz Clock */
134 { 0x20, 0x01 },
135 { 0x20, 0x01 }
136 };
137 static u8 mdma_timing[3][2] = {
138 { 0xe0, 0x0f },
139 { 0x60, 0x04 },
140 { 0x60, 0x03 },
141 };
142 u8 r_bp, r_cp;
143
144 pci_read_config_byte(pdev, port + 1, &r_bp);
145 pci_read_config_byte(pdev, port + 2, &r_cp);
146
147 r_bp &= ~0xE0;
148 r_cp &= ~0x0F;
149
150 if (adev->dma_mode >= XFER_UDMA_0) {
151 int speed = adev->dma_mode - XFER_UDMA_0;
152 r_bp |= udma_timing[speed][0];
153 r_cp |= udma_timing[speed][1];
154
155 } else {
156 int speed = adev->dma_mode - XFER_MW_DMA_0;
157 r_bp |= mdma_timing[speed][0];
158 r_cp |= mdma_timing[speed][1];
159 }
160 pci_write_config_byte(pdev, port + 1, r_bp);
161 pci_write_config_byte(pdev, port + 2, r_cp);
162
163}
164
165/**
166 * pdc2026x_bmdma_start - DMA engine begin
167 * @qc: ATA command
168 *
169 * In UDMA3 or higher we have to clock switch for the duration of the
170 * DMA transfer sequence.
171 *
172 * Note: The host lock held by the libata layer protects
173 * us from two channels both trying to set DMA bits at once
174 */
175
176static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
177{
178 struct ata_port *ap = qc->ap;
179 struct ata_device *adev = qc->dev;
180 struct ata_taskfile *tf = &qc->tf;
181 int sel66 = ap->port_no ? 0x08: 0x02;
182
183 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
184 void __iomem *clock = master + 0x11;
185 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
186
187 u32 len;
188
189 /* Check we keep host level locking here */
190 if (adev->dma_mode > XFER_UDMA_2)
191 iowrite8(ioread8(clock) | sel66, clock);
192 else
193 iowrite8(ioread8(clock) & ~sel66, clock);
194
195 /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
196 and move to qc_issue ? */
197 pdc202xx_set_dmamode(ap, qc->dev);
198
199 /* Cases the state machine will not complete correctly without help */
200 if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) {
201 len = qc->nbytes / 2;
202
203 if (tf->flags & ATA_TFLAG_WRITE)
204 len |= 0x06000000;
205 else
206 len |= 0x05000000;
207
208 iowrite32(len, atapi_reg);
209 }
210
211 /* Activate DMA */
212 ata_bmdma_start(qc);
213}
214
215/**
216 * pdc2026x_bmdma_end - DMA engine stop
217 * @qc: ATA command
218 *
219 * After a DMA completes we need to put the clock back to 33MHz for
220 * PIO timings.
221 *
222 * Note: The host lock held by the libata layer protects
223 * us from two channels both trying to set DMA bits at once
224 */
225
226static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
227{
228 struct ata_port *ap = qc->ap;
229 struct ata_device *adev = qc->dev;
230 struct ata_taskfile *tf = &qc->tf;
231
232 int sel66 = ap->port_no ? 0x08: 0x02;
233 /* The clock bits are in the same register for both channels */
234 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
235 void __iomem *clock = master + 0x11;
236 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
237
238 /* Cases the state machine will not complete correctly */
239 if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
240 iowrite32(0, atapi_reg);
241 iowrite8(ioread8(clock) & ~sel66, clock);
242 }
243 /* Flip back to 33Mhz for PIO */
244 if (adev->dma_mode > XFER_UDMA_2)
245 iowrite8(ioread8(clock) & ~sel66, clock);
246 ata_bmdma_stop(qc);
247 pdc202xx_set_piomode(ap, adev);
248}
249
250/**
251 * pdc2026x_dev_config - device setup hook
252 * @adev: newly found device
253 *
254 * Perform chip specific early setup. We need to lock the transfer
255 * sizes to 8bit to avoid making the state engine on the 2026x cards
256 * barf.
257 */
258
259static void pdc2026x_dev_config(struct ata_device *adev)
260{
261 adev->max_sectors = 256;
262}
263
264static int pdc2026x_port_start(struct ata_port *ap)
265{
266 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
267 if (bmdma) {
268 /* Enable burst mode */
269 u8 burst = ioread8(bmdma + 0x1f);
270 iowrite8(burst | 0x01, bmdma + 0x1f);
271 }
272 return ata_bmdma_port_start(ap);
273}
274
275/**
276 * pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
277 * @qc: Metadata associated with taskfile to check
278 *
279 * Just say no - not supported on older Promise.
280 *
281 * LOCKING:
282 * None (inherited from caller).
283 *
284 * RETURNS: 0 when ATAPI DMA can be used
285 * 1 otherwise
286 */
287
288static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
289{
290 return 1;
291}
292
293static struct scsi_host_template pdc202xx_sht = {
294 ATA_BMDMA_SHT(DRV_NAME),
295};
296
297static struct ata_port_operations pdc2024x_port_ops = {
298 .inherits = &ata_bmdma_port_ops,
299
300 .cable_detect = ata_cable_40wire,
301 .set_piomode = pdc202xx_set_piomode,
302 .set_dmamode = pdc202xx_set_dmamode,
303
304 .sff_exec_command = pdc202xx_exec_command,
305 .sff_irq_check = pdc202xx_irq_check,
306};
307
308static struct ata_port_operations pdc2026x_port_ops = {
309 .inherits = &pdc2024x_port_ops,
310
311 .check_atapi_dma = pdc2026x_check_atapi_dma,
312 .bmdma_start = pdc2026x_bmdma_start,
313 .bmdma_stop = pdc2026x_bmdma_stop,
314
315 .cable_detect = pdc2026x_cable_detect,
316 .dev_config = pdc2026x_dev_config,
317
318 .port_start = pdc2026x_port_start,
319
320 .sff_exec_command = pdc202xx_exec_command,
321 .sff_irq_check = pdc202xx_irq_check,
322};
323
324static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
325{
326 static const struct ata_port_info info[3] = {
327 {
328 .flags = ATA_FLAG_SLAVE_POSS,
329 .pio_mask = ATA_PIO4,
330 .mwdma_mask = ATA_MWDMA2,
331 .udma_mask = ATA_UDMA2,
332 .port_ops = &pdc2024x_port_ops
333 },
334 {
335 .flags = ATA_FLAG_SLAVE_POSS,
336 .pio_mask = ATA_PIO4,
337 .mwdma_mask = ATA_MWDMA2,
338 .udma_mask = ATA_UDMA4,
339 .port_ops = &pdc2026x_port_ops
340 },
341 {
342 .flags = ATA_FLAG_SLAVE_POSS,
343 .pio_mask = ATA_PIO4,
344 .mwdma_mask = ATA_MWDMA2,
345 .udma_mask = ATA_UDMA5,
346 .port_ops = &pdc2026x_port_ops
347 }
348
349 };
350 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
351
352 if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
353 struct pci_dev *bridge = dev->bus->self;
354 /* Don't grab anything behind a Promise I2O RAID */
355 if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
356 if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
357 return -ENODEV;
358 if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
359 return -ENODEV;
360 }
361 }
362 return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
363}
364
365static const struct pci_device_id pdc202xx[] = {
366 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
367 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
368 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
369 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
370 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
371
372 { },
373};
374
375static struct pci_driver pdc202xx_pci_driver = {
376 .name = DRV_NAME,
377 .id_table = pdc202xx,
378 .probe = pdc202xx_init_one,
379 .remove = ata_pci_remove_one,
380#ifdef CONFIG_PM_SLEEP
381 .suspend = ata_pci_device_suspend,
382 .resume = ata_pci_device_resume,
383#endif
384};
385
386module_pci_driver(pdc202xx_pci_driver);
387
388MODULE_AUTHOR("Alan Cox");
389MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
390MODULE_LICENSE("GPL");
391MODULE_DEVICE_TABLE(pci, pdc202xx);
392MODULE_VERSION(DRV_VERSION);
393