1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * pata_sis.c - SiS ATA driver |
4 | * |
5 | * (C) 2005 Red Hat |
6 | * (C) 2007,2009 Bartlomiej Zolnierkiewicz |
7 | * |
8 | * Based upon linux/drivers/ide/pci/sis5513.c |
9 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> |
10 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer |
11 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> |
12 | * SiS Taiwan : for direct support and hardware. |
13 | * Daniela Engert : for initial ATA100 advices and numerous others. |
14 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : |
15 | * for checking code correctness, providing patches. |
16 | * Original tests and design on the SiS620 chipset. |
17 | * ATA100 tests and design on the SiS735 chipset. |
18 | * ATA16/33 support from specs |
19 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> |
20 | * |
21 | * |
22 | * TODO |
23 | * Check MWDMA on drives that don't support MWDMA speed pio cycles ? |
24 | * More Testing |
25 | */ |
26 | |
27 | #include <linux/kernel.h> |
28 | #include <linux/module.h> |
29 | #include <linux/pci.h> |
30 | #include <linux/blkdev.h> |
31 | #include <linux/delay.h> |
32 | #include <linux/device.h> |
33 | #include <scsi/scsi_host.h> |
34 | #include <linux/libata.h> |
35 | #include <linux/ata.h> |
36 | #include "sis.h" |
37 | |
38 | #define DRV_NAME "pata_sis" |
39 | #define DRV_VERSION "0.5.2" |
40 | |
41 | struct sis_chipset { |
42 | u16 device; /* PCI host ID */ |
43 | const struct ata_port_info *info; /* Info block */ |
44 | /* Probably add family, cable detect type etc here to clean |
45 | up code later */ |
46 | }; |
47 | |
48 | struct sis_laptop { |
49 | u16 device; |
50 | u16 subvendor; |
51 | u16 subdevice; |
52 | }; |
53 | |
54 | static const struct sis_laptop sis_laptop[] = { |
55 | /* devid, subvendor, subdev */ |
56 | { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ |
57 | { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ |
58 | { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ |
59 | /* end marker */ |
60 | { 0, } |
61 | }; |
62 | |
63 | static int sis_short_ata40(struct pci_dev *dev) |
64 | { |
65 | const struct sis_laptop *lap = &sis_laptop[0]; |
66 | |
67 | while (lap->device) { |
68 | if (lap->device == dev->device && |
69 | lap->subvendor == dev->subsystem_vendor && |
70 | lap->subdevice == dev->subsystem_device) |
71 | return 1; |
72 | lap++; |
73 | } |
74 | |
75 | return 0; |
76 | } |
77 | |
78 | /** |
79 | * sis_old_port_base - return PCI configuration base for dev |
80 | * @adev: device |
81 | * |
82 | * Returns the base of the PCI configuration registers for this port |
83 | * number. |
84 | */ |
85 | |
86 | static int sis_old_port_base(struct ata_device *adev) |
87 | { |
88 | return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); |
89 | } |
90 | |
91 | /** |
92 | * sis_port_base - return PCI configuration base for dev |
93 | * @adev: device |
94 | * |
95 | * Returns the base of the PCI configuration registers for this port |
96 | * number. |
97 | */ |
98 | |
99 | static int sis_port_base(struct ata_device *adev) |
100 | { |
101 | struct ata_port *ap = adev->link->ap; |
102 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
103 | int port = 0x40; |
104 | u32 reg54; |
105 | |
106 | /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */ |
107 | pci_read_config_dword(dev: pdev, where: 0x54, val: ®54); |
108 | if (reg54 & 0x40000000) |
109 | port = 0x70; |
110 | |
111 | return port + (8 * ap->port_no) + (4 * adev->devno); |
112 | } |
113 | |
114 | /** |
115 | * sis_133_cable_detect - check for 40/80 pin |
116 | * @ap: Port |
117 | * |
118 | * Perform cable detection for the later UDMA133 capable |
119 | * SiS chipset. |
120 | */ |
121 | |
122 | static int sis_133_cable_detect(struct ata_port *ap) |
123 | { |
124 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
125 | u16 tmp; |
126 | |
127 | /* The top bit of this register is the cable detect bit */ |
128 | pci_read_config_word(dev: pdev, where: 0x50 + 2 * ap->port_no, val: &tmp); |
129 | if ((tmp & 0x8000) && !sis_short_ata40(dev: pdev)) |
130 | return ATA_CBL_PATA40; |
131 | return ATA_CBL_PATA80; |
132 | } |
133 | |
134 | /** |
135 | * sis_66_cable_detect - check for 40/80 pin |
136 | * @ap: Port |
137 | * |
138 | * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 |
139 | * SiS IDE controllers. |
140 | */ |
141 | |
142 | static int sis_66_cable_detect(struct ata_port *ap) |
143 | { |
144 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
145 | u8 tmp; |
146 | |
147 | /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ |
148 | pci_read_config_byte(dev: pdev, where: 0x48, val: &tmp); |
149 | tmp >>= ap->port_no; |
150 | if ((tmp & 0x10) && !sis_short_ata40(dev: pdev)) |
151 | return ATA_CBL_PATA40; |
152 | return ATA_CBL_PATA80; |
153 | } |
154 | |
155 | |
156 | /** |
157 | * sis_pre_reset - probe begin |
158 | * @link: ATA link |
159 | * @deadline: deadline jiffies for the operation |
160 | * |
161 | * Set up cable type and use generic probe init |
162 | */ |
163 | |
164 | static int sis_pre_reset(struct ata_link *link, unsigned long deadline) |
165 | { |
166 | static const struct pci_bits sis_enable_bits[] = { |
167 | { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ |
168 | { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ |
169 | }; |
170 | |
171 | struct ata_port *ap = link->ap; |
172 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
173 | |
174 | if (!pci_test_config_bits(pdev, bits: &sis_enable_bits[ap->port_no])) |
175 | return -ENOENT; |
176 | |
177 | /* Clear the FIFO settings. We can't enable the FIFO until |
178 | we know we are poking at a disk */ |
179 | pci_write_config_byte(dev: pdev, where: 0x4B, val: 0); |
180 | return ata_sff_prereset(link, deadline); |
181 | } |
182 | |
183 | |
184 | /** |
185 | * sis_set_fifo - Set RWP fifo bits for this device |
186 | * @ap: Port |
187 | * @adev: Device |
188 | * |
189 | * SIS chipsets implement prefetch/postwrite bits for each device |
190 | * on both channels. This functionality is not ATAPI compatible and |
191 | * must be configured according to the class of device present |
192 | */ |
193 | |
194 | static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) |
195 | { |
196 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
197 | u8 fifoctrl; |
198 | u8 mask = 0x11; |
199 | |
200 | mask <<= (2 * ap->port_no); |
201 | mask <<= adev->devno; |
202 | |
203 | /* This holds various bits including the FIFO control */ |
204 | pci_read_config_byte(dev: pdev, where: 0x4B, val: &fifoctrl); |
205 | fifoctrl &= ~mask; |
206 | |
207 | /* Enable for ATA (disk) only */ |
208 | if (adev->class == ATA_DEV_ATA) |
209 | fifoctrl |= mask; |
210 | pci_write_config_byte(dev: pdev, where: 0x4B, val: fifoctrl); |
211 | } |
212 | |
213 | /** |
214 | * sis_old_set_piomode - Initialize host controller PATA PIO timings |
215 | * @ap: Port whose timings we are configuring |
216 | * @adev: Device we are configuring for. |
217 | * |
218 | * Set PIO mode for device, in host controller PCI config space. This |
219 | * function handles PIO set up for all chips that are pre ATA100 and |
220 | * also early ATA100 devices. |
221 | * |
222 | * LOCKING: |
223 | * None (inherited from caller). |
224 | */ |
225 | |
226 | static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) |
227 | { |
228 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
229 | int port = sis_old_port_base(adev); |
230 | u8 t1, t2; |
231 | int speed = adev->pio_mode - XFER_PIO_0; |
232 | |
233 | static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; |
234 | static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; |
235 | |
236 | sis_set_fifo(ap, adev); |
237 | |
238 | pci_read_config_byte(dev: pdev, where: port, val: &t1); |
239 | pci_read_config_byte(dev: pdev, where: port + 1, val: &t2); |
240 | |
241 | t1 &= ~0x0F; /* Clear active/recovery timings */ |
242 | t2 &= ~0x07; |
243 | |
244 | t1 |= active[speed]; |
245 | t2 |= recovery[speed]; |
246 | |
247 | pci_write_config_byte(dev: pdev, where: port, val: t1); |
248 | pci_write_config_byte(dev: pdev, where: port + 1, val: t2); |
249 | } |
250 | |
251 | /** |
252 | * sis_100_set_piomode - Initialize host controller PATA PIO timings |
253 | * @ap: Port whose timings we are configuring |
254 | * @adev: Device we are configuring for. |
255 | * |
256 | * Set PIO mode for device, in host controller PCI config space. This |
257 | * function handles PIO set up for ATA100 devices and early ATA133. |
258 | * |
259 | * LOCKING: |
260 | * None (inherited from caller). |
261 | */ |
262 | |
263 | static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) |
264 | { |
265 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
266 | int port = sis_old_port_base(adev); |
267 | int speed = adev->pio_mode - XFER_PIO_0; |
268 | |
269 | static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; |
270 | |
271 | sis_set_fifo(ap, adev); |
272 | |
273 | pci_write_config_byte(dev: pdev, where: port, val: actrec[speed]); |
274 | } |
275 | |
276 | /** |
277 | * sis_133_set_piomode - Initialize host controller PATA PIO timings |
278 | * @ap: Port whose timings we are configuring |
279 | * @adev: Device we are configuring for. |
280 | * |
281 | * Set PIO mode for device, in host controller PCI config space. This |
282 | * function handles PIO set up for the later ATA133 devices. |
283 | * |
284 | * LOCKING: |
285 | * None (inherited from caller). |
286 | */ |
287 | |
288 | static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) |
289 | { |
290 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
291 | int port; |
292 | u32 t1; |
293 | int speed = adev->pio_mode - XFER_PIO_0; |
294 | |
295 | static const u32 timing133[] = { |
296 | 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ |
297 | 0x0C266000, |
298 | 0x04263000, |
299 | 0x0C0A3000, |
300 | 0x05093000 |
301 | }; |
302 | static const u32 timing100[] = { |
303 | 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ |
304 | 0x091C4000, |
305 | 0x031C2000, |
306 | 0x09072000, |
307 | 0x04062000 |
308 | }; |
309 | |
310 | sis_set_fifo(ap, adev); |
311 | |
312 | port = sis_port_base(adev); |
313 | pci_read_config_dword(dev: pdev, where: port, val: &t1); |
314 | t1 &= 0xC0C00FFF; /* Mask out timing */ |
315 | |
316 | if (t1 & 0x08) /* 100 or 133 ? */ |
317 | t1 |= timing133[speed]; |
318 | else |
319 | t1 |= timing100[speed]; |
320 | pci_write_config_byte(dev: pdev, where: port, val: t1); |
321 | } |
322 | |
323 | /** |
324 | * sis_old_set_dmamode - Initialize host controller PATA DMA timings |
325 | * @ap: Port whose timings we are configuring |
326 | * @adev: Device to program |
327 | * |
328 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
329 | * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike |
330 | * the old ide/pci driver. |
331 | * |
332 | * LOCKING: |
333 | * None (inherited from caller). |
334 | */ |
335 | |
336 | static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
337 | { |
338 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
339 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
340 | int drive_pci = sis_old_port_base(adev); |
341 | u16 timing; |
342 | |
343 | static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
344 | static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; |
345 | |
346 | pci_read_config_word(dev: pdev, where: drive_pci, val: &timing); |
347 | |
348 | if (adev->dma_mode < XFER_UDMA_0) { |
349 | /* bits 3-0 hold recovery timing bits 8-10 active timing and |
350 | the higher bits are dependent on the device */ |
351 | timing &= ~0x870F; |
352 | timing |= mwdma_bits[speed]; |
353 | } else { |
354 | /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ |
355 | speed = adev->dma_mode - XFER_UDMA_0; |
356 | timing &= ~0x6000; |
357 | timing |= udma_bits[speed]; |
358 | } |
359 | pci_write_config_word(dev: pdev, where: drive_pci, val: timing); |
360 | } |
361 | |
362 | /** |
363 | * sis_66_set_dmamode - Initialize host controller PATA DMA timings |
364 | * @ap: Port whose timings we are configuring |
365 | * @adev: Device to program |
366 | * |
367 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
368 | * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike |
369 | * the old ide/pci driver. |
370 | * |
371 | * LOCKING: |
372 | * None (inherited from caller). |
373 | */ |
374 | |
375 | static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
376 | { |
377 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
378 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
379 | int drive_pci = sis_old_port_base(adev); |
380 | u16 timing; |
381 | |
382 | /* MWDMA 0-2 and UDMA 0-5 */ |
383 | static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
384 | static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; |
385 | |
386 | pci_read_config_word(dev: pdev, where: drive_pci, val: &timing); |
387 | |
388 | if (adev->dma_mode < XFER_UDMA_0) { |
389 | /* bits 3-0 hold recovery timing bits 8-10 active timing and |
390 | the higher bits are dependent on the device, bit 15 udma */ |
391 | timing &= ~0x870F; |
392 | timing |= mwdma_bits[speed]; |
393 | } else { |
394 | /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ |
395 | speed = adev->dma_mode - XFER_UDMA_0; |
396 | timing &= ~0xF000; |
397 | timing |= udma_bits[speed]; |
398 | } |
399 | pci_write_config_word(dev: pdev, where: drive_pci, val: timing); |
400 | } |
401 | |
402 | /** |
403 | * sis_100_set_dmamode - Initialize host controller PATA DMA timings |
404 | * @ap: Port whose timings we are configuring |
405 | * @adev: Device to program |
406 | * |
407 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
408 | * Handles UDMA66 and early UDMA100 devices. |
409 | * |
410 | * LOCKING: |
411 | * None (inherited from caller). |
412 | */ |
413 | |
414 | static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
415 | { |
416 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
417 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
418 | int drive_pci = sis_old_port_base(adev); |
419 | u8 timing; |
420 | |
421 | static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; |
422 | |
423 | pci_read_config_byte(dev: pdev, where: drive_pci + 1, val: &timing); |
424 | |
425 | if (adev->dma_mode < XFER_UDMA_0) { |
426 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ |
427 | } else { |
428 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
429 | speed = adev->dma_mode - XFER_UDMA_0; |
430 | timing &= ~0x8F; |
431 | timing |= udma_bits[speed]; |
432 | } |
433 | pci_write_config_byte(dev: pdev, where: drive_pci + 1, val: timing); |
434 | } |
435 | |
436 | /** |
437 | * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings |
438 | * @ap: Port whose timings we are configuring |
439 | * @adev: Device to program |
440 | * |
441 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
442 | * Handles early SiS 961 bridges. |
443 | * |
444 | * LOCKING: |
445 | * None (inherited from caller). |
446 | */ |
447 | |
448 | static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
449 | { |
450 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
451 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
452 | int drive_pci = sis_old_port_base(adev); |
453 | u8 timing; |
454 | /* Low 4 bits are timing */ |
455 | static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; |
456 | |
457 | pci_read_config_byte(dev: pdev, where: drive_pci + 1, val: &timing); |
458 | |
459 | if (adev->dma_mode < XFER_UDMA_0) { |
460 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ |
461 | } else { |
462 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
463 | speed = adev->dma_mode - XFER_UDMA_0; |
464 | timing &= ~0x8F; |
465 | timing |= udma_bits[speed]; |
466 | } |
467 | pci_write_config_byte(dev: pdev, where: drive_pci + 1, val: timing); |
468 | } |
469 | |
470 | /** |
471 | * sis_133_set_dmamode - Initialize host controller PATA DMA timings |
472 | * @ap: Port whose timings we are configuring |
473 | * @adev: Device to program |
474 | * |
475 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
476 | * |
477 | * LOCKING: |
478 | * None (inherited from caller). |
479 | */ |
480 | |
481 | static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
482 | { |
483 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
484 | int port; |
485 | u32 t1; |
486 | |
487 | port = sis_port_base(adev); |
488 | pci_read_config_dword(dev: pdev, where: port, val: &t1); |
489 | |
490 | if (adev->dma_mode < XFER_UDMA_0) { |
491 | /* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */ |
492 | static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 }; |
493 | static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 }; |
494 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
495 | |
496 | t1 &= 0xC0C00FFF; |
497 | /* disable UDMA */ |
498 | t1 &= ~0x00000004; |
499 | if (t1 & 0x08) |
500 | t1 |= timing_u133[speed]; |
501 | else |
502 | t1 |= timing_u100[speed]; |
503 | } else { |
504 | /* bits 4- cycle time 8 - cvs time */ |
505 | static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; |
506 | static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; |
507 | int speed = adev->dma_mode - XFER_UDMA_0; |
508 | |
509 | t1 &= ~0x00000FF0; |
510 | /* enable UDMA */ |
511 | t1 |= 0x00000004; |
512 | if (t1 & 0x08) |
513 | t1 |= timing_u133[speed]; |
514 | else |
515 | t1 |= timing_u100[speed]; |
516 | } |
517 | pci_write_config_dword(dev: pdev, where: port, val: t1); |
518 | } |
519 | |
520 | /** |
521 | * sis_133_mode_filter - mode selection filter |
522 | * @adev: ATA device |
523 | * @mask: received mask to manipulate and pass back |
524 | * |
525 | * Block UDMA6 on devices that do not support it. |
526 | */ |
527 | |
528 | static unsigned int sis_133_mode_filter(struct ata_device *adev, unsigned int mask) |
529 | { |
530 | struct ata_port *ap = adev->link->ap; |
531 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
532 | int port = sis_port_base(adev); |
533 | u32 t1; |
534 | |
535 | pci_read_config_dword(dev: pdev, where: port, val: &t1); |
536 | /* if ATA133 is disabled, mask it out */ |
537 | if (!(t1 & 0x08)) |
538 | mask &= ~(0xC0 << ATA_SHIFT_UDMA); |
539 | return mask; |
540 | } |
541 | |
542 | static const struct scsi_host_template sis_sht = { |
543 | ATA_BMDMA_SHT(DRV_NAME), |
544 | }; |
545 | |
546 | static struct ata_port_operations sis_133_for_sata_ops = { |
547 | .inherits = &ata_bmdma_port_ops, |
548 | .set_piomode = sis_133_set_piomode, |
549 | .set_dmamode = sis_133_set_dmamode, |
550 | .cable_detect = sis_133_cable_detect, |
551 | }; |
552 | |
553 | static struct ata_port_operations sis_base_ops = { |
554 | .inherits = &ata_bmdma_port_ops, |
555 | .prereset = sis_pre_reset, |
556 | }; |
557 | |
558 | static struct ata_port_operations sis_133_ops = { |
559 | .inherits = &sis_base_ops, |
560 | .set_piomode = sis_133_set_piomode, |
561 | .set_dmamode = sis_133_set_dmamode, |
562 | .cable_detect = sis_133_cable_detect, |
563 | .mode_filter = sis_133_mode_filter, |
564 | }; |
565 | |
566 | static struct ata_port_operations sis_133_early_ops = { |
567 | .inherits = &sis_base_ops, |
568 | .set_piomode = sis_100_set_piomode, |
569 | .set_dmamode = sis_133_early_set_dmamode, |
570 | .cable_detect = sis_66_cable_detect, |
571 | }; |
572 | |
573 | static struct ata_port_operations sis_100_ops = { |
574 | .inherits = &sis_base_ops, |
575 | .set_piomode = sis_100_set_piomode, |
576 | .set_dmamode = sis_100_set_dmamode, |
577 | .cable_detect = sis_66_cable_detect, |
578 | }; |
579 | |
580 | static struct ata_port_operations sis_66_ops = { |
581 | .inherits = &sis_base_ops, |
582 | .set_piomode = sis_old_set_piomode, |
583 | .set_dmamode = sis_66_set_dmamode, |
584 | .cable_detect = sis_66_cable_detect, |
585 | }; |
586 | |
587 | static struct ata_port_operations sis_old_ops = { |
588 | .inherits = &sis_base_ops, |
589 | .set_piomode = sis_old_set_piomode, |
590 | .set_dmamode = sis_old_set_dmamode, |
591 | .cable_detect = ata_cable_40wire, |
592 | }; |
593 | |
594 | static const struct ata_port_info sis_info = { |
595 | .flags = ATA_FLAG_SLAVE_POSS, |
596 | .pio_mask = ATA_PIO4, |
597 | .mwdma_mask = ATA_MWDMA2, |
598 | /* No UDMA */ |
599 | .port_ops = &sis_old_ops, |
600 | }; |
601 | static const struct ata_port_info sis_info33 = { |
602 | .flags = ATA_FLAG_SLAVE_POSS, |
603 | .pio_mask = ATA_PIO4, |
604 | .mwdma_mask = ATA_MWDMA2, |
605 | .udma_mask = ATA_UDMA2, |
606 | .port_ops = &sis_old_ops, |
607 | }; |
608 | static const struct ata_port_info sis_info66 = { |
609 | .flags = ATA_FLAG_SLAVE_POSS, |
610 | .pio_mask = ATA_PIO4, |
611 | /* No MWDMA */ |
612 | .udma_mask = ATA_UDMA4, |
613 | .port_ops = &sis_66_ops, |
614 | }; |
615 | static const struct ata_port_info sis_info100 = { |
616 | .flags = ATA_FLAG_SLAVE_POSS, |
617 | .pio_mask = ATA_PIO4, |
618 | /* No MWDMA */ |
619 | .udma_mask = ATA_UDMA5, |
620 | .port_ops = &sis_100_ops, |
621 | }; |
622 | static const struct ata_port_info sis_info100_early = { |
623 | .flags = ATA_FLAG_SLAVE_POSS, |
624 | .pio_mask = ATA_PIO4, |
625 | /* No MWDMA */ |
626 | .udma_mask = ATA_UDMA5, |
627 | .port_ops = &sis_66_ops, |
628 | }; |
629 | static const struct ata_port_info sis_info133 = { |
630 | .flags = ATA_FLAG_SLAVE_POSS, |
631 | .pio_mask = ATA_PIO4, |
632 | .mwdma_mask = ATA_MWDMA2, |
633 | .udma_mask = ATA_UDMA6, |
634 | .port_ops = &sis_133_ops, |
635 | }; |
636 | const struct ata_port_info sis_info133_for_sata = { |
637 | .flags = ATA_FLAG_SLAVE_POSS, |
638 | .pio_mask = ATA_PIO4, |
639 | /* No MWDMA */ |
640 | .udma_mask = ATA_UDMA6, |
641 | .port_ops = &sis_133_for_sata_ops, |
642 | }; |
643 | static const struct ata_port_info sis_info133_early = { |
644 | .flags = ATA_FLAG_SLAVE_POSS, |
645 | .pio_mask = ATA_PIO4, |
646 | /* No MWDMA */ |
647 | .udma_mask = ATA_UDMA6, |
648 | .port_ops = &sis_133_early_ops, |
649 | }; |
650 | |
651 | /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ |
652 | EXPORT_SYMBOL_GPL(sis_info133_for_sata); |
653 | |
654 | static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) |
655 | { |
656 | u16 regw; |
657 | u8 reg; |
658 | |
659 | if (sis->info == &sis_info133) { |
660 | pci_read_config_word(dev: pdev, where: 0x50, val: ®w); |
661 | if (regw & 0x08) |
662 | pci_write_config_word(dev: pdev, where: 0x50, val: regw & ~0x08); |
663 | pci_read_config_word(dev: pdev, where: 0x52, val: ®w); |
664 | if (regw & 0x08) |
665 | pci_write_config_word(dev: pdev, where: 0x52, val: regw & ~0x08); |
666 | return; |
667 | } |
668 | |
669 | if (sis->info == &sis_info133_early || sis->info == &sis_info100) { |
670 | /* Fix up latency */ |
671 | pci_write_config_byte(dev: pdev, PCI_LATENCY_TIMER, val: 0x80); |
672 | /* Set compatibility bit */ |
673 | pci_read_config_byte(dev: pdev, where: 0x49, val: ®); |
674 | if (!(reg & 0x01)) |
675 | pci_write_config_byte(dev: pdev, where: 0x49, val: reg | 0x01); |
676 | return; |
677 | } |
678 | |
679 | if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { |
680 | /* Fix up latency */ |
681 | pci_write_config_byte(dev: pdev, PCI_LATENCY_TIMER, val: 0x80); |
682 | /* Set compatibility bit */ |
683 | pci_read_config_byte(dev: pdev, where: 0x52, val: ®); |
684 | if (!(reg & 0x04)) |
685 | pci_write_config_byte(dev: pdev, where: 0x52, val: reg | 0x04); |
686 | return; |
687 | } |
688 | |
689 | if (sis->info == &sis_info33) { |
690 | pci_read_config_byte(dev: pdev, PCI_CLASS_PROG, val: ®); |
691 | if (( reg & 0x0F ) != 0x00) |
692 | pci_write_config_byte(dev: pdev, PCI_CLASS_PROG, val: reg & 0xF0); |
693 | /* Fall through to ATA16 fixup below */ |
694 | } |
695 | |
696 | if (sis->info == &sis_info || sis->info == &sis_info33) { |
697 | /* force per drive recovery and active timings |
698 | needed on ATA_33 and below chips */ |
699 | pci_read_config_byte(dev: pdev, where: 0x52, val: ®); |
700 | if (!(reg & 0x08)) |
701 | pci_write_config_byte(dev: pdev, where: 0x52, val: reg|0x08); |
702 | return; |
703 | } |
704 | |
705 | BUG(); |
706 | } |
707 | |
708 | /** |
709 | * sis_init_one - Register SiS ATA PCI device with kernel services |
710 | * @pdev: PCI device to register |
711 | * @ent: Entry in sis_pci_tbl matching with @pdev |
712 | * |
713 | * Called from kernel PCI layer. We probe for combined mode (sigh), |
714 | * and then hand over control to libata, for it to do the rest. |
715 | * |
716 | * LOCKING: |
717 | * Inherited from PCI layer (may sleep). |
718 | * |
719 | * RETURNS: |
720 | * Zero on success, or -ERRNO value. |
721 | */ |
722 | |
723 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
724 | { |
725 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
726 | struct pci_dev *host = NULL; |
727 | struct sis_chipset *chipset = NULL; |
728 | struct sis_chipset *sets; |
729 | int rc; |
730 | |
731 | static struct sis_chipset sis_chipsets[] = { |
732 | |
733 | { 0x0968, &sis_info133 }, |
734 | { 0x0966, &sis_info133 }, |
735 | { 0x0965, &sis_info133 }, |
736 | { 0x0745, &sis_info100 }, |
737 | { 0x0735, &sis_info100 }, |
738 | { 0x0733, &sis_info100 }, |
739 | { 0x0635, &sis_info100 }, |
740 | { 0x0633, &sis_info100 }, |
741 | |
742 | { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ |
743 | { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ |
744 | |
745 | { 0x0640, &sis_info66 }, |
746 | { 0x0630, &sis_info66 }, |
747 | { 0x0620, &sis_info66 }, |
748 | { 0x0540, &sis_info66 }, |
749 | { 0x0530, &sis_info66 }, |
750 | |
751 | { 0x5600, &sis_info33 }, |
752 | { 0x5598, &sis_info33 }, |
753 | { 0x5597, &sis_info33 }, |
754 | { 0x5591, &sis_info33 }, |
755 | { 0x5582, &sis_info33 }, |
756 | { 0x5581, &sis_info33 }, |
757 | |
758 | { 0x5596, &sis_info }, |
759 | { 0x5571, &sis_info }, |
760 | { 0x5517, &sis_info }, |
761 | { 0x5511, &sis_info }, |
762 | |
763 | {0} |
764 | }; |
765 | static struct sis_chipset sis133_early = { |
766 | 0x0, &sis_info133_early |
767 | }; |
768 | static struct sis_chipset sis133 = { |
769 | 0x0, &sis_info133 |
770 | }; |
771 | static struct sis_chipset sis100_early = { |
772 | 0x0, &sis_info100_early |
773 | }; |
774 | static struct sis_chipset sis100 = { |
775 | 0x0, &sis_info100 |
776 | }; |
777 | |
778 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
779 | |
780 | rc = pcim_enable_device(pdev); |
781 | if (rc) |
782 | return rc; |
783 | |
784 | /* We have to find the bridge first */ |
785 | for (sets = &sis_chipsets[0]; sets->device; sets++) { |
786 | host = pci_get_device(PCI_VENDOR_ID_SI, device: sets->device, NULL); |
787 | if (host != NULL) { |
788 | chipset = sets; /* Match found */ |
789 | if (sets->device == 0x630) { /* SIS630 */ |
790 | if (host->revision >= 0x30) /* 630 ET */ |
791 | chipset = &sis100_early; |
792 | } |
793 | break; |
794 | } |
795 | } |
796 | |
797 | /* Look for concealed bridges */ |
798 | if (chipset == NULL) { |
799 | /* Second check */ |
800 | u32 idemisc; |
801 | u16 trueid; |
802 | |
803 | /* Disable ID masking and register remapping then |
804 | see what the real ID is */ |
805 | |
806 | pci_read_config_dword(dev: pdev, where: 0x54, val: &idemisc); |
807 | pci_write_config_dword(dev: pdev, where: 0x54, val: idemisc & 0x7fffffff); |
808 | pci_read_config_word(dev: pdev, PCI_DEVICE_ID, val: &trueid); |
809 | pci_write_config_dword(dev: pdev, where: 0x54, val: idemisc); |
810 | |
811 | switch(trueid) { |
812 | case 0x5518: /* SIS 962/963 */ |
813 | dev_info(&pdev->dev, |
814 | "SiS 962/963 MuTIOL IDE UDMA133 controller\n" ); |
815 | chipset = &sis133; |
816 | if ((idemisc & 0x40000000) == 0) { |
817 | pci_write_config_dword(dev: pdev, where: 0x54, val: idemisc | 0x40000000); |
818 | dev_info(&pdev->dev, |
819 | "Switching to 5513 register mapping\n" ); |
820 | } |
821 | break; |
822 | case 0x0180: /* SIS 965/965L */ |
823 | chipset = &sis133; |
824 | break; |
825 | case 0x1180: /* SIS 966/966L */ |
826 | chipset = &sis133; |
827 | break; |
828 | } |
829 | } |
830 | |
831 | /* Further check */ |
832 | if (chipset == NULL) { |
833 | struct pci_dev *lpc_bridge; |
834 | u16 trueid; |
835 | u8 prefctl; |
836 | u8 idecfg; |
837 | |
838 | /* Try the second unmasking technique */ |
839 | pci_read_config_byte(dev: pdev, where: 0x4a, val: &idecfg); |
840 | pci_write_config_byte(dev: pdev, where: 0x4a, val: idecfg | 0x10); |
841 | pci_read_config_word(dev: pdev, PCI_DEVICE_ID, val: &trueid); |
842 | pci_write_config_byte(dev: pdev, where: 0x4a, val: idecfg); |
843 | |
844 | switch(trueid) { |
845 | case 0x5517: |
846 | lpc_bridge = pci_get_slot(bus: pdev->bus, devfn: 0x10); /* Bus 0 Dev 2 Fn 0 */ |
847 | if (lpc_bridge == NULL) |
848 | break; |
849 | pci_read_config_byte(dev: pdev, where: 0x49, val: &prefctl); |
850 | pci_dev_put(dev: lpc_bridge); |
851 | |
852 | if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { |
853 | chipset = &sis133_early; |
854 | break; |
855 | } |
856 | chipset = &sis100; |
857 | break; |
858 | } |
859 | } |
860 | pci_dev_put(dev: host); |
861 | |
862 | /* No chipset info, no support */ |
863 | if (chipset == NULL) |
864 | return -ENODEV; |
865 | |
866 | ppi[0] = chipset->info; |
867 | |
868 | sis_fixup(pdev, sis: chipset); |
869 | |
870 | return ata_pci_bmdma_init_one(pdev, ppi, sht: &sis_sht, host_priv: chipset, hflags: 0); |
871 | } |
872 | |
873 | #ifdef CONFIG_PM_SLEEP |
874 | static int sis_reinit_one(struct pci_dev *pdev) |
875 | { |
876 | struct ata_host *host = pci_get_drvdata(pdev); |
877 | int rc; |
878 | |
879 | rc = ata_pci_device_do_resume(pdev); |
880 | if (rc) |
881 | return rc; |
882 | |
883 | sis_fixup(pdev, sis: host->private_data); |
884 | |
885 | ata_host_resume(host); |
886 | return 0; |
887 | } |
888 | #endif |
889 | |
890 | static const struct pci_device_id sis_pci_tbl[] = { |
891 | { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ |
892 | { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ |
893 | { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ |
894 | |
895 | { } |
896 | }; |
897 | |
898 | static struct pci_driver sis_pci_driver = { |
899 | .name = DRV_NAME, |
900 | .id_table = sis_pci_tbl, |
901 | .probe = sis_init_one, |
902 | .remove = ata_pci_remove_one, |
903 | #ifdef CONFIG_PM_SLEEP |
904 | .suspend = ata_pci_device_suspend, |
905 | .resume = sis_reinit_one, |
906 | #endif |
907 | }; |
908 | |
909 | module_pci_driver(sis_pci_driver); |
910 | |
911 | MODULE_AUTHOR("Alan Cox" ); |
912 | MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA" ); |
913 | MODULE_LICENSE("GPL" ); |
914 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); |
915 | MODULE_VERSION(DRV_VERSION); |
916 | |