1/*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat
5 * (C) 2007,2009 Bartlomiej Zolnierkiewicz
6 *
7 * Based upon linux/drivers/ide/pci/sis5513.c
8 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
9 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
10 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
11 * SiS Taiwan : for direct support and hardware.
12 * Daniela Engert : for initial ATA100 advices and numerous others.
13 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
14 * for checking code correctness, providing patches.
15 * Original tests and design on the SiS620 chipset.
16 * ATA100 tests and design on the SiS735 chipset.
17 * ATA16/33 support from specs
18 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
19 *
20 *
21 * TODO
22 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
23 * More Testing
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34#include <linux/ata.h>
35#include "sis.h"
36
37#define DRV_NAME "pata_sis"
38#define DRV_VERSION "0.5.2"
39
40struct sis_chipset {
41 u16 device; /* PCI host ID */
42 const struct ata_port_info *info; /* Info block */
43 /* Probably add family, cable detect type etc here to clean
44 up code later */
45};
46
47struct sis_laptop {
48 u16 device;
49 u16 subvendor;
50 u16 subdevice;
51};
52
53static const struct sis_laptop sis_laptop[] = {
54 /* devid, subvendor, subdev */
55 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
56 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
57 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
58 /* end marker */
59 { 0, }
60};
61
62static int sis_short_ata40(struct pci_dev *dev)
63{
64 const struct sis_laptop *lap = &sis_laptop[0];
65
66 while (lap->device) {
67 if (lap->device == dev->device &&
68 lap->subvendor == dev->subsystem_vendor &&
69 lap->subdevice == dev->subsystem_device)
70 return 1;
71 lap++;
72 }
73
74 return 0;
75}
76
77/**
78 * sis_old_port_base - return PCI configuration base for dev
79 * @adev: device
80 *
81 * Returns the base of the PCI configuration registers for this port
82 * number.
83 */
84
85static int sis_old_port_base(struct ata_device *adev)
86{
87 return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno);
88}
89
90/**
91 * sis_port_base - return PCI configuration base for dev
92 * @adev: device
93 *
94 * Returns the base of the PCI configuration registers for this port
95 * number.
96 */
97
98static int sis_port_base(struct ata_device *adev)
99{
100 struct ata_port *ap = adev->link->ap;
101 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
102 int port = 0x40;
103 u32 reg54;
104
105 /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */
106 pci_read_config_dword(pdev, 0x54, &reg54);
107 if (reg54 & 0x40000000)
108 port = 0x70;
109
110 return port + (8 * ap->port_no) + (4 * adev->devno);
111}
112
113/**
114 * sis_133_cable_detect - check for 40/80 pin
115 * @ap: Port
116 * @deadline: deadline jiffies for the operation
117 *
118 * Perform cable detection for the later UDMA133 capable
119 * SiS chipset.
120 */
121
122static int sis_133_cable_detect(struct ata_port *ap)
123{
124 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
125 u16 tmp;
126
127 /* The top bit of this register is the cable detect bit */
128 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
129 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
130 return ATA_CBL_PATA40;
131 return ATA_CBL_PATA80;
132}
133
134/**
135 * sis_66_cable_detect - check for 40/80 pin
136 * @ap: Port
137 *
138 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
139 * SiS IDE controllers.
140 */
141
142static int sis_66_cable_detect(struct ata_port *ap)
143{
144 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
145 u8 tmp;
146
147 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
148 pci_read_config_byte(pdev, 0x48, &tmp);
149 tmp >>= ap->port_no;
150 if ((tmp & 0x10) && !sis_short_ata40(pdev))
151 return ATA_CBL_PATA40;
152 return ATA_CBL_PATA80;
153}
154
155
156/**
157 * sis_pre_reset - probe begin
158 * @link: ATA link
159 * @deadline: deadline jiffies for the operation
160 *
161 * Set up cable type and use generic probe init
162 */
163
164static int sis_pre_reset(struct ata_link *link, unsigned long deadline)
165{
166 static const struct pci_bits sis_enable_bits[] = {
167 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
168 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
169 };
170
171 struct ata_port *ap = link->ap;
172 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
173
174 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
175 return -ENOENT;
176
177 /* Clear the FIFO settings. We can't enable the FIFO until
178 we know we are poking at a disk */
179 pci_write_config_byte(pdev, 0x4B, 0);
180 return ata_sff_prereset(link, deadline);
181}
182
183
184/**
185 * sis_set_fifo - Set RWP fifo bits for this device
186 * @ap: Port
187 * @adev: Device
188 *
189 * SIS chipsets implement prefetch/postwrite bits for each device
190 * on both channels. This functionality is not ATAPI compatible and
191 * must be configured according to the class of device present
192 */
193
194static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
195{
196 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
197 u8 fifoctrl;
198 u8 mask = 0x11;
199
200 mask <<= (2 * ap->port_no);
201 mask <<= adev->devno;
202
203 /* This holds various bits including the FIFO control */
204 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
205 fifoctrl &= ~mask;
206
207 /* Enable for ATA (disk) only */
208 if (adev->class == ATA_DEV_ATA)
209 fifoctrl |= mask;
210 pci_write_config_byte(pdev, 0x4B, fifoctrl);
211}
212
213/**
214 * sis_old_set_piomode - Initialize host controller PATA PIO timings
215 * @ap: Port whose timings we are configuring
216 * @adev: Device we are configuring for.
217 *
218 * Set PIO mode for device, in host controller PCI config space. This
219 * function handles PIO set up for all chips that are pre ATA100 and
220 * also early ATA100 devices.
221 *
222 * LOCKING:
223 * None (inherited from caller).
224 */
225
226static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
227{
228 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
229 int port = sis_old_port_base(adev);
230 u8 t1, t2;
231 int speed = adev->pio_mode - XFER_PIO_0;
232
233 static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
234 static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
235
236 sis_set_fifo(ap, adev);
237
238 pci_read_config_byte(pdev, port, &t1);
239 pci_read_config_byte(pdev, port + 1, &t2);
240
241 t1 &= ~0x0F; /* Clear active/recovery timings */
242 t2 &= ~0x07;
243
244 t1 |= active[speed];
245 t2 |= recovery[speed];
246
247 pci_write_config_byte(pdev, port, t1);
248 pci_write_config_byte(pdev, port + 1, t2);
249}
250
251/**
252 * sis_100_set_piomode - Initialize host controller PATA PIO timings
253 * @ap: Port whose timings we are configuring
254 * @adev: Device we are configuring for.
255 *
256 * Set PIO mode for device, in host controller PCI config space. This
257 * function handles PIO set up for ATA100 devices and early ATA133.
258 *
259 * LOCKING:
260 * None (inherited from caller).
261 */
262
263static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
264{
265 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
266 int port = sis_old_port_base(adev);
267 int speed = adev->pio_mode - XFER_PIO_0;
268
269 static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
270
271 sis_set_fifo(ap, adev);
272
273 pci_write_config_byte(pdev, port, actrec[speed]);
274}
275
276/**
277 * sis_133_set_piomode - Initialize host controller PATA PIO timings
278 * @ap: Port whose timings we are configuring
279 * @adev: Device we are configuring for.
280 *
281 * Set PIO mode for device, in host controller PCI config space. This
282 * function handles PIO set up for the later ATA133 devices.
283 *
284 * LOCKING:
285 * None (inherited from caller).
286 */
287
288static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
289{
290 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
291 int port;
292 u32 t1;
293 int speed = adev->pio_mode - XFER_PIO_0;
294
295 static const u32 timing133[] = {
296 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
297 0x0C266000,
298 0x04263000,
299 0x0C0A3000,
300 0x05093000
301 };
302 static const u32 timing100[] = {
303 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
304 0x091C4000,
305 0x031C2000,
306 0x09072000,
307 0x04062000
308 };
309
310 sis_set_fifo(ap, adev);
311
312 port = sis_port_base(adev);
313 pci_read_config_dword(pdev, port, &t1);
314 t1 &= 0xC0C00FFF; /* Mask out timing */
315
316 if (t1 & 0x08) /* 100 or 133 ? */
317 t1 |= timing133[speed];
318 else
319 t1 |= timing100[speed];
320 pci_write_config_byte(pdev, port, t1);
321}
322
323/**
324 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
325 * @ap: Port whose timings we are configuring
326 * @adev: Device to program
327 *
328 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
329 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
330 * the old ide/pci driver.
331 *
332 * LOCKING:
333 * None (inherited from caller).
334 */
335
336static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
337{
338 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
339 int speed = adev->dma_mode - XFER_MW_DMA_0;
340 int drive_pci = sis_old_port_base(adev);
341 u16 timing;
342
343 static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
344 static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
345
346 pci_read_config_word(pdev, drive_pci, &timing);
347
348 if (adev->dma_mode < XFER_UDMA_0) {
349 /* bits 3-0 hold recovery timing bits 8-10 active timing and
350 the higher bits are dependent on the device */
351 timing &= ~0x870F;
352 timing |= mwdma_bits[speed];
353 } else {
354 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
355 speed = adev->dma_mode - XFER_UDMA_0;
356 timing &= ~0x6000;
357 timing |= udma_bits[speed];
358 }
359 pci_write_config_word(pdev, drive_pci, timing);
360}
361
362/**
363 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
364 * @ap: Port whose timings we are configuring
365 * @adev: Device to program
366 *
367 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
368 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
369 * the old ide/pci driver.
370 *
371 * LOCKING:
372 * None (inherited from caller).
373 */
374
375static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
376{
377 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
378 int speed = adev->dma_mode - XFER_MW_DMA_0;
379 int drive_pci = sis_old_port_base(adev);
380 u16 timing;
381
382 /* MWDMA 0-2 and UDMA 0-5 */
383 static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
384 static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 };
385
386 pci_read_config_word(pdev, drive_pci, &timing);
387
388 if (adev->dma_mode < XFER_UDMA_0) {
389 /* bits 3-0 hold recovery timing bits 8-10 active timing and
390 the higher bits are dependent on the device, bit 15 udma */
391 timing &= ~0x870F;
392 timing |= mwdma_bits[speed];
393 } else {
394 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
395 speed = adev->dma_mode - XFER_UDMA_0;
396 timing &= ~0xF000;
397 timing |= udma_bits[speed];
398 }
399 pci_write_config_word(pdev, drive_pci, timing);
400}
401
402/**
403 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
404 * @ap: Port whose timings we are configuring
405 * @adev: Device to program
406 *
407 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
408 * Handles UDMA66 and early UDMA100 devices.
409 *
410 * LOCKING:
411 * None (inherited from caller).
412 */
413
414static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
415{
416 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
417 int speed = adev->dma_mode - XFER_MW_DMA_0;
418 int drive_pci = sis_old_port_base(adev);
419 u8 timing;
420
421 static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
422
423 pci_read_config_byte(pdev, drive_pci + 1, &timing);
424
425 if (adev->dma_mode < XFER_UDMA_0) {
426 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
427 } else {
428 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
429 speed = adev->dma_mode - XFER_UDMA_0;
430 timing &= ~0x8F;
431 timing |= udma_bits[speed];
432 }
433 pci_write_config_byte(pdev, drive_pci + 1, timing);
434}
435
436/**
437 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
438 * @ap: Port whose timings we are configuring
439 * @adev: Device to program
440 *
441 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
442 * Handles early SiS 961 bridges.
443 *
444 * LOCKING:
445 * None (inherited from caller).
446 */
447
448static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
449{
450 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
451 int speed = adev->dma_mode - XFER_MW_DMA_0;
452 int drive_pci = sis_old_port_base(adev);
453 u8 timing;
454 /* Low 4 bits are timing */
455 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
456
457 pci_read_config_byte(pdev, drive_pci + 1, &timing);
458
459 if (adev->dma_mode < XFER_UDMA_0) {
460 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
461 } else {
462 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
463 speed = adev->dma_mode - XFER_UDMA_0;
464 timing &= ~0x8F;
465 timing |= udma_bits[speed];
466 }
467 pci_write_config_byte(pdev, drive_pci + 1, timing);
468}
469
470/**
471 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
472 * @ap: Port whose timings we are configuring
473 * @adev: Device to program
474 *
475 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
476 *
477 * LOCKING:
478 * None (inherited from caller).
479 */
480
481static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
482{
483 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
484 int port;
485 u32 t1;
486
487 port = sis_port_base(adev);
488 pci_read_config_dword(pdev, port, &t1);
489
490 if (adev->dma_mode < XFER_UDMA_0) {
491 /* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */
492 static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 };
493 static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 };
494 int speed = adev->dma_mode - XFER_MW_DMA_0;
495
496 t1 &= 0xC0C00FFF;
497 /* disable UDMA */
498 t1 &= ~0x00000004;
499 if (t1 & 0x08)
500 t1 |= timing_u133[speed];
501 else
502 t1 |= timing_u100[speed];
503 } else {
504 /* bits 4- cycle time 8 - cvs time */
505 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
506 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
507 int speed = adev->dma_mode - XFER_UDMA_0;
508
509 t1 &= ~0x00000FF0;
510 /* enable UDMA */
511 t1 |= 0x00000004;
512 if (t1 & 0x08)
513 t1 |= timing_u133[speed];
514 else
515 t1 |= timing_u100[speed];
516 }
517 pci_write_config_dword(pdev, port, t1);
518}
519
520/**
521 * sis_133_mode_filter - mode selection filter
522 * @adev: ATA device
523 *
524 * Block UDMA6 on devices that do not support it.
525 */
526
527static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long mask)
528{
529 struct ata_port *ap = adev->link->ap;
530 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
531 int port = sis_port_base(adev);
532 u32 t1;
533
534 pci_read_config_dword(pdev, port, &t1);
535 /* if ATA133 is disabled, mask it out */
536 if (!(t1 & 0x08))
537 mask &= ~(0xC0 << ATA_SHIFT_UDMA);
538 return mask;
539}
540
541static struct scsi_host_template sis_sht = {
542 ATA_BMDMA_SHT(DRV_NAME),
543};
544
545static struct ata_port_operations sis_133_for_sata_ops = {
546 .inherits = &ata_bmdma_port_ops,
547 .set_piomode = sis_133_set_piomode,
548 .set_dmamode = sis_133_set_dmamode,
549 .cable_detect = sis_133_cable_detect,
550};
551
552static struct ata_port_operations sis_base_ops = {
553 .inherits = &ata_bmdma_port_ops,
554 .prereset = sis_pre_reset,
555};
556
557static struct ata_port_operations sis_133_ops = {
558 .inherits = &sis_base_ops,
559 .set_piomode = sis_133_set_piomode,
560 .set_dmamode = sis_133_set_dmamode,
561 .cable_detect = sis_133_cable_detect,
562 .mode_filter = sis_133_mode_filter,
563};
564
565static struct ata_port_operations sis_133_early_ops = {
566 .inherits = &sis_base_ops,
567 .set_piomode = sis_100_set_piomode,
568 .set_dmamode = sis_133_early_set_dmamode,
569 .cable_detect = sis_66_cable_detect,
570};
571
572static struct ata_port_operations sis_100_ops = {
573 .inherits = &sis_base_ops,
574 .set_piomode = sis_100_set_piomode,
575 .set_dmamode = sis_100_set_dmamode,
576 .cable_detect = sis_66_cable_detect,
577};
578
579static struct ata_port_operations sis_66_ops = {
580 .inherits = &sis_base_ops,
581 .set_piomode = sis_old_set_piomode,
582 .set_dmamode = sis_66_set_dmamode,
583 .cable_detect = sis_66_cable_detect,
584};
585
586static struct ata_port_operations sis_old_ops = {
587 .inherits = &sis_base_ops,
588 .set_piomode = sis_old_set_piomode,
589 .set_dmamode = sis_old_set_dmamode,
590 .cable_detect = ata_cable_40wire,
591};
592
593static const struct ata_port_info sis_info = {
594 .flags = ATA_FLAG_SLAVE_POSS,
595 .pio_mask = ATA_PIO4,
596 .mwdma_mask = ATA_MWDMA2,
597 /* No UDMA */
598 .port_ops = &sis_old_ops,
599};
600static const struct ata_port_info sis_info33 = {
601 .flags = ATA_FLAG_SLAVE_POSS,
602 .pio_mask = ATA_PIO4,
603 .mwdma_mask = ATA_MWDMA2,
604 .udma_mask = ATA_UDMA2,
605 .port_ops = &sis_old_ops,
606};
607static const struct ata_port_info sis_info66 = {
608 .flags = ATA_FLAG_SLAVE_POSS,
609 .pio_mask = ATA_PIO4,
610 /* No MWDMA */
611 .udma_mask = ATA_UDMA4,
612 .port_ops = &sis_66_ops,
613};
614static const struct ata_port_info sis_info100 = {
615 .flags = ATA_FLAG_SLAVE_POSS,
616 .pio_mask = ATA_PIO4,
617 /* No MWDMA */
618 .udma_mask = ATA_UDMA5,
619 .port_ops = &sis_100_ops,
620};
621static const struct ata_port_info sis_info100_early = {
622 .flags = ATA_FLAG_SLAVE_POSS,
623 .pio_mask = ATA_PIO4,
624 /* No MWDMA */
625 .udma_mask = ATA_UDMA5,
626 .port_ops = &sis_66_ops,
627};
628static const struct ata_port_info sis_info133 = {
629 .flags = ATA_FLAG_SLAVE_POSS,
630 .pio_mask = ATA_PIO4,
631 .mwdma_mask = ATA_MWDMA2,
632 .udma_mask = ATA_UDMA6,
633 .port_ops = &sis_133_ops,
634};
635const struct ata_port_info sis_info133_for_sata = {
636 .flags = ATA_FLAG_SLAVE_POSS,
637 .pio_mask = ATA_PIO4,
638 /* No MWDMA */
639 .udma_mask = ATA_UDMA6,
640 .port_ops = &sis_133_for_sata_ops,
641};
642static const struct ata_port_info sis_info133_early = {
643 .flags = ATA_FLAG_SLAVE_POSS,
644 .pio_mask = ATA_PIO4,
645 /* No MWDMA */
646 .udma_mask = ATA_UDMA6,
647 .port_ops = &sis_133_early_ops,
648};
649
650/* Privately shared with the SiS180 SATA driver, not for use elsewhere */
651EXPORT_SYMBOL_GPL(sis_info133_for_sata);
652
653static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
654{
655 u16 regw;
656 u8 reg;
657
658 if (sis->info == &sis_info133) {
659 pci_read_config_word(pdev, 0x50, &regw);
660 if (regw & 0x08)
661 pci_write_config_word(pdev, 0x50, regw & ~0x08);
662 pci_read_config_word(pdev, 0x52, &regw);
663 if (regw & 0x08)
664 pci_write_config_word(pdev, 0x52, regw & ~0x08);
665 return;
666 }
667
668 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
669 /* Fix up latency */
670 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
671 /* Set compatibility bit */
672 pci_read_config_byte(pdev, 0x49, &reg);
673 if (!(reg & 0x01))
674 pci_write_config_byte(pdev, 0x49, reg | 0x01);
675 return;
676 }
677
678 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
679 /* Fix up latency */
680 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
681 /* Set compatibility bit */
682 pci_read_config_byte(pdev, 0x52, &reg);
683 if (!(reg & 0x04))
684 pci_write_config_byte(pdev, 0x52, reg | 0x04);
685 return;
686 }
687
688 if (sis->info == &sis_info33) {
689 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
690 if (( reg & 0x0F ) != 0x00)
691 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
692 /* Fall through to ATA16 fixup below */
693 }
694
695 if (sis->info == &sis_info || sis->info == &sis_info33) {
696 /* force per drive recovery and active timings
697 needed on ATA_33 and below chips */
698 pci_read_config_byte(pdev, 0x52, &reg);
699 if (!(reg & 0x08))
700 pci_write_config_byte(pdev, 0x52, reg|0x08);
701 return;
702 }
703
704 BUG();
705}
706
707/**
708 * sis_init_one - Register SiS ATA PCI device with kernel services
709 * @pdev: PCI device to register
710 * @ent: Entry in sis_pci_tbl matching with @pdev
711 *
712 * Called from kernel PCI layer. We probe for combined mode (sigh),
713 * and then hand over control to libata, for it to do the rest.
714 *
715 * LOCKING:
716 * Inherited from PCI layer (may sleep).
717 *
718 * RETURNS:
719 * Zero on success, or -ERRNO value.
720 */
721
722static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
723{
724 const struct ata_port_info *ppi[] = { NULL, NULL };
725 struct pci_dev *host = NULL;
726 struct sis_chipset *chipset = NULL;
727 struct sis_chipset *sets;
728 int rc;
729
730 static struct sis_chipset sis_chipsets[] = {
731
732 { 0x0968, &sis_info133 },
733 { 0x0966, &sis_info133 },
734 { 0x0965, &sis_info133 },
735 { 0x0745, &sis_info100 },
736 { 0x0735, &sis_info100 },
737 { 0x0733, &sis_info100 },
738 { 0x0635, &sis_info100 },
739 { 0x0633, &sis_info100 },
740
741 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
742 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
743
744 { 0x0640, &sis_info66 },
745 { 0x0630, &sis_info66 },
746 { 0x0620, &sis_info66 },
747 { 0x0540, &sis_info66 },
748 { 0x0530, &sis_info66 },
749
750 { 0x5600, &sis_info33 },
751 { 0x5598, &sis_info33 },
752 { 0x5597, &sis_info33 },
753 { 0x5591, &sis_info33 },
754 { 0x5582, &sis_info33 },
755 { 0x5581, &sis_info33 },
756
757 { 0x5596, &sis_info },
758 { 0x5571, &sis_info },
759 { 0x5517, &sis_info },
760 { 0x5511, &sis_info },
761
762 {0}
763 };
764 static struct sis_chipset sis133_early = {
765 0x0, &sis_info133_early
766 };
767 static struct sis_chipset sis133 = {
768 0x0, &sis_info133
769 };
770 static struct sis_chipset sis100_early = {
771 0x0, &sis_info100_early
772 };
773 static struct sis_chipset sis100 = {
774 0x0, &sis_info100
775 };
776
777 ata_print_version_once(&pdev->dev, DRV_VERSION);
778
779 rc = pcim_enable_device(pdev);
780 if (rc)
781 return rc;
782
783 /* We have to find the bridge first */
784 for (sets = &sis_chipsets[0]; sets->device; sets++) {
785 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
786 if (host != NULL) {
787 chipset = sets; /* Match found */
788 if (sets->device == 0x630) { /* SIS630 */
789 if (host->revision >= 0x30) /* 630 ET */
790 chipset = &sis100_early;
791 }
792 break;
793 }
794 }
795
796 /* Look for concealed bridges */
797 if (chipset == NULL) {
798 /* Second check */
799 u32 idemisc;
800 u16 trueid;
801
802 /* Disable ID masking and register remapping then
803 see what the real ID is */
804
805 pci_read_config_dword(pdev, 0x54, &idemisc);
806 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
807 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
808 pci_write_config_dword(pdev, 0x54, idemisc);
809
810 switch(trueid) {
811 case 0x5518: /* SIS 962/963 */
812 dev_info(&pdev->dev,
813 "SiS 962/963 MuTIOL IDE UDMA133 controller\n");
814 chipset = &sis133;
815 if ((idemisc & 0x40000000) == 0) {
816 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
817 dev_info(&pdev->dev,
818 "Switching to 5513 register mapping\n");
819 }
820 break;
821 case 0x0180: /* SIS 965/965L */
822 chipset = &sis133;
823 break;
824 case 0x1180: /* SIS 966/966L */
825 chipset = &sis133;
826 break;
827 }
828 }
829
830 /* Further check */
831 if (chipset == NULL) {
832 struct pci_dev *lpc_bridge;
833 u16 trueid;
834 u8 prefctl;
835 u8 idecfg;
836
837 /* Try the second unmasking technique */
838 pci_read_config_byte(pdev, 0x4a, &idecfg);
839 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
840 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
841 pci_write_config_byte(pdev, 0x4a, idecfg);
842
843 switch(trueid) {
844 case 0x5517:
845 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
846 if (lpc_bridge == NULL)
847 break;
848 pci_read_config_byte(pdev, 0x49, &prefctl);
849 pci_dev_put(lpc_bridge);
850
851 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
852 chipset = &sis133_early;
853 break;
854 }
855 chipset = &sis100;
856 break;
857 }
858 }
859 pci_dev_put(host);
860
861 /* No chipset info, no support */
862 if (chipset == NULL)
863 return -ENODEV;
864
865 ppi[0] = chipset->info;
866
867 sis_fixup(pdev, chipset);
868
869 return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0);
870}
871
872#ifdef CONFIG_PM_SLEEP
873static int sis_reinit_one(struct pci_dev *pdev)
874{
875 struct ata_host *host = pci_get_drvdata(pdev);
876 int rc;
877
878 rc = ata_pci_device_do_resume(pdev);
879 if (rc)
880 return rc;
881
882 sis_fixup(pdev, host->private_data);
883
884 ata_host_resume(host);
885 return 0;
886}
887#endif
888
889static const struct pci_device_id sis_pci_tbl[] = {
890 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
891 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
892 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
893
894 { }
895};
896
897static struct pci_driver sis_pci_driver = {
898 .name = DRV_NAME,
899 .id_table = sis_pci_tbl,
900 .probe = sis_init_one,
901 .remove = ata_pci_remove_one,
902#ifdef CONFIG_PM_SLEEP
903 .suspend = ata_pci_device_suspend,
904 .resume = sis_reinit_one,
905#endif
906};
907
908module_pci_driver(sis_pci_driver);
909
910MODULE_AUTHOR("Alan Cox");
911MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
912MODULE_LICENSE("GPL");
913MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
914MODULE_VERSION(DRV_VERSION);
915