1/*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/driver-api/libata.rst
25 *
26 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/gfp.h>
38#include <linux/pci.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <linux/libata.h>
45
46#define DRV_NAME "pdc_adma"
47#define DRV_VERSION "1.0"
48
49/* macro to calculate base address for ATA regs */
50#define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
51
52/* macro to calculate base address for ADMA regs */
53#define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
54
55/* macro to obtain addresses from ata_port */
56#define ADMA_PORT_REGS(ap) \
57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
58
59enum {
60 ADMA_MMIO_BAR = 4,
61
62 ADMA_PORTS = 2,
63 ADMA_CPB_BYTES = 40,
64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
66
67 ADMA_DMA_BOUNDARY = 0xffffffff,
68
69 /* global register offsets */
70 ADMA_MODE_LOCK = 0x00c7,
71
72 /* per-channel register offsets */
73 ADMA_CONTROL = 0x0000, /* ADMA control */
74 ADMA_STATUS = 0x0002, /* ADMA status */
75 ADMA_CPB_COUNT = 0x0004, /* CPB count */
76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
81
82 /* ADMA_CONTROL register bits */
83 aNIEN = (1 << 8), /* irq mask: 1==masked */
84 aGO = (1 << 7), /* packet trigger ("Go!") */
85 aRSTADM = (1 << 5), /* ADMA logic reset */
86 aPIOMD4 = 0x0003, /* PIO mode 4 */
87
88 /* ADMA_STATUS register bits */
89 aPSD = (1 << 6),
90 aUIRQ = (1 << 4),
91 aPERR = (1 << 0),
92
93 /* CPB bits */
94 cDONE = (1 << 0),
95 cATERR = (1 << 3),
96
97 cVLD = (1 << 0),
98 cDAT = (1 << 2),
99 cIEN = (1 << 3),
100
101 /* PRD bits */
102 pORD = (1 << 4),
103 pDIRO = (1 << 5),
104 pEND = (1 << 7),
105
106 /* ATA register flags */
107 rIGN = (1 << 5),
108 rEND = (1 << 7),
109
110 /* ATA register addresses */
111 ADMA_REGS_CONTROL = 0x0e,
112 ADMA_REGS_SECTOR_COUNT = 0x12,
113 ADMA_REGS_LBA_LOW = 0x13,
114 ADMA_REGS_LBA_MID = 0x14,
115 ADMA_REGS_LBA_HIGH = 0x15,
116 ADMA_REGS_DEVICE = 0x16,
117 ADMA_REGS_COMMAND = 0x17,
118
119 /* PCI device IDs */
120 board_1841_idx = 0, /* ADMA 2-port controller */
121};
122
123typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
124
125struct adma_port_priv {
126 u8 *pkt;
127 dma_addr_t pkt_dma;
128 adma_state_t state;
129};
130
131static int adma_ata_init_one(struct pci_dev *pdev,
132 const struct pci_device_id *ent);
133static int adma_port_start(struct ata_port *ap);
134static void adma_port_stop(struct ata_port *ap);
135static void adma_qc_prep(struct ata_queued_cmd *qc);
136static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
137static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
138static void adma_freeze(struct ata_port *ap);
139static void adma_thaw(struct ata_port *ap);
140static int adma_prereset(struct ata_link *link, unsigned long deadline);
141
142static struct scsi_host_template adma_ata_sht = {
143 ATA_BASE_SHT(DRV_NAME),
144 .sg_tablesize = LIBATA_MAX_PRD,
145 .dma_boundary = ADMA_DMA_BOUNDARY,
146};
147
148static struct ata_port_operations adma_ata_ops = {
149 .inherits = &ata_sff_port_ops,
150
151 .lost_interrupt = ATA_OP_NULL,
152
153 .check_atapi_dma = adma_check_atapi_dma,
154 .qc_prep = adma_qc_prep,
155 .qc_issue = adma_qc_issue,
156
157 .freeze = adma_freeze,
158 .thaw = adma_thaw,
159 .prereset = adma_prereset,
160
161 .port_start = adma_port_start,
162 .port_stop = adma_port_stop,
163};
164
165static struct ata_port_info adma_port_info[] = {
166 /* board_1841_idx */
167 {
168 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
169 .pio_mask = ATA_PIO4_ONLY,
170 .udma_mask = ATA_UDMA4,
171 .port_ops = &adma_ata_ops,
172 },
173};
174
175static const struct pci_device_id adma_ata_pci_tbl[] = {
176 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
177
178 { } /* terminate list */
179};
180
181static struct pci_driver adma_ata_pci_driver = {
182 .name = DRV_NAME,
183 .id_table = adma_ata_pci_tbl,
184 .probe = adma_ata_init_one,
185 .remove = ata_pci_remove_one,
186};
187
188static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
189{
190 return 1; /* ATAPI DMA not yet supported */
191}
192
193static void adma_reset_engine(struct ata_port *ap)
194{
195 void __iomem *chan = ADMA_PORT_REGS(ap);
196
197 /* reset ADMA to idle state */
198 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
199 udelay(2);
200 writew(aPIOMD4, chan + ADMA_CONTROL);
201 udelay(2);
202}
203
204static void adma_reinit_engine(struct ata_port *ap)
205{
206 struct adma_port_priv *pp = ap->private_data;
207 void __iomem *chan = ADMA_PORT_REGS(ap);
208
209 /* mask/clear ATA interrupts */
210 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
211 ata_sff_check_status(ap);
212
213 /* reset the ADMA engine */
214 adma_reset_engine(ap);
215
216 /* set in-FIFO threshold to 0x100 */
217 writew(0x100, chan + ADMA_FIFO_IN);
218
219 /* set CPB pointer */
220 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
221
222 /* set out-FIFO threshold to 0x100 */
223 writew(0x100, chan + ADMA_FIFO_OUT);
224
225 /* set CPB count */
226 writew(1, chan + ADMA_CPB_COUNT);
227
228 /* read/discard ADMA status */
229 readb(chan + ADMA_STATUS);
230}
231
232static inline void adma_enter_reg_mode(struct ata_port *ap)
233{
234 void __iomem *chan = ADMA_PORT_REGS(ap);
235
236 writew(aPIOMD4, chan + ADMA_CONTROL);
237 readb(chan + ADMA_STATUS); /* flush */
238}
239
240static void adma_freeze(struct ata_port *ap)
241{
242 void __iomem *chan = ADMA_PORT_REGS(ap);
243
244 /* mask/clear ATA interrupts */
245 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
246 ata_sff_check_status(ap);
247
248 /* reset ADMA to idle state */
249 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
250 udelay(2);
251 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
252 udelay(2);
253}
254
255static void adma_thaw(struct ata_port *ap)
256{
257 adma_reinit_engine(ap);
258}
259
260static int adma_prereset(struct ata_link *link, unsigned long deadline)
261{
262 struct ata_port *ap = link->ap;
263 struct adma_port_priv *pp = ap->private_data;
264
265 if (pp->state != adma_state_idle) /* healthy paranoia */
266 pp->state = adma_state_mmio;
267 adma_reinit_engine(ap);
268
269 return ata_sff_prereset(link, deadline);
270}
271
272static int adma_fill_sg(struct ata_queued_cmd *qc)
273{
274 struct scatterlist *sg;
275 struct ata_port *ap = qc->ap;
276 struct adma_port_priv *pp = ap->private_data;
277 u8 *buf = pp->pkt, *last_buf = NULL;
278 int i = (2 + buf[3]) * 8;
279 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
280 unsigned int si;
281
282 for_each_sg(qc->sg, sg, qc->n_elem, si) {
283 u32 addr;
284 u32 len;
285
286 addr = (u32)sg_dma_address(sg);
287 *(__le32 *)(buf + i) = cpu_to_le32(addr);
288 i += 4;
289
290 len = sg_dma_len(sg) >> 3;
291 *(__le32 *)(buf + i) = cpu_to_le32(len);
292 i += 4;
293
294 last_buf = &buf[i];
295 buf[i++] = pFLAGS;
296 buf[i++] = qc->dev->dma_mode & 0xf;
297 buf[i++] = 0; /* pPKLW */
298 buf[i++] = 0; /* reserved */
299
300 *(__le32 *)(buf + i) =
301 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
302 i += 4;
303
304 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
305 (unsigned long)addr, len);
306 }
307
308 if (likely(last_buf))
309 *last_buf |= pEND;
310
311 return i;
312}
313
314static void adma_qc_prep(struct ata_queued_cmd *qc)
315{
316 struct adma_port_priv *pp = qc->ap->private_data;
317 u8 *buf = pp->pkt;
318 u32 pkt_dma = (u32)pp->pkt_dma;
319 int i = 0;
320
321 VPRINTK("ENTER\n");
322
323 adma_enter_reg_mode(qc->ap);
324 if (qc->tf.protocol != ATA_PROT_DMA)
325 return;
326
327 buf[i++] = 0; /* Response flags */
328 buf[i++] = 0; /* reserved */
329 buf[i++] = cVLD | cDAT | cIEN;
330 i++; /* cLEN, gets filled in below */
331
332 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
333 i += 4; /* cNCPB */
334 i += 4; /* cPRD, gets filled in below */
335
336 buf[i++] = 0; /* reserved */
337 buf[i++] = 0; /* reserved */
338 buf[i++] = 0; /* reserved */
339 buf[i++] = 0; /* reserved */
340
341 /* ATA registers; must be a multiple of 4 */
342 buf[i++] = qc->tf.device;
343 buf[i++] = ADMA_REGS_DEVICE;
344 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
345 buf[i++] = qc->tf.hob_nsect;
346 buf[i++] = ADMA_REGS_SECTOR_COUNT;
347 buf[i++] = qc->tf.hob_lbal;
348 buf[i++] = ADMA_REGS_LBA_LOW;
349 buf[i++] = qc->tf.hob_lbam;
350 buf[i++] = ADMA_REGS_LBA_MID;
351 buf[i++] = qc->tf.hob_lbah;
352 buf[i++] = ADMA_REGS_LBA_HIGH;
353 }
354 buf[i++] = qc->tf.nsect;
355 buf[i++] = ADMA_REGS_SECTOR_COUNT;
356 buf[i++] = qc->tf.lbal;
357 buf[i++] = ADMA_REGS_LBA_LOW;
358 buf[i++] = qc->tf.lbam;
359 buf[i++] = ADMA_REGS_LBA_MID;
360 buf[i++] = qc->tf.lbah;
361 buf[i++] = ADMA_REGS_LBA_HIGH;
362 buf[i++] = 0;
363 buf[i++] = ADMA_REGS_CONTROL;
364 buf[i++] = rIGN;
365 buf[i++] = 0;
366 buf[i++] = qc->tf.command;
367 buf[i++] = ADMA_REGS_COMMAND | rEND;
368
369 buf[3] = (i >> 3) - 2; /* cLEN */
370 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
371
372 i = adma_fill_sg(qc);
373 wmb(); /* flush PRDs and pkt to memory */
374#if 0
375 /* dump out CPB + PRDs for debug */
376 {
377 int j, len = 0;
378 static char obuf[2048];
379 for (j = 0; j < i; ++j) {
380 len += sprintf(obuf+len, "%02x ", buf[j]);
381 if ((j & 7) == 7) {
382 printk("%s\n", obuf);
383 len = 0;
384 }
385 }
386 if (len)
387 printk("%s\n", obuf);
388 }
389#endif
390}
391
392static inline void adma_packet_start(struct ata_queued_cmd *qc)
393{
394 struct ata_port *ap = qc->ap;
395 void __iomem *chan = ADMA_PORT_REGS(ap);
396
397 VPRINTK("ENTER, ap %p\n", ap);
398
399 /* fire up the ADMA engine */
400 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
401}
402
403static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
404{
405 struct adma_port_priv *pp = qc->ap->private_data;
406
407 switch (qc->tf.protocol) {
408 case ATA_PROT_DMA:
409 pp->state = adma_state_pkt;
410 adma_packet_start(qc);
411 return 0;
412
413 case ATAPI_PROT_DMA:
414 BUG();
415 break;
416
417 default:
418 break;
419 }
420
421 pp->state = adma_state_mmio;
422 return ata_sff_qc_issue(qc);
423}
424
425static inline unsigned int adma_intr_pkt(struct ata_host *host)
426{
427 unsigned int handled = 0, port_no;
428
429 for (port_no = 0; port_no < host->n_ports; ++port_no) {
430 struct ata_port *ap = host->ports[port_no];
431 struct adma_port_priv *pp;
432 struct ata_queued_cmd *qc;
433 void __iomem *chan = ADMA_PORT_REGS(ap);
434 u8 status = readb(chan + ADMA_STATUS);
435
436 if (status == 0)
437 continue;
438 handled = 1;
439 adma_enter_reg_mode(ap);
440 pp = ap->private_data;
441 if (!pp || pp->state != adma_state_pkt)
442 continue;
443 qc = ata_qc_from_tag(ap, ap->link.active_tag);
444 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
445 if (status & aPERR)
446 qc->err_mask |= AC_ERR_HOST_BUS;
447 else if ((status & (aPSD | aUIRQ)))
448 qc->err_mask |= AC_ERR_OTHER;
449
450 if (pp->pkt[0] & cATERR)
451 qc->err_mask |= AC_ERR_DEV;
452 else if (pp->pkt[0] != cDONE)
453 qc->err_mask |= AC_ERR_OTHER;
454
455 if (!qc->err_mask)
456 ata_qc_complete(qc);
457 else {
458 struct ata_eh_info *ehi = &ap->link.eh_info;
459 ata_ehi_clear_desc(ehi);
460 ata_ehi_push_desc(ehi,
461 "ADMA-status 0x%02X", status);
462 ata_ehi_push_desc(ehi,
463 "pkt[0] 0x%02X", pp->pkt[0]);
464
465 if (qc->err_mask == AC_ERR_DEV)
466 ata_port_abort(ap);
467 else
468 ata_port_freeze(ap);
469 }
470 }
471 }
472 return handled;
473}
474
475static inline unsigned int adma_intr_mmio(struct ata_host *host)
476{
477 unsigned int handled = 0, port_no;
478
479 for (port_no = 0; port_no < host->n_ports; ++port_no) {
480 struct ata_port *ap = host->ports[port_no];
481 struct adma_port_priv *pp = ap->private_data;
482 struct ata_queued_cmd *qc;
483
484 if (!pp || pp->state != adma_state_mmio)
485 continue;
486 qc = ata_qc_from_tag(ap, ap->link.active_tag);
487 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
488
489 /* check main status, clearing INTRQ */
490 u8 status = ata_sff_check_status(ap);
491 if ((status & ATA_BUSY))
492 continue;
493 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
494 ap->print_id, qc->tf.protocol, status);
495
496 /* complete taskfile transaction */
497 pp->state = adma_state_idle;
498 qc->err_mask |= ac_err_mask(status);
499 if (!qc->err_mask)
500 ata_qc_complete(qc);
501 else {
502 struct ata_eh_info *ehi = &ap->link.eh_info;
503 ata_ehi_clear_desc(ehi);
504 ata_ehi_push_desc(ehi, "status 0x%02X", status);
505
506 if (qc->err_mask == AC_ERR_DEV)
507 ata_port_abort(ap);
508 else
509 ata_port_freeze(ap);
510 }
511 handled = 1;
512 }
513 }
514 return handled;
515}
516
517static irqreturn_t adma_intr(int irq, void *dev_instance)
518{
519 struct ata_host *host = dev_instance;
520 unsigned int handled = 0;
521
522 VPRINTK("ENTER\n");
523
524 spin_lock(&host->lock);
525 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
526 spin_unlock(&host->lock);
527
528 VPRINTK("EXIT\n");
529
530 return IRQ_RETVAL(handled);
531}
532
533static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
534{
535 port->cmd_addr =
536 port->data_addr = base + 0x000;
537 port->error_addr =
538 port->feature_addr = base + 0x004;
539 port->nsect_addr = base + 0x008;
540 port->lbal_addr = base + 0x00c;
541 port->lbam_addr = base + 0x010;
542 port->lbah_addr = base + 0x014;
543 port->device_addr = base + 0x018;
544 port->status_addr =
545 port->command_addr = base + 0x01c;
546 port->altstatus_addr =
547 port->ctl_addr = base + 0x038;
548}
549
550static int adma_port_start(struct ata_port *ap)
551{
552 struct device *dev = ap->host->dev;
553 struct adma_port_priv *pp;
554
555 adma_enter_reg_mode(ap);
556 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
557 if (!pp)
558 return -ENOMEM;
559 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
560 GFP_KERNEL);
561 if (!pp->pkt)
562 return -ENOMEM;
563 /* paranoia? */
564 if ((pp->pkt_dma & 7) != 0) {
565 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
566 (u32)pp->pkt_dma);
567 return -ENOMEM;
568 }
569 memset(pp->pkt, 0, ADMA_PKT_BYTES);
570 ap->private_data = pp;
571 adma_reinit_engine(ap);
572 return 0;
573}
574
575static void adma_port_stop(struct ata_port *ap)
576{
577 adma_reset_engine(ap);
578}
579
580static void adma_host_init(struct ata_host *host, unsigned int chip_id)
581{
582 unsigned int port_no;
583
584 /* enable/lock aGO operation */
585 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
586
587 /* reset the ADMA logic */
588 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
589 adma_reset_engine(host->ports[port_no]);
590}
591
592static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
593{
594 int rc;
595
596 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
597 if (rc) {
598 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
599 return rc;
600 }
601 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
602 if (rc) {
603 dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
604 return rc;
605 }
606 return 0;
607}
608
609static int adma_ata_init_one(struct pci_dev *pdev,
610 const struct pci_device_id *ent)
611{
612 unsigned int board_idx = (unsigned int) ent->driver_data;
613 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
614 struct ata_host *host;
615 void __iomem *mmio_base;
616 int rc, port_no;
617
618 ata_print_version_once(&pdev->dev, DRV_VERSION);
619
620 /* alloc host */
621 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
622 if (!host)
623 return -ENOMEM;
624
625 /* acquire resources and fill host */
626 rc = pcim_enable_device(pdev);
627 if (rc)
628 return rc;
629
630 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
631 return -ENODEV;
632
633 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
634 if (rc)
635 return rc;
636 host->iomap = pcim_iomap_table(pdev);
637 mmio_base = host->iomap[ADMA_MMIO_BAR];
638
639 rc = adma_set_dma_masks(pdev, mmio_base);
640 if (rc)
641 return rc;
642
643 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
644 struct ata_port *ap = host->ports[port_no];
645 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
646 unsigned int offset = port_base - mmio_base;
647
648 adma_ata_setup_port(&ap->ioaddr, port_base);
649
650 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
651 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
652 }
653
654 /* initialize adapter */
655 adma_host_init(host, board_idx);
656
657 pci_set_master(pdev);
658 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
659 &adma_ata_sht);
660}
661
662module_pci_driver(adma_ata_pci_driver);
663
664MODULE_AUTHOR("Mark Lord");
665MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
666MODULE_LICENSE("GPL");
667MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
668MODULE_VERSION(DRV_VERSION);
669