1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Cortina Systems Gemini SATA bridge add-on to Faraday FTIDE010 |
4 | * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> |
5 | */ |
6 | |
7 | #include <linux/init.h> |
8 | #include <linux/module.h> |
9 | #include <linux/platform_device.h> |
10 | #include <linux/bitops.h> |
11 | #include <linux/mfd/syscon.h> |
12 | #include <linux/regmap.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/reset.h> |
15 | #include <linux/of.h> |
16 | #include <linux/clk.h> |
17 | #include <linux/io.h> |
18 | #include <linux/pinctrl/consumer.h> |
19 | #include "sata_gemini.h" |
20 | |
21 | #define DRV_NAME "gemini_sata_bridge" |
22 | |
23 | /** |
24 | * struct sata_gemini - a state container for a Gemini SATA bridge |
25 | * @dev: the containing device |
26 | * @base: remapped I/O memory base |
27 | * @muxmode: the current muxing mode |
28 | * @ide_pins: if the device is using the plain IDE interface pins |
29 | * @sata_bridge: if the device enables the SATA bridge |
30 | * @sata0_reset: SATA0 reset handler |
31 | * @sata1_reset: SATA1 reset handler |
32 | * @sata0_pclk: SATA0 PCLK handler |
33 | * @sata1_pclk: SATA1 PCLK handler |
34 | */ |
35 | struct sata_gemini { |
36 | struct device *dev; |
37 | void __iomem *base; |
38 | enum gemini_muxmode muxmode; |
39 | bool ide_pins; |
40 | bool sata_bridge; |
41 | struct reset_control *sata0_reset; |
42 | struct reset_control *sata1_reset; |
43 | struct clk *sata0_pclk; |
44 | struct clk *sata1_pclk; |
45 | }; |
46 | |
47 | /* Miscellaneous Control Register */ |
48 | #define GEMINI_GLOBAL_MISC_CTRL 0x30 |
49 | /* |
50 | * Values of IDE IOMUX bits in the misc control register |
51 | * |
52 | * Bits 26:24 are "IDE IO Select", which decides what SATA |
53 | * adapters are connected to which of the two IDE/ATA |
54 | * controllers in the Gemini. We can connect the two IDE blocks |
55 | * to one SATA adapter each, both acting as master, or one IDE |
56 | * blocks to two SATA adapters so the IDE block can act in a |
57 | * master/slave configuration. |
58 | * |
59 | * We also bring out different blocks on the actual IDE |
60 | * pins (not SATA pins) if (and only if) these are muxed in. |
61 | * |
62 | * 111-100 - Reserved |
63 | * Mode 0: 000 - ata0 master <-> sata0 |
64 | * ata1 master <-> sata1 |
65 | * ata0 slave interface brought out on IDE pads |
66 | * Mode 1: 001 - ata0 master <-> sata0 |
67 | * ata1 master <-> sata1 |
68 | * ata1 slave interface brought out on IDE pads |
69 | * Mode 2: 010 - ata1 master <-> sata1 |
70 | * ata1 slave <-> sata0 |
71 | * ata0 master and slave interfaces brought out |
72 | * on IDE pads |
73 | * Mode 3: 011 - ata0 master <-> sata0 |
74 | * ata1 slave <-> sata1 |
75 | * ata1 master and slave interfaces brought out |
76 | * on IDE pads |
77 | */ |
78 | #define GEMINI_IDE_IOMUX_MASK (7 << 24) |
79 | #define GEMINI_IDE_IOMUX_MODE0 (0 << 24) |
80 | #define GEMINI_IDE_IOMUX_MODE1 (1 << 24) |
81 | #define GEMINI_IDE_IOMUX_MODE2 (2 << 24) |
82 | #define GEMINI_IDE_IOMUX_MODE3 (3 << 24) |
83 | #define GEMINI_IDE_IOMUX_SHIFT (24) |
84 | |
85 | /* |
86 | * Registers directly controlling the PATA<->SATA adapters |
87 | */ |
88 | #define GEMINI_SATA_ID 0x00 |
89 | #define GEMINI_SATA_PHY_ID 0x04 |
90 | #define GEMINI_SATA0_STATUS 0x08 |
91 | #define GEMINI_SATA1_STATUS 0x0c |
92 | #define GEMINI_SATA0_CTRL 0x18 |
93 | #define GEMINI_SATA1_CTRL 0x1c |
94 | |
95 | #define GEMINI_SATA_STATUS_BIST_DONE BIT(5) |
96 | #define GEMINI_SATA_STATUS_BIST_OK BIT(4) |
97 | #define GEMINI_SATA_STATUS_PHY_READY BIT(0) |
98 | |
99 | #define GEMINI_SATA_CTRL_PHY_BIST_EN BIT(14) |
100 | #define GEMINI_SATA_CTRL_PHY_FORCE_IDLE BIT(13) |
101 | #define GEMINI_SATA_CTRL_PHY_FORCE_READY BIT(12) |
102 | #define GEMINI_SATA_CTRL_PHY_AFE_LOOP_EN BIT(10) |
103 | #define GEMINI_SATA_CTRL_PHY_DIG_LOOP_EN BIT(9) |
104 | #define GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN BIT(4) |
105 | #define GEMINI_SATA_CTRL_ATAPI_EN BIT(3) |
106 | #define GEMINI_SATA_CTRL_BUS_WITH_20 BIT(2) |
107 | #define GEMINI_SATA_CTRL_SLAVE_EN BIT(1) |
108 | #define GEMINI_SATA_CTRL_EN BIT(0) |
109 | |
110 | /* |
111 | * There is only ever one instance of this bridge on a system, |
112 | * so create a singleton so that the FTIDE010 instances can grab |
113 | * a reference to it. |
114 | */ |
115 | static struct sata_gemini *sg_singleton; |
116 | |
117 | struct sata_gemini *gemini_sata_bridge_get(void) |
118 | { |
119 | if (sg_singleton) |
120 | return sg_singleton; |
121 | return ERR_PTR(error: -EPROBE_DEFER); |
122 | } |
123 | EXPORT_SYMBOL(gemini_sata_bridge_get); |
124 | |
125 | bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1) |
126 | { |
127 | if (!sg->sata_bridge) |
128 | return false; |
129 | /* |
130 | * In muxmode 2 and 3 one of the ATA controllers is |
131 | * actually not connected to any SATA bridge. |
132 | */ |
133 | if ((sg->muxmode == GEMINI_MUXMODE_2) && |
134 | !is_ata1) |
135 | return false; |
136 | if ((sg->muxmode == GEMINI_MUXMODE_3) && |
137 | is_ata1) |
138 | return false; |
139 | |
140 | return true; |
141 | } |
142 | EXPORT_SYMBOL(gemini_sata_bridge_enabled); |
143 | |
144 | enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg) |
145 | { |
146 | return sg->muxmode; |
147 | } |
148 | EXPORT_SYMBOL(gemini_sata_get_muxmode); |
149 | |
150 | static int gemini_sata_setup_bridge(struct sata_gemini *sg, |
151 | unsigned int bridge) |
152 | { |
153 | unsigned long timeout = jiffies + (HZ * 1); |
154 | bool bridge_online; |
155 | u32 val; |
156 | |
157 | if (bridge == 0) { |
158 | val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; |
159 | /* SATA0 slave mode is only used in muxmode 2 */ |
160 | if (sg->muxmode == GEMINI_MUXMODE_2) |
161 | val |= GEMINI_SATA_CTRL_SLAVE_EN; |
162 | writel(val, addr: sg->base + GEMINI_SATA0_CTRL); |
163 | } else { |
164 | val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; |
165 | /* SATA1 slave mode is only used in muxmode 3 */ |
166 | if (sg->muxmode == GEMINI_MUXMODE_3) |
167 | val |= GEMINI_SATA_CTRL_SLAVE_EN; |
168 | writel(val, addr: sg->base + GEMINI_SATA1_CTRL); |
169 | } |
170 | |
171 | /* Vendor code waits 10 ms here */ |
172 | msleep(msecs: 10); |
173 | |
174 | /* Wait for PHY to become ready */ |
175 | do { |
176 | msleep(msecs: 100); |
177 | |
178 | if (bridge == 0) |
179 | val = readl(addr: sg->base + GEMINI_SATA0_STATUS); |
180 | else |
181 | val = readl(addr: sg->base + GEMINI_SATA1_STATUS); |
182 | if (val & GEMINI_SATA_STATUS_PHY_READY) |
183 | break; |
184 | } while (time_before(jiffies, timeout)); |
185 | |
186 | bridge_online = !!(val & GEMINI_SATA_STATUS_PHY_READY); |
187 | |
188 | dev_info(sg->dev, "SATA%d PHY %s\n" , bridge, |
189 | bridge_online ? "ready" : "not ready" ); |
190 | |
191 | return bridge_online ? 0: -ENODEV; |
192 | } |
193 | |
194 | int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge) |
195 | { |
196 | struct clk *pclk; |
197 | int ret; |
198 | |
199 | if (bridge == 0) |
200 | pclk = sg->sata0_pclk; |
201 | else |
202 | pclk = sg->sata1_pclk; |
203 | clk_enable(clk: pclk); |
204 | msleep(msecs: 10); |
205 | |
206 | /* Do not keep clocking a bridge that is not online */ |
207 | ret = gemini_sata_setup_bridge(sg, bridge); |
208 | if (ret) |
209 | clk_disable(clk: pclk); |
210 | |
211 | return ret; |
212 | } |
213 | EXPORT_SYMBOL(gemini_sata_start_bridge); |
214 | |
215 | void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge) |
216 | { |
217 | if (bridge == 0) |
218 | clk_disable(clk: sg->sata0_pclk); |
219 | else if (bridge == 1) |
220 | clk_disable(clk: sg->sata1_pclk); |
221 | } |
222 | EXPORT_SYMBOL(gemini_sata_stop_bridge); |
223 | |
224 | int gemini_sata_reset_bridge(struct sata_gemini *sg, |
225 | unsigned int bridge) |
226 | { |
227 | if (bridge == 0) |
228 | reset_control_reset(rstc: sg->sata0_reset); |
229 | else |
230 | reset_control_reset(rstc: sg->sata1_reset); |
231 | msleep(msecs: 10); |
232 | return gemini_sata_setup_bridge(sg, bridge); |
233 | } |
234 | EXPORT_SYMBOL(gemini_sata_reset_bridge); |
235 | |
236 | static int gemini_sata_bridge_init(struct sata_gemini *sg) |
237 | { |
238 | struct device *dev = sg->dev; |
239 | u32 sata_id, sata_phy_id; |
240 | int ret; |
241 | |
242 | sg->sata0_pclk = devm_clk_get(dev, id: "SATA0_PCLK" ); |
243 | if (IS_ERR(ptr: sg->sata0_pclk)) { |
244 | dev_err(dev, "no SATA0 PCLK" ); |
245 | return -ENODEV; |
246 | } |
247 | sg->sata1_pclk = devm_clk_get(dev, id: "SATA1_PCLK" ); |
248 | if (IS_ERR(ptr: sg->sata1_pclk)) { |
249 | dev_err(dev, "no SATA1 PCLK" ); |
250 | return -ENODEV; |
251 | } |
252 | |
253 | ret = clk_prepare_enable(clk: sg->sata0_pclk); |
254 | if (ret) { |
255 | dev_err(dev, "failed to enable SATA0 PCLK\n" ); |
256 | return ret; |
257 | } |
258 | ret = clk_prepare_enable(clk: sg->sata1_pclk); |
259 | if (ret) { |
260 | dev_err(dev, "failed to enable SATA1 PCLK\n" ); |
261 | clk_disable_unprepare(clk: sg->sata0_pclk); |
262 | return ret; |
263 | } |
264 | |
265 | sg->sata0_reset = devm_reset_control_get_exclusive(dev, id: "sata0" ); |
266 | if (IS_ERR(ptr: sg->sata0_reset)) { |
267 | dev_err(dev, "no SATA0 reset controller\n" ); |
268 | clk_disable_unprepare(clk: sg->sata1_pclk); |
269 | clk_disable_unprepare(clk: sg->sata0_pclk); |
270 | return PTR_ERR(ptr: sg->sata0_reset); |
271 | } |
272 | sg->sata1_reset = devm_reset_control_get_exclusive(dev, id: "sata1" ); |
273 | if (IS_ERR(ptr: sg->sata1_reset)) { |
274 | dev_err(dev, "no SATA1 reset controller\n" ); |
275 | clk_disable_unprepare(clk: sg->sata1_pclk); |
276 | clk_disable_unprepare(clk: sg->sata0_pclk); |
277 | return PTR_ERR(ptr: sg->sata1_reset); |
278 | } |
279 | |
280 | sata_id = readl(addr: sg->base + GEMINI_SATA_ID); |
281 | sata_phy_id = readl(addr: sg->base + GEMINI_SATA_PHY_ID); |
282 | sg->sata_bridge = true; |
283 | clk_disable(clk: sg->sata0_pclk); |
284 | clk_disable(clk: sg->sata1_pclk); |
285 | |
286 | dev_info(dev, "SATA ID %08x, PHY ID: %08x\n" , sata_id, sata_phy_id); |
287 | |
288 | return 0; |
289 | } |
290 | |
291 | static int gemini_setup_ide_pins(struct device *dev) |
292 | { |
293 | struct pinctrl *p; |
294 | struct pinctrl_state *ide_state; |
295 | int ret; |
296 | |
297 | p = devm_pinctrl_get(dev); |
298 | if (IS_ERR(ptr: p)) |
299 | return PTR_ERR(ptr: p); |
300 | |
301 | ide_state = pinctrl_lookup_state(p, name: "ide" ); |
302 | if (IS_ERR(ptr: ide_state)) |
303 | return PTR_ERR(ptr: ide_state); |
304 | |
305 | ret = pinctrl_select_state(p, s: ide_state); |
306 | if (ret) { |
307 | dev_err(dev, "could not select IDE state\n" ); |
308 | return ret; |
309 | } |
310 | |
311 | return 0; |
312 | } |
313 | |
314 | static int gemini_sata_probe(struct platform_device *pdev) |
315 | { |
316 | struct device *dev = &pdev->dev; |
317 | struct device_node *np = dev->of_node; |
318 | struct sata_gemini *sg; |
319 | struct regmap *map; |
320 | enum gemini_muxmode muxmode; |
321 | u32 gmode; |
322 | u32 gmask; |
323 | int ret; |
324 | |
325 | sg = devm_kzalloc(dev, size: sizeof(*sg), GFP_KERNEL); |
326 | if (!sg) |
327 | return -ENOMEM; |
328 | sg->dev = dev; |
329 | |
330 | sg->base = devm_platform_ioremap_resource(pdev, index: 0); |
331 | if (IS_ERR(ptr: sg->base)) |
332 | return PTR_ERR(ptr: sg->base); |
333 | |
334 | map = syscon_regmap_lookup_by_phandle(np, property: "syscon" ); |
335 | if (IS_ERR(ptr: map)) { |
336 | dev_err(dev, "no global syscon\n" ); |
337 | return PTR_ERR(ptr: map); |
338 | } |
339 | |
340 | /* Set up the SATA bridge if need be */ |
341 | if (of_property_read_bool(np, propname: "cortina,gemini-enable-sata-bridge" )) { |
342 | ret = gemini_sata_bridge_init(sg); |
343 | if (ret) |
344 | return ret; |
345 | } |
346 | |
347 | if (of_property_read_bool(np, propname: "cortina,gemini-enable-ide-pins" )) |
348 | sg->ide_pins = true; |
349 | |
350 | if (!sg->sata_bridge && !sg->ide_pins) { |
351 | dev_err(dev, "neither SATA bridge or IDE output enabled\n" ); |
352 | ret = -EINVAL; |
353 | goto out_unprep_clk; |
354 | } |
355 | |
356 | ret = of_property_read_u32(np, propname: "cortina,gemini-ata-muxmode" , out_value: &muxmode); |
357 | if (ret) { |
358 | dev_err(dev, "could not parse ATA muxmode\n" ); |
359 | goto out_unprep_clk; |
360 | } |
361 | if (muxmode > GEMINI_MUXMODE_3) { |
362 | dev_err(dev, "illegal muxmode %d\n" , muxmode); |
363 | ret = -EINVAL; |
364 | goto out_unprep_clk; |
365 | } |
366 | sg->muxmode = muxmode; |
367 | gmask = GEMINI_IDE_IOMUX_MASK; |
368 | gmode = (muxmode << GEMINI_IDE_IOMUX_SHIFT); |
369 | |
370 | ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask: gmask, val: gmode); |
371 | if (ret) { |
372 | dev_err(dev, "unable to set up IDE muxing\n" ); |
373 | ret = -ENODEV; |
374 | goto out_unprep_clk; |
375 | } |
376 | |
377 | /* |
378 | * Route out the IDE pins if desired. |
379 | * This is done by looking up a special pin control state called |
380 | * "ide" that will route out the IDE pins. |
381 | */ |
382 | if (sg->ide_pins) { |
383 | ret = gemini_setup_ide_pins(dev); |
384 | if (ret) |
385 | return ret; |
386 | } |
387 | |
388 | dev_info(dev, "set up the Gemini IDE/SATA nexus\n" ); |
389 | platform_set_drvdata(pdev, data: sg); |
390 | sg_singleton = sg; |
391 | |
392 | return 0; |
393 | |
394 | out_unprep_clk: |
395 | if (sg->sata_bridge) { |
396 | clk_unprepare(clk: sg->sata1_pclk); |
397 | clk_unprepare(clk: sg->sata0_pclk); |
398 | } |
399 | return ret; |
400 | } |
401 | |
402 | static void gemini_sata_remove(struct platform_device *pdev) |
403 | { |
404 | struct sata_gemini *sg = platform_get_drvdata(pdev); |
405 | |
406 | if (sg->sata_bridge) { |
407 | clk_unprepare(clk: sg->sata1_pclk); |
408 | clk_unprepare(clk: sg->sata0_pclk); |
409 | } |
410 | sg_singleton = NULL; |
411 | } |
412 | |
413 | static const struct of_device_id gemini_sata_of_match[] = { |
414 | { .compatible = "cortina,gemini-sata-bridge" , }, |
415 | { /* sentinel */ } |
416 | }; |
417 | |
418 | static struct platform_driver gemini_sata_driver = { |
419 | .driver = { |
420 | .name = DRV_NAME, |
421 | .of_match_table = gemini_sata_of_match, |
422 | }, |
423 | .probe = gemini_sata_probe, |
424 | .remove_new = gemini_sata_remove, |
425 | }; |
426 | module_platform_driver(gemini_sata_driver); |
427 | |
428 | MODULE_DESCRIPTION("low level driver for Cortina Systems Gemini SATA bridge" ); |
429 | MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>" ); |
430 | MODULE_LICENSE("GPL" ); |
431 | MODULE_ALIAS("platform:" DRV_NAME); |
432 | |