1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * sata_inic162x.c - Driver for Initio 162x SATA controllers |
4 | * |
5 | * Copyright 2006 SUSE Linux Products GmbH |
6 | * Copyright 2006 Tejun Heo <teheo@novell.com> |
7 | * |
8 | * **** WARNING **** |
9 | * |
10 | * This driver never worked properly and unfortunately data corruption is |
11 | * relatively common. There isn't anyone working on the driver and there's |
12 | * no support from the vendor. Do not use this driver in any production |
13 | * environment. |
14 | * |
15 | * http://thread.gmane.org/gmane.linux.debian.devel.bugs.rc/378525/focus=54491 |
16 | * https://bugzilla.kernel.org/show_bug.cgi?id=60565 |
17 | * |
18 | * ***************** |
19 | * |
20 | * This controller is eccentric and easily locks up if something isn't |
21 | * right. Documentation is available at initio's website but it only |
22 | * documents registers (not programming model). |
23 | * |
24 | * This driver has interesting history. The first version was written |
25 | * from the documentation and a 2.4 IDE driver posted on a Taiwan |
26 | * company, which didn't use any IDMA features and couldn't handle |
27 | * LBA48. The resulting driver couldn't handle LBA48 devices either |
28 | * making it pretty useless. |
29 | * |
30 | * After a while, initio picked the driver up, renamed it to |
31 | * sata_initio162x, updated it to use IDMA for ATA DMA commands and |
32 | * posted it on their website. It only used ATA_PROT_DMA for IDMA and |
33 | * attaching both devices and issuing IDMA and !IDMA commands |
34 | * simultaneously broke it due to PIRQ masking interaction but it did |
35 | * show how to use the IDMA (ADMA + some initio specific twists) |
36 | * engine. |
37 | * |
38 | * Then, I picked up their changes again and here's the usable driver |
39 | * which uses IDMA for everything. Everything works now including |
40 | * LBA48, CD/DVD burning, suspend/resume and hotplug. There are some |
41 | * issues tho. Result Tf is not resported properly, NCQ isn't |
42 | * supported yet and CD/DVD writing works with DMA assisted PIO |
43 | * protocol (which, for native SATA devices, shouldn't cause any |
44 | * noticeable difference). |
45 | * |
46 | * Anyways, so, here's finally a working driver for inic162x. Enjoy! |
47 | * |
48 | * initio: If you guys wanna improve the driver regarding result TF |
49 | * access and other stuff, please feel free to contact me. I'll be |
50 | * happy to assist. |
51 | */ |
52 | |
53 | #include <linux/gfp.h> |
54 | #include <linux/kernel.h> |
55 | #include <linux/module.h> |
56 | #include <linux/pci.h> |
57 | #include <scsi/scsi_host.h> |
58 | #include <linux/libata.h> |
59 | #include <linux/blkdev.h> |
60 | #include <scsi/scsi_device.h> |
61 | |
62 | #define DRV_NAME "sata_inic162x" |
63 | #define DRV_VERSION "0.4" |
64 | |
65 | enum { |
66 | MMIO_BAR_PCI = 5, |
67 | MMIO_BAR_CARDBUS = 1, |
68 | |
69 | NR_PORTS = 2, |
70 | |
71 | IDMA_CPB_TBL_SIZE = 4 * 32, |
72 | |
73 | INIC_DMA_BOUNDARY = 0xffffff, |
74 | |
75 | HOST_ACTRL = 0x08, |
76 | HOST_CTL = 0x7c, |
77 | HOST_STAT = 0x7e, |
78 | HOST_IRQ_STAT = 0xbc, |
79 | HOST_IRQ_MASK = 0xbe, |
80 | |
81 | PORT_SIZE = 0x40, |
82 | |
83 | /* registers for ATA TF operation */ |
84 | PORT_TF_DATA = 0x00, |
85 | PORT_TF_FEATURE = 0x01, |
86 | PORT_TF_NSECT = 0x02, |
87 | PORT_TF_LBAL = 0x03, |
88 | PORT_TF_LBAM = 0x04, |
89 | PORT_TF_LBAH = 0x05, |
90 | PORT_TF_DEVICE = 0x06, |
91 | PORT_TF_COMMAND = 0x07, |
92 | PORT_TF_ALT_STAT = 0x08, |
93 | PORT_IRQ_STAT = 0x09, |
94 | PORT_IRQ_MASK = 0x0a, |
95 | PORT_PRD_CTL = 0x0b, |
96 | PORT_PRD_ADDR = 0x0c, |
97 | PORT_PRD_XFERLEN = 0x10, |
98 | PORT_CPB_CPBLAR = 0x18, |
99 | PORT_CPB_PTQFIFO = 0x1c, |
100 | |
101 | /* IDMA register */ |
102 | PORT_IDMA_CTL = 0x14, |
103 | PORT_IDMA_STAT = 0x16, |
104 | |
105 | PORT_RPQ_FIFO = 0x1e, |
106 | PORT_RPQ_CNT = 0x1f, |
107 | |
108 | PORT_SCR = 0x20, |
109 | |
110 | /* HOST_CTL bits */ |
111 | HCTL_LEDEN = (1 << 3), /* enable LED operation */ |
112 | HCTL_IRQOFF = (1 << 8), /* global IRQ off */ |
113 | HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */ |
114 | HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/ |
115 | HCTL_PWRDWN = (1 << 12), /* power down PHYs */ |
116 | HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */ |
117 | HCTL_RPGSEL = (1 << 15), /* register page select */ |
118 | |
119 | HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST | |
120 | HCTL_RPGSEL, |
121 | |
122 | /* HOST_IRQ_(STAT|MASK) bits */ |
123 | HIRQ_PORT0 = (1 << 0), |
124 | HIRQ_PORT1 = (1 << 1), |
125 | HIRQ_SOFT = (1 << 14), |
126 | HIRQ_GLOBAL = (1 << 15), /* STAT only */ |
127 | |
128 | /* PORT_IRQ_(STAT|MASK) bits */ |
129 | PIRQ_OFFLINE = (1 << 0), /* device unplugged */ |
130 | PIRQ_ONLINE = (1 << 1), /* device plugged */ |
131 | PIRQ_COMPLETE = (1 << 2), /* completion interrupt */ |
132 | PIRQ_FATAL = (1 << 3), /* fatal error */ |
133 | PIRQ_ATA = (1 << 4), /* ATA interrupt */ |
134 | PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */ |
135 | PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */ |
136 | |
137 | PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL, |
138 | PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA, |
139 | PIRQ_MASK_FREEZE = 0xff, |
140 | |
141 | /* PORT_PRD_CTL bits */ |
142 | PRD_CTL_START = (1 << 0), |
143 | PRD_CTL_WR = (1 << 3), |
144 | PRD_CTL_DMAEN = (1 << 7), /* DMA enable */ |
145 | |
146 | /* PORT_IDMA_CTL bits */ |
147 | IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */ |
148 | IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinery */ |
149 | IDMA_CTL_GO = (1 << 7), /* IDMA mode go */ |
150 | IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */ |
151 | |
152 | /* PORT_IDMA_STAT bits */ |
153 | IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */ |
154 | IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */ |
155 | IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */ |
156 | IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */ |
157 | IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */ |
158 | IDMA_STAT_PSD = (1 << 6), /* ADMA pause */ |
159 | IDMA_STAT_DONE = (1 << 7), /* ADMA done */ |
160 | |
161 | IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR, |
162 | |
163 | /* CPB Control Flags*/ |
164 | CPB_CTL_VALID = (1 << 0), /* CPB valid */ |
165 | CPB_CTL_QUEUED = (1 << 1), /* queued command */ |
166 | CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */ |
167 | CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */ |
168 | CPB_CTL_DEVDIR = (1 << 4), /* device direction control */ |
169 | |
170 | /* CPB Response Flags */ |
171 | CPB_RESP_DONE = (1 << 0), /* ATA command complete */ |
172 | CPB_RESP_REL = (1 << 1), /* ATA release */ |
173 | CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */ |
174 | CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */ |
175 | CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */ |
176 | CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */ |
177 | CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */ |
178 | CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */ |
179 | |
180 | /* PRD Control Flags */ |
181 | PRD_DRAIN = (1 << 1), /* ignore data excess */ |
182 | PRD_CDB = (1 << 2), /* atapi packet command pointer */ |
183 | PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */ |
184 | PRD_DMA = (1 << 4), /* data transfer method */ |
185 | PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */ |
186 | PRD_IOM = (1 << 6), /* io/memory transfer */ |
187 | PRD_END = (1 << 7), /* APRD chain end */ |
188 | }; |
189 | |
190 | /* Comman Parameter Block */ |
191 | struct inic_cpb { |
192 | u8 resp_flags; /* Response Flags */ |
193 | u8 error; /* ATA Error */ |
194 | u8 status; /* ATA Status */ |
195 | u8 ctl_flags; /* Control Flags */ |
196 | __le32 len; /* Total Transfer Length */ |
197 | __le32 prd; /* First PRD pointer */ |
198 | u8 rsvd[4]; |
199 | /* 16 bytes */ |
200 | u8 feature; /* ATA Feature */ |
201 | u8 hob_feature; /* ATA Ex. Feature */ |
202 | u8 device; /* ATA Device/Head */ |
203 | u8 mirctl; /* Mirror Control */ |
204 | u8 nsect; /* ATA Sector Count */ |
205 | u8 hob_nsect; /* ATA Ex. Sector Count */ |
206 | u8 lbal; /* ATA Sector Number */ |
207 | u8 hob_lbal; /* ATA Ex. Sector Number */ |
208 | u8 lbam; /* ATA Cylinder Low */ |
209 | u8 hob_lbam; /* ATA Ex. Cylinder Low */ |
210 | u8 lbah; /* ATA Cylinder High */ |
211 | u8 hob_lbah; /* ATA Ex. Cylinder High */ |
212 | u8 command; /* ATA Command */ |
213 | u8 ctl; /* ATA Control */ |
214 | u8 slave_error; /* Slave ATA Error */ |
215 | u8 slave_status; /* Slave ATA Status */ |
216 | /* 32 bytes */ |
217 | } __packed; |
218 | |
219 | /* Physical Region Descriptor */ |
220 | struct inic_prd { |
221 | __le32 mad; /* Physical Memory Address */ |
222 | __le16 len; /* Transfer Length */ |
223 | u8 rsvd; |
224 | u8 flags; /* Control Flags */ |
225 | } __packed; |
226 | |
227 | struct inic_pkt { |
228 | struct inic_cpb cpb; |
229 | struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */ |
230 | u8 cdb[ATAPI_CDB_LEN]; |
231 | } __packed; |
232 | |
233 | struct inic_host_priv { |
234 | void __iomem *mmio_base; |
235 | u16 cached_hctl; |
236 | }; |
237 | |
238 | struct inic_port_priv { |
239 | struct inic_pkt *pkt; |
240 | dma_addr_t pkt_dma; |
241 | u32 *cpb_tbl; |
242 | dma_addr_t cpb_tbl_dma; |
243 | }; |
244 | |
245 | static const struct scsi_host_template inic_sht = { |
246 | ATA_BASE_SHT(DRV_NAME), |
247 | .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */ |
248 | |
249 | /* |
250 | * This controller is braindamaged. dma_boundary is 0xffff like others |
251 | * but it will lock up the whole machine HARD if 65536 byte PRD entry |
252 | * is fed. Reduce maximum segment size. |
253 | */ |
254 | .dma_boundary = INIC_DMA_BOUNDARY, |
255 | .max_segment_size = 65536 - 512, |
256 | }; |
257 | |
258 | static const int scr_map[] = { |
259 | [SCR_STATUS] = 0, |
260 | [SCR_ERROR] = 1, |
261 | [SCR_CONTROL] = 2, |
262 | }; |
263 | |
264 | static void __iomem *inic_port_base(struct ata_port *ap) |
265 | { |
266 | struct inic_host_priv *hpriv = ap->host->private_data; |
267 | |
268 | return hpriv->mmio_base + ap->port_no * PORT_SIZE; |
269 | } |
270 | |
271 | static void inic_reset_port(void __iomem *port_base) |
272 | { |
273 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; |
274 | |
275 | /* stop IDMA engine */ |
276 | readw(addr: idma_ctl); /* flush */ |
277 | msleep(msecs: 1); |
278 | |
279 | /* mask IRQ and assert reset */ |
280 | writew(val: IDMA_CTL_RST_IDMA, addr: idma_ctl); |
281 | readw(addr: idma_ctl); /* flush */ |
282 | msleep(msecs: 1); |
283 | |
284 | /* release reset */ |
285 | writew(val: 0, addr: idma_ctl); |
286 | |
287 | /* clear irq */ |
288 | writeb(val: 0xff, addr: port_base + PORT_IRQ_STAT); |
289 | } |
290 | |
291 | static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) |
292 | { |
293 | void __iomem *scr_addr = inic_port_base(ap: link->ap) + PORT_SCR; |
294 | |
295 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) |
296 | return -EINVAL; |
297 | |
298 | *val = readl(addr: scr_addr + scr_map[sc_reg] * 4); |
299 | |
300 | /* this controller has stuck DIAG.N, ignore it */ |
301 | if (sc_reg == SCR_ERROR) |
302 | *val &= ~SERR_PHYRDY_CHG; |
303 | return 0; |
304 | } |
305 | |
306 | static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) |
307 | { |
308 | void __iomem *scr_addr = inic_port_base(ap: link->ap) + PORT_SCR; |
309 | |
310 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) |
311 | return -EINVAL; |
312 | |
313 | writel(val, addr: scr_addr + scr_map[sc_reg] * 4); |
314 | return 0; |
315 | } |
316 | |
317 | static void inic_stop_idma(struct ata_port *ap) |
318 | { |
319 | void __iomem *port_base = inic_port_base(ap); |
320 | |
321 | readb(addr: port_base + PORT_RPQ_FIFO); |
322 | readb(addr: port_base + PORT_RPQ_CNT); |
323 | writew(val: 0, addr: port_base + PORT_IDMA_CTL); |
324 | } |
325 | |
326 | static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat) |
327 | { |
328 | struct ata_eh_info *ehi = &ap->link.eh_info; |
329 | struct inic_port_priv *pp = ap->private_data; |
330 | struct inic_cpb *cpb = &pp->pkt->cpb; |
331 | bool freeze = false; |
332 | |
333 | ata_ehi_clear_desc(ehi); |
334 | ata_ehi_push_desc(ehi, fmt: "irq_stat=0x%x idma_stat=0x%x" , |
335 | irq_stat, idma_stat); |
336 | |
337 | inic_stop_idma(ap); |
338 | |
339 | if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) { |
340 | ata_ehi_push_desc(ehi, fmt: "hotplug" ); |
341 | ata_ehi_hotplugged(ehi); |
342 | freeze = true; |
343 | } |
344 | |
345 | if (idma_stat & IDMA_STAT_PERR) { |
346 | ata_ehi_push_desc(ehi, fmt: "PCI error" ); |
347 | freeze = true; |
348 | } |
349 | |
350 | if (idma_stat & IDMA_STAT_CPBERR) { |
351 | ata_ehi_push_desc(ehi, fmt: "CPB error" ); |
352 | |
353 | if (cpb->resp_flags & CPB_RESP_IGNORED) { |
354 | __ata_ehi_push_desc(ehi, fmt: " ignored" ); |
355 | ehi->err_mask |= AC_ERR_INVALID; |
356 | freeze = true; |
357 | } |
358 | |
359 | if (cpb->resp_flags & CPB_RESP_ATA_ERR) |
360 | ehi->err_mask |= AC_ERR_DEV; |
361 | |
362 | if (cpb->resp_flags & CPB_RESP_SPURIOUS) { |
363 | __ata_ehi_push_desc(ehi, fmt: " spurious-intr" ); |
364 | ehi->err_mask |= AC_ERR_HSM; |
365 | freeze = true; |
366 | } |
367 | |
368 | if (cpb->resp_flags & |
369 | (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) { |
370 | __ata_ehi_push_desc(ehi, fmt: " data-over/underflow" ); |
371 | ehi->err_mask |= AC_ERR_HSM; |
372 | freeze = true; |
373 | } |
374 | } |
375 | |
376 | if (freeze) |
377 | ata_port_freeze(ap); |
378 | else |
379 | ata_port_abort(ap); |
380 | } |
381 | |
382 | static void inic_host_intr(struct ata_port *ap) |
383 | { |
384 | void __iomem *port_base = inic_port_base(ap); |
385 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag: ap->link.active_tag); |
386 | u8 irq_stat; |
387 | u16 idma_stat; |
388 | |
389 | /* read and clear IRQ status */ |
390 | irq_stat = readb(addr: port_base + PORT_IRQ_STAT); |
391 | writeb(val: irq_stat, addr: port_base + PORT_IRQ_STAT); |
392 | idma_stat = readw(addr: port_base + PORT_IDMA_STAT); |
393 | |
394 | if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR))) |
395 | inic_host_err_intr(ap, irq_stat, idma_stat); |
396 | |
397 | if (unlikely(!qc)) |
398 | goto spurious; |
399 | |
400 | if (likely(idma_stat & IDMA_STAT_DONE)) { |
401 | inic_stop_idma(ap); |
402 | |
403 | /* Depending on circumstances, device error |
404 | * isn't reported by IDMA, check it explicitly. |
405 | */ |
406 | if (unlikely(readb(port_base + PORT_TF_COMMAND) & |
407 | (ATA_DF | ATA_ERR))) |
408 | qc->err_mask |= AC_ERR_DEV; |
409 | |
410 | ata_qc_complete(qc); |
411 | return; |
412 | } |
413 | |
414 | spurious: |
415 | ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n" , |
416 | qc ? qc->tf.command : 0xff, irq_stat, idma_stat); |
417 | } |
418 | |
419 | static irqreturn_t inic_interrupt(int irq, void *dev_instance) |
420 | { |
421 | struct ata_host *host = dev_instance; |
422 | struct inic_host_priv *hpriv = host->private_data; |
423 | u16 host_irq_stat; |
424 | int i, handled = 0; |
425 | |
426 | host_irq_stat = readw(addr: hpriv->mmio_base + HOST_IRQ_STAT); |
427 | |
428 | if (unlikely(!(host_irq_stat & HIRQ_GLOBAL))) |
429 | goto out; |
430 | |
431 | spin_lock(lock: &host->lock); |
432 | |
433 | for (i = 0; i < NR_PORTS; i++) |
434 | if (host_irq_stat & (HIRQ_PORT0 << i)) { |
435 | inic_host_intr(ap: host->ports[i]); |
436 | handled++; |
437 | } |
438 | |
439 | spin_unlock(lock: &host->lock); |
440 | |
441 | out: |
442 | return IRQ_RETVAL(handled); |
443 | } |
444 | |
445 | static int inic_check_atapi_dma(struct ata_queued_cmd *qc) |
446 | { |
447 | /* For some reason ATAPI_PROT_DMA doesn't work for some |
448 | * commands including writes and other misc ops. Use PIO |
449 | * protocol instead, which BTW is driven by the DMA engine |
450 | * anyway, so it shouldn't make much difference for native |
451 | * SATA devices. |
452 | */ |
453 | if (atapi_cmd_type(opcode: qc->cdb[0]) == READ) |
454 | return 0; |
455 | return 1; |
456 | } |
457 | |
458 | static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc) |
459 | { |
460 | struct scatterlist *sg; |
461 | unsigned int si; |
462 | u8 flags = 0; |
463 | |
464 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
465 | flags |= PRD_WRITE; |
466 | |
467 | if (ata_is_dma(prot: qc->tf.protocol)) |
468 | flags |= PRD_DMA; |
469 | |
470 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
471 | prd->mad = cpu_to_le32(sg_dma_address(sg)); |
472 | prd->len = cpu_to_le16(sg_dma_len(sg)); |
473 | prd->flags = flags; |
474 | prd++; |
475 | } |
476 | |
477 | WARN_ON(!si); |
478 | prd[-1].flags |= PRD_END; |
479 | } |
480 | |
481 | static enum ata_completion_errors inic_qc_prep(struct ata_queued_cmd *qc) |
482 | { |
483 | struct inic_port_priv *pp = qc->ap->private_data; |
484 | struct inic_pkt *pkt = pp->pkt; |
485 | struct inic_cpb *cpb = &pkt->cpb; |
486 | struct inic_prd *prd = pkt->prd; |
487 | bool is_atapi = ata_is_atapi(prot: qc->tf.protocol); |
488 | bool is_data = ata_is_data(prot: qc->tf.protocol); |
489 | unsigned int cdb_len = 0; |
490 | |
491 | if (is_atapi) |
492 | cdb_len = qc->dev->cdb_len; |
493 | |
494 | /* prepare packet, based on initio driver */ |
495 | memset(pkt, 0, sizeof(struct inic_pkt)); |
496 | |
497 | cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN; |
498 | if (is_atapi || is_data) |
499 | cpb->ctl_flags |= CPB_CTL_DATA; |
500 | |
501 | cpb->len = cpu_to_le32(qc->nbytes + cdb_len); |
502 | cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd)); |
503 | |
504 | cpb->device = qc->tf.device; |
505 | cpb->feature = qc->tf.feature; |
506 | cpb->nsect = qc->tf.nsect; |
507 | cpb->lbal = qc->tf.lbal; |
508 | cpb->lbam = qc->tf.lbam; |
509 | cpb->lbah = qc->tf.lbah; |
510 | |
511 | if (qc->tf.flags & ATA_TFLAG_LBA48) { |
512 | cpb->hob_feature = qc->tf.hob_feature; |
513 | cpb->hob_nsect = qc->tf.hob_nsect; |
514 | cpb->hob_lbal = qc->tf.hob_lbal; |
515 | cpb->hob_lbam = qc->tf.hob_lbam; |
516 | cpb->hob_lbah = qc->tf.hob_lbah; |
517 | } |
518 | |
519 | cpb->command = qc->tf.command; |
520 | /* don't load ctl - dunno why. it's like that in the initio driver */ |
521 | |
522 | /* setup PRD for CDB */ |
523 | if (is_atapi) { |
524 | memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN); |
525 | prd->mad = cpu_to_le32(pp->pkt_dma + |
526 | offsetof(struct inic_pkt, cdb)); |
527 | prd->len = cpu_to_le16(cdb_len); |
528 | prd->flags = PRD_CDB | PRD_WRITE; |
529 | if (!is_data) |
530 | prd->flags |= PRD_END; |
531 | prd++; |
532 | } |
533 | |
534 | /* setup sg table */ |
535 | if (is_data) |
536 | inic_fill_sg(prd, qc); |
537 | |
538 | pp->cpb_tbl[0] = pp->pkt_dma; |
539 | |
540 | return AC_ERR_OK; |
541 | } |
542 | |
543 | static unsigned int inic_qc_issue(struct ata_queued_cmd *qc) |
544 | { |
545 | struct ata_port *ap = qc->ap; |
546 | void __iomem *port_base = inic_port_base(ap); |
547 | |
548 | /* fire up the ADMA engine */ |
549 | writew(val: HCTL_FTHD0 | HCTL_LEDEN, addr: port_base + HOST_CTL); |
550 | writew(val: IDMA_CTL_GO, addr: port_base + PORT_IDMA_CTL); |
551 | writeb(val: 0, addr: port_base + PORT_CPB_PTQFIFO); |
552 | |
553 | return 0; |
554 | } |
555 | |
556 | static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
557 | { |
558 | void __iomem *port_base = inic_port_base(ap); |
559 | |
560 | tf->error = readb(addr: port_base + PORT_TF_FEATURE); |
561 | tf->nsect = readb(addr: port_base + PORT_TF_NSECT); |
562 | tf->lbal = readb(addr: port_base + PORT_TF_LBAL); |
563 | tf->lbam = readb(addr: port_base + PORT_TF_LBAM); |
564 | tf->lbah = readb(addr: port_base + PORT_TF_LBAH); |
565 | tf->device = readb(addr: port_base + PORT_TF_DEVICE); |
566 | tf->status = readb(addr: port_base + PORT_TF_COMMAND); |
567 | } |
568 | |
569 | static void inic_qc_fill_rtf(struct ata_queued_cmd *qc) |
570 | { |
571 | struct ata_taskfile *rtf = &qc->result_tf; |
572 | struct ata_taskfile tf; |
573 | |
574 | /* FIXME: Except for status and error, result TF access |
575 | * doesn't work. I tried reading from BAR0/2, CPB and BAR5. |
576 | * None works regardless of which command interface is used. |
577 | * For now return true iff status indicates device error. |
578 | * This means that we're reporting bogus sector for RW |
579 | * failures. Eeekk.... |
580 | */ |
581 | inic_tf_read(ap: qc->ap, tf: &tf); |
582 | |
583 | if (tf.status & ATA_ERR) { |
584 | rtf->status = tf.status; |
585 | rtf->error = tf.error; |
586 | } |
587 | } |
588 | |
589 | static void inic_freeze(struct ata_port *ap) |
590 | { |
591 | void __iomem *port_base = inic_port_base(ap); |
592 | |
593 | writeb(val: PIRQ_MASK_FREEZE, addr: port_base + PORT_IRQ_MASK); |
594 | writeb(val: 0xff, addr: port_base + PORT_IRQ_STAT); |
595 | } |
596 | |
597 | static void inic_thaw(struct ata_port *ap) |
598 | { |
599 | void __iomem *port_base = inic_port_base(ap); |
600 | |
601 | writeb(val: 0xff, addr: port_base + PORT_IRQ_STAT); |
602 | writeb(val: PIRQ_MASK_DEFAULT, addr: port_base + PORT_IRQ_MASK); |
603 | } |
604 | |
605 | static int inic_check_ready(struct ata_link *link) |
606 | { |
607 | void __iomem *port_base = inic_port_base(ap: link->ap); |
608 | |
609 | return ata_check_ready(readb(addr: port_base + PORT_TF_COMMAND)); |
610 | } |
611 | |
612 | /* |
613 | * SRST and SControl hardreset don't give valid signature on this |
614 | * controller. Only controller specific hardreset mechanism works. |
615 | */ |
616 | static int inic_hardreset(struct ata_link *link, unsigned int *class, |
617 | unsigned long deadline) |
618 | { |
619 | struct ata_port *ap = link->ap; |
620 | void __iomem *port_base = inic_port_base(ap); |
621 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; |
622 | const unsigned int *timing = sata_ehc_deb_timing(ehc: &link->eh_context); |
623 | int rc; |
624 | |
625 | /* hammer it into sane state */ |
626 | inic_reset_port(port_base); |
627 | |
628 | writew(val: IDMA_CTL_RST_ATA, addr: idma_ctl); |
629 | readw(addr: idma_ctl); /* flush */ |
630 | ata_msleep(ap, msecs: 1); |
631 | writew(val: 0, addr: idma_ctl); |
632 | |
633 | rc = sata_link_resume(link, params: timing, deadline); |
634 | if (rc) { |
635 | ata_link_warn(link, |
636 | "failed to resume link after reset (errno=%d)\n" , |
637 | rc); |
638 | return rc; |
639 | } |
640 | |
641 | *class = ATA_DEV_NONE; |
642 | if (ata_link_online(link)) { |
643 | struct ata_taskfile tf; |
644 | |
645 | /* wait for link to become ready */ |
646 | rc = ata_wait_after_reset(link, deadline, check_ready: inic_check_ready); |
647 | /* link occupied, -ENODEV too is an error */ |
648 | if (rc) { |
649 | ata_link_warn(link, |
650 | "device not ready after hardreset (errno=%d)\n" , |
651 | rc); |
652 | return rc; |
653 | } |
654 | |
655 | inic_tf_read(ap, tf: &tf); |
656 | *class = ata_port_classify(ap, tf: &tf); |
657 | } |
658 | |
659 | return 0; |
660 | } |
661 | |
662 | static void inic_error_handler(struct ata_port *ap) |
663 | { |
664 | void __iomem *port_base = inic_port_base(ap); |
665 | |
666 | inic_reset_port(port_base); |
667 | ata_std_error_handler(ap); |
668 | } |
669 | |
670 | static void inic_post_internal_cmd(struct ata_queued_cmd *qc) |
671 | { |
672 | /* make DMA engine forget about the failed command */ |
673 | if (qc->flags & ATA_QCFLAG_EH) |
674 | inic_reset_port(port_base: inic_port_base(ap: qc->ap)); |
675 | } |
676 | |
677 | static void init_port(struct ata_port *ap) |
678 | { |
679 | void __iomem *port_base = inic_port_base(ap); |
680 | struct inic_port_priv *pp = ap->private_data; |
681 | |
682 | /* clear packet and CPB table */ |
683 | memset(pp->pkt, 0, sizeof(struct inic_pkt)); |
684 | memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE); |
685 | |
686 | /* setup CPB lookup table addresses */ |
687 | writel(val: pp->cpb_tbl_dma, addr: port_base + PORT_CPB_CPBLAR); |
688 | } |
689 | |
690 | static int inic_port_resume(struct ata_port *ap) |
691 | { |
692 | init_port(ap); |
693 | return 0; |
694 | } |
695 | |
696 | static int inic_port_start(struct ata_port *ap) |
697 | { |
698 | struct device *dev = ap->host->dev; |
699 | struct inic_port_priv *pp; |
700 | |
701 | /* alloc and initialize private data */ |
702 | pp = devm_kzalloc(dev, size: sizeof(*pp), GFP_KERNEL); |
703 | if (!pp) |
704 | return -ENOMEM; |
705 | ap->private_data = pp; |
706 | |
707 | /* Alloc resources */ |
708 | pp->pkt = dmam_alloc_coherent(dev, size: sizeof(struct inic_pkt), |
709 | dma_handle: &pp->pkt_dma, GFP_KERNEL); |
710 | if (!pp->pkt) |
711 | return -ENOMEM; |
712 | |
713 | pp->cpb_tbl = dmam_alloc_coherent(dev, size: IDMA_CPB_TBL_SIZE, |
714 | dma_handle: &pp->cpb_tbl_dma, GFP_KERNEL); |
715 | if (!pp->cpb_tbl) |
716 | return -ENOMEM; |
717 | |
718 | init_port(ap); |
719 | |
720 | return 0; |
721 | } |
722 | |
723 | static struct ata_port_operations inic_port_ops = { |
724 | .inherits = &sata_port_ops, |
725 | |
726 | .check_atapi_dma = inic_check_atapi_dma, |
727 | .qc_prep = inic_qc_prep, |
728 | .qc_issue = inic_qc_issue, |
729 | .qc_fill_rtf = inic_qc_fill_rtf, |
730 | |
731 | .freeze = inic_freeze, |
732 | .thaw = inic_thaw, |
733 | .hardreset = inic_hardreset, |
734 | .error_handler = inic_error_handler, |
735 | .post_internal_cmd = inic_post_internal_cmd, |
736 | |
737 | .scr_read = inic_scr_read, |
738 | .scr_write = inic_scr_write, |
739 | |
740 | .port_resume = inic_port_resume, |
741 | .port_start = inic_port_start, |
742 | }; |
743 | |
744 | static const struct ata_port_info inic_port_info = { |
745 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, |
746 | .pio_mask = ATA_PIO4, |
747 | .mwdma_mask = ATA_MWDMA2, |
748 | .udma_mask = ATA_UDMA6, |
749 | .port_ops = &inic_port_ops |
750 | }; |
751 | |
752 | static int init_controller(void __iomem *mmio_base, u16 hctl) |
753 | { |
754 | int i; |
755 | u16 val; |
756 | |
757 | hctl &= ~HCTL_KNOWN_BITS; |
758 | |
759 | /* Soft reset whole controller. Spec says reset duration is 3 |
760 | * PCI clocks, be generous and give it 10ms. |
761 | */ |
762 | writew(val: hctl | HCTL_SOFTRST, addr: mmio_base + HOST_CTL); |
763 | readw(addr: mmio_base + HOST_CTL); /* flush */ |
764 | |
765 | for (i = 0; i < 10; i++) { |
766 | msleep(msecs: 1); |
767 | val = readw(addr: mmio_base + HOST_CTL); |
768 | if (!(val & HCTL_SOFTRST)) |
769 | break; |
770 | } |
771 | |
772 | if (val & HCTL_SOFTRST) |
773 | return -EIO; |
774 | |
775 | /* mask all interrupts and reset ports */ |
776 | for (i = 0; i < NR_PORTS; i++) { |
777 | void __iomem *port_base = mmio_base + i * PORT_SIZE; |
778 | |
779 | writeb(val: 0xff, addr: port_base + PORT_IRQ_MASK); |
780 | inic_reset_port(port_base); |
781 | } |
782 | |
783 | /* port IRQ is masked now, unmask global IRQ */ |
784 | writew(val: hctl & ~HCTL_IRQOFF, addr: mmio_base + HOST_CTL); |
785 | val = readw(addr: mmio_base + HOST_IRQ_MASK); |
786 | val &= ~(HIRQ_PORT0 | HIRQ_PORT1); |
787 | writew(val, addr: mmio_base + HOST_IRQ_MASK); |
788 | |
789 | return 0; |
790 | } |
791 | |
792 | #ifdef CONFIG_PM_SLEEP |
793 | static int inic_pci_device_resume(struct pci_dev *pdev) |
794 | { |
795 | struct ata_host *host = pci_get_drvdata(pdev); |
796 | struct inic_host_priv *hpriv = host->private_data; |
797 | int rc; |
798 | |
799 | rc = ata_pci_device_do_resume(pdev); |
800 | if (rc) |
801 | return rc; |
802 | |
803 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
804 | rc = init_controller(mmio_base: hpriv->mmio_base, hctl: hpriv->cached_hctl); |
805 | if (rc) |
806 | return rc; |
807 | } |
808 | |
809 | ata_host_resume(host); |
810 | |
811 | return 0; |
812 | } |
813 | #endif |
814 | |
815 | static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
816 | { |
817 | const struct ata_port_info *ppi[] = { &inic_port_info, NULL }; |
818 | struct ata_host *host; |
819 | struct inic_host_priv *hpriv; |
820 | void __iomem * const *iomap; |
821 | int mmio_bar; |
822 | int i, rc; |
823 | |
824 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
825 | |
826 | dev_alert(&pdev->dev, "inic162x support is broken with common data corruption issues and will be disabled by default, contact linux-ide@vger.kernel.org if in production use\n" ); |
827 | |
828 | /* alloc host */ |
829 | host = ata_host_alloc_pinfo(dev: &pdev->dev, ppi, n_ports: NR_PORTS); |
830 | hpriv = devm_kzalloc(dev: &pdev->dev, size: sizeof(*hpriv), GFP_KERNEL); |
831 | if (!host || !hpriv) |
832 | return -ENOMEM; |
833 | |
834 | host->private_data = hpriv; |
835 | |
836 | /* Acquire resources and fill host. Note that PCI and cardbus |
837 | * use different BARs. |
838 | */ |
839 | rc = pcim_enable_device(pdev); |
840 | if (rc) |
841 | return rc; |
842 | |
843 | if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM) |
844 | mmio_bar = MMIO_BAR_PCI; |
845 | else |
846 | mmio_bar = MMIO_BAR_CARDBUS; |
847 | |
848 | rc = pcim_iomap_regions(pdev, mask: 1 << mmio_bar, DRV_NAME); |
849 | if (rc) |
850 | return rc; |
851 | host->iomap = iomap = pcim_iomap_table(pdev); |
852 | hpriv->mmio_base = iomap[mmio_bar]; |
853 | hpriv->cached_hctl = readw(addr: hpriv->mmio_base + HOST_CTL); |
854 | |
855 | for (i = 0; i < NR_PORTS; i++) { |
856 | struct ata_port *ap = host->ports[i]; |
857 | |
858 | ata_port_pbar_desc(ap, bar: mmio_bar, offset: -1, name: "mmio" ); |
859 | ata_port_pbar_desc(ap, bar: mmio_bar, offset: i * PORT_SIZE, name: "port" ); |
860 | } |
861 | |
862 | /* Set dma_mask. This devices doesn't support 64bit addressing. */ |
863 | rc = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(32)); |
864 | if (rc) { |
865 | dev_err(&pdev->dev, "32-bit DMA enable failed\n" ); |
866 | return rc; |
867 | } |
868 | |
869 | rc = init_controller(mmio_base: hpriv->mmio_base, hctl: hpriv->cached_hctl); |
870 | if (rc) { |
871 | dev_err(&pdev->dev, "failed to initialize controller\n" ); |
872 | return rc; |
873 | } |
874 | |
875 | pci_set_master(dev: pdev); |
876 | return ata_host_activate(host, irq: pdev->irq, irq_handler: inic_interrupt, IRQF_SHARED, |
877 | sht: &inic_sht); |
878 | } |
879 | |
880 | static const struct pci_device_id inic_pci_tbl[] = { |
881 | { PCI_VDEVICE(INIT, 0x1622), }, |
882 | { }, |
883 | }; |
884 | |
885 | static struct pci_driver inic_pci_driver = { |
886 | .name = DRV_NAME, |
887 | .id_table = inic_pci_tbl, |
888 | #ifdef CONFIG_PM_SLEEP |
889 | .suspend = ata_pci_device_suspend, |
890 | .resume = inic_pci_device_resume, |
891 | #endif |
892 | .probe = inic_init_one, |
893 | .remove = ata_pci_remove_one, |
894 | }; |
895 | |
896 | module_pci_driver(inic_pci_driver); |
897 | |
898 | MODULE_AUTHOR("Tejun Heo" ); |
899 | MODULE_DESCRIPTION("low-level driver for Initio 162x SATA" ); |
900 | MODULE_LICENSE("GPL v2" ); |
901 | MODULE_DEVICE_TABLE(pci, inic_pci_tbl); |
902 | MODULE_VERSION(DRV_VERSION); |
903 | |