1/*
2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
3 *
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
6 *
7 * This file is released under GPL v2.
8 *
9 * **** WARNING ****
10 *
11 * This driver never worked properly and unfortunately data corruption is
12 * relatively common. There isn't anyone working on the driver and there's
13 * no support from the vendor. Do not use this driver in any production
14 * environment.
15 *
16 * http://thread.gmane.org/gmane.linux.debian.devel.bugs.rc/378525/focus=54491
17 * https://bugzilla.kernel.org/show_bug.cgi?id=60565
18 *
19 * *****************
20 *
21 * This controller is eccentric and easily locks up if something isn't
22 * right. Documentation is available at initio's website but it only
23 * documents registers (not programming model).
24 *
25 * This driver has interesting history. The first version was written
26 * from the documentation and a 2.4 IDE driver posted on a Taiwan
27 * company, which didn't use any IDMA features and couldn't handle
28 * LBA48. The resulting driver couldn't handle LBA48 devices either
29 * making it pretty useless.
30 *
31 * After a while, initio picked the driver up, renamed it to
32 * sata_initio162x, updated it to use IDMA for ATA DMA commands and
33 * posted it on their website. It only used ATA_PROT_DMA for IDMA and
34 * attaching both devices and issuing IDMA and !IDMA commands
35 * simultaneously broke it due to PIRQ masking interaction but it did
36 * show how to use the IDMA (ADMA + some initio specific twists)
37 * engine.
38 *
39 * Then, I picked up their changes again and here's the usable driver
40 * which uses IDMA for everything. Everything works now including
41 * LBA48, CD/DVD burning, suspend/resume and hotplug. There are some
42 * issues tho. Result Tf is not resported properly, NCQ isn't
43 * supported yet and CD/DVD writing works with DMA assisted PIO
44 * protocol (which, for native SATA devices, shouldn't cause any
45 * noticeable difference).
46 *
47 * Anyways, so, here's finally a working driver for inic162x. Enjoy!
48 *
49 * initio: If you guys wanna improve the driver regarding result TF
50 * access and other stuff, please feel free to contact me. I'll be
51 * happy to assist.
52 */
53
54#include <linux/gfp.h>
55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <scsi/scsi_host.h>
59#include <linux/libata.h>
60#include <linux/blkdev.h>
61#include <scsi/scsi_device.h>
62
63#define DRV_NAME "sata_inic162x"
64#define DRV_VERSION "0.4"
65
66enum {
67 MMIO_BAR_PCI = 5,
68 MMIO_BAR_CARDBUS = 1,
69
70 NR_PORTS = 2,
71
72 IDMA_CPB_TBL_SIZE = 4 * 32,
73
74 INIC_DMA_BOUNDARY = 0xffffff,
75
76 HOST_ACTRL = 0x08,
77 HOST_CTL = 0x7c,
78 HOST_STAT = 0x7e,
79 HOST_IRQ_STAT = 0xbc,
80 HOST_IRQ_MASK = 0xbe,
81
82 PORT_SIZE = 0x40,
83
84 /* registers for ATA TF operation */
85 PORT_TF_DATA = 0x00,
86 PORT_TF_FEATURE = 0x01,
87 PORT_TF_NSECT = 0x02,
88 PORT_TF_LBAL = 0x03,
89 PORT_TF_LBAM = 0x04,
90 PORT_TF_LBAH = 0x05,
91 PORT_TF_DEVICE = 0x06,
92 PORT_TF_COMMAND = 0x07,
93 PORT_TF_ALT_STAT = 0x08,
94 PORT_IRQ_STAT = 0x09,
95 PORT_IRQ_MASK = 0x0a,
96 PORT_PRD_CTL = 0x0b,
97 PORT_PRD_ADDR = 0x0c,
98 PORT_PRD_XFERLEN = 0x10,
99 PORT_CPB_CPBLAR = 0x18,
100 PORT_CPB_PTQFIFO = 0x1c,
101
102 /* IDMA register */
103 PORT_IDMA_CTL = 0x14,
104 PORT_IDMA_STAT = 0x16,
105
106 PORT_RPQ_FIFO = 0x1e,
107 PORT_RPQ_CNT = 0x1f,
108
109 PORT_SCR = 0x20,
110
111 /* HOST_CTL bits */
112 HCTL_LEDEN = (1 << 3), /* enable LED operation */
113 HCTL_IRQOFF = (1 << 8), /* global IRQ off */
114 HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
115 HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
116 HCTL_PWRDWN = (1 << 12), /* power down PHYs */
117 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
118 HCTL_RPGSEL = (1 << 15), /* register page select */
119
120 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
121 HCTL_RPGSEL,
122
123 /* HOST_IRQ_(STAT|MASK) bits */
124 HIRQ_PORT0 = (1 << 0),
125 HIRQ_PORT1 = (1 << 1),
126 HIRQ_SOFT = (1 << 14),
127 HIRQ_GLOBAL = (1 << 15), /* STAT only */
128
129 /* PORT_IRQ_(STAT|MASK) bits */
130 PIRQ_OFFLINE = (1 << 0), /* device unplugged */
131 PIRQ_ONLINE = (1 << 1), /* device plugged */
132 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
133 PIRQ_FATAL = (1 << 3), /* fatal error */
134 PIRQ_ATA = (1 << 4), /* ATA interrupt */
135 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
136 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
137
138 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
139 PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA,
140 PIRQ_MASK_FREEZE = 0xff,
141
142 /* PORT_PRD_CTL bits */
143 PRD_CTL_START = (1 << 0),
144 PRD_CTL_WR = (1 << 3),
145 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
146
147 /* PORT_IDMA_CTL bits */
148 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
149 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
150 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
151 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
152
153 /* PORT_IDMA_STAT bits */
154 IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */
155 IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */
156 IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */
157 IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */
158 IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */
159 IDMA_STAT_PSD = (1 << 6), /* ADMA pause */
160 IDMA_STAT_DONE = (1 << 7), /* ADMA done */
161
162 IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
163
164 /* CPB Control Flags*/
165 CPB_CTL_VALID = (1 << 0), /* CPB valid */
166 CPB_CTL_QUEUED = (1 << 1), /* queued command */
167 CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */
168 CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */
169 CPB_CTL_DEVDIR = (1 << 4), /* device direction control */
170
171 /* CPB Response Flags */
172 CPB_RESP_DONE = (1 << 0), /* ATA command complete */
173 CPB_RESP_REL = (1 << 1), /* ATA release */
174 CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */
175 CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */
176 CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */
177 CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */
178 CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */
179 CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */
180
181 /* PRD Control Flags */
182 PRD_DRAIN = (1 << 1), /* ignore data excess */
183 PRD_CDB = (1 << 2), /* atapi packet command pointer */
184 PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */
185 PRD_DMA = (1 << 4), /* data transfer method */
186 PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */
187 PRD_IOM = (1 << 6), /* io/memory transfer */
188 PRD_END = (1 << 7), /* APRD chain end */
189};
190
191/* Comman Parameter Block */
192struct inic_cpb {
193 u8 resp_flags; /* Response Flags */
194 u8 error; /* ATA Error */
195 u8 status; /* ATA Status */
196 u8 ctl_flags; /* Control Flags */
197 __le32 len; /* Total Transfer Length */
198 __le32 prd; /* First PRD pointer */
199 u8 rsvd[4];
200 /* 16 bytes */
201 u8 feature; /* ATA Feature */
202 u8 hob_feature; /* ATA Ex. Feature */
203 u8 device; /* ATA Device/Head */
204 u8 mirctl; /* Mirror Control */
205 u8 nsect; /* ATA Sector Count */
206 u8 hob_nsect; /* ATA Ex. Sector Count */
207 u8 lbal; /* ATA Sector Number */
208 u8 hob_lbal; /* ATA Ex. Sector Number */
209 u8 lbam; /* ATA Cylinder Low */
210 u8 hob_lbam; /* ATA Ex. Cylinder Low */
211 u8 lbah; /* ATA Cylinder High */
212 u8 hob_lbah; /* ATA Ex. Cylinder High */
213 u8 command; /* ATA Command */
214 u8 ctl; /* ATA Control */
215 u8 slave_error; /* Slave ATA Error */
216 u8 slave_status; /* Slave ATA Status */
217 /* 32 bytes */
218} __packed;
219
220/* Physical Region Descriptor */
221struct inic_prd {
222 __le32 mad; /* Physical Memory Address */
223 __le16 len; /* Transfer Length */
224 u8 rsvd;
225 u8 flags; /* Control Flags */
226} __packed;
227
228struct inic_pkt {
229 struct inic_cpb cpb;
230 struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
231 u8 cdb[ATAPI_CDB_LEN];
232} __packed;
233
234struct inic_host_priv {
235 void __iomem *mmio_base;
236 u16 cached_hctl;
237};
238
239struct inic_port_priv {
240 struct inic_pkt *pkt;
241 dma_addr_t pkt_dma;
242 u32 *cpb_tbl;
243 dma_addr_t cpb_tbl_dma;
244};
245
246static struct scsi_host_template inic_sht = {
247 ATA_BASE_SHT(DRV_NAME),
248 .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */
249
250 /*
251 * This controller is braindamaged. dma_boundary is 0xffff like others
252 * but it will lock up the whole machine HARD if 65536 byte PRD entry
253 * is fed. Reduce maximum segment size.
254 */
255 .dma_boundary = INIC_DMA_BOUNDARY,
256 .max_segment_size = 65536 - 512,
257};
258
259static const int scr_map[] = {
260 [SCR_STATUS] = 0,
261 [SCR_ERROR] = 1,
262 [SCR_CONTROL] = 2,
263};
264
265static void __iomem *inic_port_base(struct ata_port *ap)
266{
267 struct inic_host_priv *hpriv = ap->host->private_data;
268
269 return hpriv->mmio_base + ap->port_no * PORT_SIZE;
270}
271
272static void inic_reset_port(void __iomem *port_base)
273{
274 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
275
276 /* stop IDMA engine */
277 readw(idma_ctl); /* flush */
278 msleep(1);
279
280 /* mask IRQ and assert reset */
281 writew(IDMA_CTL_RST_IDMA, idma_ctl);
282 readw(idma_ctl); /* flush */
283 msleep(1);
284
285 /* release reset */
286 writew(0, idma_ctl);
287
288 /* clear irq */
289 writeb(0xff, port_base + PORT_IRQ_STAT);
290}
291
292static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
293{
294 void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
295
296 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
297 return -EINVAL;
298
299 *val = readl(scr_addr + scr_map[sc_reg] * 4);
300
301 /* this controller has stuck DIAG.N, ignore it */
302 if (sc_reg == SCR_ERROR)
303 *val &= ~SERR_PHYRDY_CHG;
304 return 0;
305}
306
307static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
308{
309 void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
310
311 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
312 return -EINVAL;
313
314 writel(val, scr_addr + scr_map[sc_reg] * 4);
315 return 0;
316}
317
318static void inic_stop_idma(struct ata_port *ap)
319{
320 void __iomem *port_base = inic_port_base(ap);
321
322 readb(port_base + PORT_RPQ_FIFO);
323 readb(port_base + PORT_RPQ_CNT);
324 writew(0, port_base + PORT_IDMA_CTL);
325}
326
327static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
328{
329 struct ata_eh_info *ehi = &ap->link.eh_info;
330 struct inic_port_priv *pp = ap->private_data;
331 struct inic_cpb *cpb = &pp->pkt->cpb;
332 bool freeze = false;
333
334 ata_ehi_clear_desc(ehi);
335 ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
336 irq_stat, idma_stat);
337
338 inic_stop_idma(ap);
339
340 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
341 ata_ehi_push_desc(ehi, "hotplug");
342 ata_ehi_hotplugged(ehi);
343 freeze = true;
344 }
345
346 if (idma_stat & IDMA_STAT_PERR) {
347 ata_ehi_push_desc(ehi, "PCI error");
348 freeze = true;
349 }
350
351 if (idma_stat & IDMA_STAT_CPBERR) {
352 ata_ehi_push_desc(ehi, "CPB error");
353
354 if (cpb->resp_flags & CPB_RESP_IGNORED) {
355 __ata_ehi_push_desc(ehi, " ignored");
356 ehi->err_mask |= AC_ERR_INVALID;
357 freeze = true;
358 }
359
360 if (cpb->resp_flags & CPB_RESP_ATA_ERR)
361 ehi->err_mask |= AC_ERR_DEV;
362
363 if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
364 __ata_ehi_push_desc(ehi, " spurious-intr");
365 ehi->err_mask |= AC_ERR_HSM;
366 freeze = true;
367 }
368
369 if (cpb->resp_flags &
370 (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
371 __ata_ehi_push_desc(ehi, " data-over/underflow");
372 ehi->err_mask |= AC_ERR_HSM;
373 freeze = true;
374 }
375 }
376
377 if (freeze)
378 ata_port_freeze(ap);
379 else
380 ata_port_abort(ap);
381}
382
383static void inic_host_intr(struct ata_port *ap)
384{
385 void __iomem *port_base = inic_port_base(ap);
386 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
387 u8 irq_stat;
388 u16 idma_stat;
389
390 /* read and clear IRQ status */
391 irq_stat = readb(port_base + PORT_IRQ_STAT);
392 writeb(irq_stat, port_base + PORT_IRQ_STAT);
393 idma_stat = readw(port_base + PORT_IDMA_STAT);
394
395 if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
396 inic_host_err_intr(ap, irq_stat, idma_stat);
397
398 if (unlikely(!qc))
399 goto spurious;
400
401 if (likely(idma_stat & IDMA_STAT_DONE)) {
402 inic_stop_idma(ap);
403
404 /* Depending on circumstances, device error
405 * isn't reported by IDMA, check it explicitly.
406 */
407 if (unlikely(readb(port_base + PORT_TF_COMMAND) &
408 (ATA_DF | ATA_ERR)))
409 qc->err_mask |= AC_ERR_DEV;
410
411 ata_qc_complete(qc);
412 return;
413 }
414
415 spurious:
416 ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
417 qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
418}
419
420static irqreturn_t inic_interrupt(int irq, void *dev_instance)
421{
422 struct ata_host *host = dev_instance;
423 struct inic_host_priv *hpriv = host->private_data;
424 u16 host_irq_stat;
425 int i, handled = 0;
426
427 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
428
429 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
430 goto out;
431
432 spin_lock(&host->lock);
433
434 for (i = 0; i < NR_PORTS; i++)
435 if (host_irq_stat & (HIRQ_PORT0 << i)) {
436 inic_host_intr(host->ports[i]);
437 handled++;
438 }
439
440 spin_unlock(&host->lock);
441
442 out:
443 return IRQ_RETVAL(handled);
444}
445
446static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
447{
448 /* For some reason ATAPI_PROT_DMA doesn't work for some
449 * commands including writes and other misc ops. Use PIO
450 * protocol instead, which BTW is driven by the DMA engine
451 * anyway, so it shouldn't make much difference for native
452 * SATA devices.
453 */
454 if (atapi_cmd_type(qc->cdb[0]) == READ)
455 return 0;
456 return 1;
457}
458
459static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
460{
461 struct scatterlist *sg;
462 unsigned int si;
463 u8 flags = 0;
464
465 if (qc->tf.flags & ATA_TFLAG_WRITE)
466 flags |= PRD_WRITE;
467
468 if (ata_is_dma(qc->tf.protocol))
469 flags |= PRD_DMA;
470
471 for_each_sg(qc->sg, sg, qc->n_elem, si) {
472 prd->mad = cpu_to_le32(sg_dma_address(sg));
473 prd->len = cpu_to_le16(sg_dma_len(sg));
474 prd->flags = flags;
475 prd++;
476 }
477
478 WARN_ON(!si);
479 prd[-1].flags |= PRD_END;
480}
481
482static void inic_qc_prep(struct ata_queued_cmd *qc)
483{
484 struct inic_port_priv *pp = qc->ap->private_data;
485 struct inic_pkt *pkt = pp->pkt;
486 struct inic_cpb *cpb = &pkt->cpb;
487 struct inic_prd *prd = pkt->prd;
488 bool is_atapi = ata_is_atapi(qc->tf.protocol);
489 bool is_data = ata_is_data(qc->tf.protocol);
490 unsigned int cdb_len = 0;
491
492 VPRINTK("ENTER\n");
493
494 if (is_atapi)
495 cdb_len = qc->dev->cdb_len;
496
497 /* prepare packet, based on initio driver */
498 memset(pkt, 0, sizeof(struct inic_pkt));
499
500 cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
501 if (is_atapi || is_data)
502 cpb->ctl_flags |= CPB_CTL_DATA;
503
504 cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
505 cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
506
507 cpb->device = qc->tf.device;
508 cpb->feature = qc->tf.feature;
509 cpb->nsect = qc->tf.nsect;
510 cpb->lbal = qc->tf.lbal;
511 cpb->lbam = qc->tf.lbam;
512 cpb->lbah = qc->tf.lbah;
513
514 if (qc->tf.flags & ATA_TFLAG_LBA48) {
515 cpb->hob_feature = qc->tf.hob_feature;
516 cpb->hob_nsect = qc->tf.hob_nsect;
517 cpb->hob_lbal = qc->tf.hob_lbal;
518 cpb->hob_lbam = qc->tf.hob_lbam;
519 cpb->hob_lbah = qc->tf.hob_lbah;
520 }
521
522 cpb->command = qc->tf.command;
523 /* don't load ctl - dunno why. it's like that in the initio driver */
524
525 /* setup PRD for CDB */
526 if (is_atapi) {
527 memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
528 prd->mad = cpu_to_le32(pp->pkt_dma +
529 offsetof(struct inic_pkt, cdb));
530 prd->len = cpu_to_le16(cdb_len);
531 prd->flags = PRD_CDB | PRD_WRITE;
532 if (!is_data)
533 prd->flags |= PRD_END;
534 prd++;
535 }
536
537 /* setup sg table */
538 if (is_data)
539 inic_fill_sg(prd, qc);
540
541 pp->cpb_tbl[0] = pp->pkt_dma;
542}
543
544static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
545{
546 struct ata_port *ap = qc->ap;
547 void __iomem *port_base = inic_port_base(ap);
548
549 /* fire up the ADMA engine */
550 writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL);
551 writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
552 writeb(0, port_base + PORT_CPB_PTQFIFO);
553
554 return 0;
555}
556
557static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
558{
559 void __iomem *port_base = inic_port_base(ap);
560
561 tf->feature = readb(port_base + PORT_TF_FEATURE);
562 tf->nsect = readb(port_base + PORT_TF_NSECT);
563 tf->lbal = readb(port_base + PORT_TF_LBAL);
564 tf->lbam = readb(port_base + PORT_TF_LBAM);
565 tf->lbah = readb(port_base + PORT_TF_LBAH);
566 tf->device = readb(port_base + PORT_TF_DEVICE);
567 tf->command = readb(port_base + PORT_TF_COMMAND);
568}
569
570static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
571{
572 struct ata_taskfile *rtf = &qc->result_tf;
573 struct ata_taskfile tf;
574
575 /* FIXME: Except for status and error, result TF access
576 * doesn't work. I tried reading from BAR0/2, CPB and BAR5.
577 * None works regardless of which command interface is used.
578 * For now return true iff status indicates device error.
579 * This means that we're reporting bogus sector for RW
580 * failures. Eeekk....
581 */
582 inic_tf_read(qc->ap, &tf);
583
584 if (!(tf.command & ATA_ERR))
585 return false;
586
587 rtf->command = tf.command;
588 rtf->feature = tf.feature;
589 return true;
590}
591
592static void inic_freeze(struct ata_port *ap)
593{
594 void __iomem *port_base = inic_port_base(ap);
595
596 writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
597 writeb(0xff, port_base + PORT_IRQ_STAT);
598}
599
600static void inic_thaw(struct ata_port *ap)
601{
602 void __iomem *port_base = inic_port_base(ap);
603
604 writeb(0xff, port_base + PORT_IRQ_STAT);
605 writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
606}
607
608static int inic_check_ready(struct ata_link *link)
609{
610 void __iomem *port_base = inic_port_base(link->ap);
611
612 return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
613}
614
615/*
616 * SRST and SControl hardreset don't give valid signature on this
617 * controller. Only controller specific hardreset mechanism works.
618 */
619static int inic_hardreset(struct ata_link *link, unsigned int *class,
620 unsigned long deadline)
621{
622 struct ata_port *ap = link->ap;
623 void __iomem *port_base = inic_port_base(ap);
624 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
625 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
626 int rc;
627
628 /* hammer it into sane state */
629 inic_reset_port(port_base);
630
631 writew(IDMA_CTL_RST_ATA, idma_ctl);
632 readw(idma_ctl); /* flush */
633 ata_msleep(ap, 1);
634 writew(0, idma_ctl);
635
636 rc = sata_link_resume(link, timing, deadline);
637 if (rc) {
638 ata_link_warn(link,
639 "failed to resume link after reset (errno=%d)\n",
640 rc);
641 return rc;
642 }
643
644 *class = ATA_DEV_NONE;
645 if (ata_link_online(link)) {
646 struct ata_taskfile tf;
647
648 /* wait for link to become ready */
649 rc = ata_wait_after_reset(link, deadline, inic_check_ready);
650 /* link occupied, -ENODEV too is an error */
651 if (rc) {
652 ata_link_warn(link,
653 "device not ready after hardreset (errno=%d)\n",
654 rc);
655 return rc;
656 }
657
658 inic_tf_read(ap, &tf);
659 *class = ata_dev_classify(&tf);
660 }
661
662 return 0;
663}
664
665static void inic_error_handler(struct ata_port *ap)
666{
667 void __iomem *port_base = inic_port_base(ap);
668
669 inic_reset_port(port_base);
670 ata_std_error_handler(ap);
671}
672
673static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
674{
675 /* make DMA engine forget about the failed command */
676 if (qc->flags & ATA_QCFLAG_FAILED)
677 inic_reset_port(inic_port_base(qc->ap));
678}
679
680static void init_port(struct ata_port *ap)
681{
682 void __iomem *port_base = inic_port_base(ap);
683 struct inic_port_priv *pp = ap->private_data;
684
685 /* clear packet and CPB table */
686 memset(pp->pkt, 0, sizeof(struct inic_pkt));
687 memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
688
689 /* setup CPB lookup table addresses */
690 writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
691}
692
693static int inic_port_resume(struct ata_port *ap)
694{
695 init_port(ap);
696 return 0;
697}
698
699static int inic_port_start(struct ata_port *ap)
700{
701 struct device *dev = ap->host->dev;
702 struct inic_port_priv *pp;
703
704 /* alloc and initialize private data */
705 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
706 if (!pp)
707 return -ENOMEM;
708 ap->private_data = pp;
709
710 /* Alloc resources */
711 pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
712 &pp->pkt_dma, GFP_KERNEL);
713 if (!pp->pkt)
714 return -ENOMEM;
715
716 pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
717 &pp->cpb_tbl_dma, GFP_KERNEL);
718 if (!pp->cpb_tbl)
719 return -ENOMEM;
720
721 init_port(ap);
722
723 return 0;
724}
725
726static struct ata_port_operations inic_port_ops = {
727 .inherits = &sata_port_ops,
728
729 .check_atapi_dma = inic_check_atapi_dma,
730 .qc_prep = inic_qc_prep,
731 .qc_issue = inic_qc_issue,
732 .qc_fill_rtf = inic_qc_fill_rtf,
733
734 .freeze = inic_freeze,
735 .thaw = inic_thaw,
736 .hardreset = inic_hardreset,
737 .error_handler = inic_error_handler,
738 .post_internal_cmd = inic_post_internal_cmd,
739
740 .scr_read = inic_scr_read,
741 .scr_write = inic_scr_write,
742
743 .port_resume = inic_port_resume,
744 .port_start = inic_port_start,
745};
746
747static const struct ata_port_info inic_port_info = {
748 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
749 .pio_mask = ATA_PIO4,
750 .mwdma_mask = ATA_MWDMA2,
751 .udma_mask = ATA_UDMA6,
752 .port_ops = &inic_port_ops
753};
754
755static int init_controller(void __iomem *mmio_base, u16 hctl)
756{
757 int i;
758 u16 val;
759
760 hctl &= ~HCTL_KNOWN_BITS;
761
762 /* Soft reset whole controller. Spec says reset duration is 3
763 * PCI clocks, be generous and give it 10ms.
764 */
765 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
766 readw(mmio_base + HOST_CTL); /* flush */
767
768 for (i = 0; i < 10; i++) {
769 msleep(1);
770 val = readw(mmio_base + HOST_CTL);
771 if (!(val & HCTL_SOFTRST))
772 break;
773 }
774
775 if (val & HCTL_SOFTRST)
776 return -EIO;
777
778 /* mask all interrupts and reset ports */
779 for (i = 0; i < NR_PORTS; i++) {
780 void __iomem *port_base = mmio_base + i * PORT_SIZE;
781
782 writeb(0xff, port_base + PORT_IRQ_MASK);
783 inic_reset_port(port_base);
784 }
785
786 /* port IRQ is masked now, unmask global IRQ */
787 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
788 val = readw(mmio_base + HOST_IRQ_MASK);
789 val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
790 writew(val, mmio_base + HOST_IRQ_MASK);
791
792 return 0;
793}
794
795#ifdef CONFIG_PM_SLEEP
796static int inic_pci_device_resume(struct pci_dev *pdev)
797{
798 struct ata_host *host = pci_get_drvdata(pdev);
799 struct inic_host_priv *hpriv = host->private_data;
800 int rc;
801
802 rc = ata_pci_device_do_resume(pdev);
803 if (rc)
804 return rc;
805
806 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
807 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
808 if (rc)
809 return rc;
810 }
811
812 ata_host_resume(host);
813
814 return 0;
815}
816#endif
817
818static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
819{
820 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
821 struct ata_host *host;
822 struct inic_host_priv *hpriv;
823 void __iomem * const *iomap;
824 int mmio_bar;
825 int i, rc;
826
827 ata_print_version_once(&pdev->dev, DRV_VERSION);
828
829 dev_alert(&pdev->dev, "inic162x support is broken with common data corruption issues and will be disabled by default, contact linux-ide@vger.kernel.org if in production use\n");
830
831 /* alloc host */
832 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
833 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
834 if (!host || !hpriv)
835 return -ENOMEM;
836
837 host->private_data = hpriv;
838
839 /* Acquire resources and fill host. Note that PCI and cardbus
840 * use different BARs.
841 */
842 rc = pcim_enable_device(pdev);
843 if (rc)
844 return rc;
845
846 if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
847 mmio_bar = MMIO_BAR_PCI;
848 else
849 mmio_bar = MMIO_BAR_CARDBUS;
850
851 rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
852 if (rc)
853 return rc;
854 host->iomap = iomap = pcim_iomap_table(pdev);
855 hpriv->mmio_base = iomap[mmio_bar];
856 hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
857
858 for (i = 0; i < NR_PORTS; i++) {
859 struct ata_port *ap = host->ports[i];
860
861 ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
862 ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
863 }
864
865 /* Set dma_mask. This devices doesn't support 64bit addressing. */
866 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
867 if (rc) {
868 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
869 return rc;
870 }
871
872 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
873 if (rc) {
874 dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
875 return rc;
876 }
877
878 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
879 if (rc) {
880 dev_err(&pdev->dev, "failed to initialize controller\n");
881 return rc;
882 }
883
884 pci_set_master(pdev);
885 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
886 &inic_sht);
887}
888
889static const struct pci_device_id inic_pci_tbl[] = {
890 { PCI_VDEVICE(INIT, 0x1622), },
891 { },
892};
893
894static struct pci_driver inic_pci_driver = {
895 .name = DRV_NAME,
896 .id_table = inic_pci_tbl,
897#ifdef CONFIG_PM_SLEEP
898 .suspend = ata_pci_device_suspend,
899 .resume = inic_pci_device_resume,
900#endif
901 .probe = inic_init_one,
902 .remove = ata_pci_remove_one,
903};
904
905module_pci_driver(inic_pci_driver);
906
907MODULE_AUTHOR("Tejun Heo");
908MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
909MODULE_LICENSE("GPL v2");
910MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
911MODULE_VERSION(DRV_VERSION);
912