1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Renesas R-Car SATA driver |
4 | * |
5 | * Author: Vladimir Barinov <source@cogentembedded.com> |
6 | * Copyright (C) 2013-2015 Cogent Embedded, Inc. |
7 | * Copyright (C) 2013-2015 Renesas Solutions Corp. |
8 | */ |
9 | |
10 | #include <linux/kernel.h> |
11 | #include <linux/module.h> |
12 | #include <linux/ata.h> |
13 | #include <linux/libata.h> |
14 | #include <linux/of.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/pm_runtime.h> |
17 | #include <linux/err.h> |
18 | |
19 | #define DRV_NAME "sata_rcar" |
20 | |
21 | /* SH-Navi2G/ATAPI module compatible control registers */ |
22 | #define ATAPI_CONTROL1_REG 0x180 |
23 | #define ATAPI_STATUS_REG 0x184 |
24 | #define ATAPI_INT_ENABLE_REG 0x188 |
25 | #define ATAPI_DTB_ADR_REG 0x198 |
26 | #define ATAPI_DMA_START_ADR_REG 0x19C |
27 | #define ATAPI_DMA_TRANS_CNT_REG 0x1A0 |
28 | #define ATAPI_CONTROL2_REG 0x1A4 |
29 | #define ATAPI_SIG_ST_REG 0x1B0 |
30 | #define ATAPI_BYTE_SWAP_REG 0x1BC |
31 | |
32 | /* ATAPI control 1 register (ATAPI_CONTROL1) bits */ |
33 | #define ATAPI_CONTROL1_ISM BIT(16) |
34 | #define ATAPI_CONTROL1_DTA32M BIT(11) |
35 | #define ATAPI_CONTROL1_RESET BIT(7) |
36 | #define ATAPI_CONTROL1_DESE BIT(3) |
37 | #define ATAPI_CONTROL1_RW BIT(2) |
38 | #define ATAPI_CONTROL1_STOP BIT(1) |
39 | #define ATAPI_CONTROL1_START BIT(0) |
40 | |
41 | /* ATAPI status register (ATAPI_STATUS) bits */ |
42 | #define ATAPI_STATUS_SATAINT BIT(11) |
43 | #define ATAPI_STATUS_DNEND BIT(6) |
44 | #define ATAPI_STATUS_DEVTRM BIT(5) |
45 | #define ATAPI_STATUS_DEVINT BIT(4) |
46 | #define ATAPI_STATUS_ERR BIT(2) |
47 | #define ATAPI_STATUS_NEND BIT(1) |
48 | #define ATAPI_STATUS_ACT BIT(0) |
49 | |
50 | /* Interrupt enable register (ATAPI_INT_ENABLE) bits */ |
51 | #define ATAPI_INT_ENABLE_SATAINT BIT(11) |
52 | #define ATAPI_INT_ENABLE_DNEND BIT(6) |
53 | #define ATAPI_INT_ENABLE_DEVTRM BIT(5) |
54 | #define ATAPI_INT_ENABLE_DEVINT BIT(4) |
55 | #define ATAPI_INT_ENABLE_ERR BIT(2) |
56 | #define ATAPI_INT_ENABLE_NEND BIT(1) |
57 | #define ATAPI_INT_ENABLE_ACT BIT(0) |
58 | |
59 | /* Access control registers for physical layer control register */ |
60 | #define SATAPHYADDR_REG 0x200 |
61 | #define SATAPHYWDATA_REG 0x204 |
62 | #define SATAPHYACCEN_REG 0x208 |
63 | #define SATAPHYRESET_REG 0x20C |
64 | #define SATAPHYRDATA_REG 0x210 |
65 | #define SATAPHYACK_REG 0x214 |
66 | |
67 | /* Physical layer control address command register (SATAPHYADDR) bits */ |
68 | #define SATAPHYADDR_PHYRATEMODE BIT(10) |
69 | #define SATAPHYADDR_PHYCMD_READ BIT(9) |
70 | #define SATAPHYADDR_PHYCMD_WRITE BIT(8) |
71 | |
72 | /* Physical layer control enable register (SATAPHYACCEN) bits */ |
73 | #define SATAPHYACCEN_PHYLANE BIT(0) |
74 | |
75 | /* Physical layer control reset register (SATAPHYRESET) bits */ |
76 | #define SATAPHYRESET_PHYRST BIT(1) |
77 | #define SATAPHYRESET_PHYSRES BIT(0) |
78 | |
79 | /* Physical layer control acknowledge register (SATAPHYACK) bits */ |
80 | #define SATAPHYACK_PHYACK BIT(0) |
81 | |
82 | /* Serial-ATA HOST control registers */ |
83 | #define BISTCONF_REG 0x102C |
84 | #define SDATA_REG 0x1100 |
85 | #define SSDEVCON_REG 0x1204 |
86 | |
87 | #define 0x1400 |
88 | #define SCRSERR_REG 0x1404 |
89 | #define SCRSCON_REG 0x1408 |
90 | #define SCRSACT_REG 0x140C |
91 | |
92 | #define SATAINTSTAT_REG 0x1508 |
93 | #define SATAINTMASK_REG 0x150C |
94 | |
95 | /* SATA INT status register (SATAINTSTAT) bits */ |
96 | #define SATAINTSTAT_SERR BIT(3) |
97 | #define SATAINTSTAT_ATA BIT(0) |
98 | |
99 | /* SATA INT mask register (SATAINTSTAT) bits */ |
100 | #define SATAINTMASK_SERRMSK BIT(3) |
101 | #define SATAINTMASK_ERRMSK BIT(2) |
102 | #define SATAINTMASK_ERRCRTMSK BIT(1) |
103 | #define SATAINTMASK_ATAMSK BIT(0) |
104 | #define SATAINTMASK_ALL_GEN1 0x7ff |
105 | #define SATAINTMASK_ALL_GEN2 0xfff |
106 | |
107 | #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \ |
108 | SATAINTMASK_ATAMSK) |
109 | |
110 | /* Physical Layer Control Registers */ |
111 | #define SATAPCTLR1_REG 0x43 |
112 | #define SATAPCTLR2_REG 0x52 |
113 | #define SATAPCTLR3_REG 0x5A |
114 | #define SATAPCTLR4_REG 0x60 |
115 | |
116 | /* Descriptor table word 0 bit (when DTA32M = 1) */ |
117 | #define SATA_RCAR_DTEND BIT(0) |
118 | |
119 | #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFFUL |
120 | |
121 | /* Gen2 Physical Layer Control Registers */ |
122 | #define RCAR_GEN2_PHY_CTL1_REG 0x1704 |
123 | #define RCAR_GEN2_PHY_CTL1 0x34180002 |
124 | #define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */ |
125 | |
126 | #define RCAR_GEN2_PHY_CTL2_REG 0x170C |
127 | #define RCAR_GEN2_PHY_CTL2 0x00002303 |
128 | |
129 | #define RCAR_GEN2_PHY_CTL3_REG 0x171C |
130 | #define RCAR_GEN2_PHY_CTL3 0x000B0194 |
131 | |
132 | #define RCAR_GEN2_PHY_CTL4_REG 0x1724 |
133 | #define RCAR_GEN2_PHY_CTL4 0x00030994 |
134 | |
135 | #define RCAR_GEN2_PHY_CTL5_REG 0x1740 |
136 | #define RCAR_GEN2_PHY_CTL5 0x03004001 |
137 | #define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */ |
138 | #define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */ |
139 | |
140 | enum sata_rcar_type { |
141 | RCAR_GEN1_SATA, |
142 | RCAR_GEN2_SATA, |
143 | RCAR_GEN3_SATA, |
144 | RCAR_R8A7790_ES1_SATA, |
145 | }; |
146 | |
147 | struct sata_rcar_priv { |
148 | void __iomem *base; |
149 | u32 sataint_mask; |
150 | enum sata_rcar_type type; |
151 | }; |
152 | |
153 | static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv) |
154 | { |
155 | void __iomem *base = priv->base; |
156 | |
157 | /* idle state */ |
158 | iowrite32(0, base + SATAPHYADDR_REG); |
159 | /* reset */ |
160 | iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); |
161 | udelay(10); |
162 | /* deassert reset */ |
163 | iowrite32(0, base + SATAPHYRESET_REG); |
164 | } |
165 | |
166 | static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg, |
167 | u32 val, int group) |
168 | { |
169 | void __iomem *base = priv->base; |
170 | int timeout; |
171 | |
172 | /* deassert reset */ |
173 | iowrite32(0, base + SATAPHYRESET_REG); |
174 | /* lane 1 */ |
175 | iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); |
176 | /* write phy register value */ |
177 | iowrite32(val, base + SATAPHYWDATA_REG); |
178 | /* set register group */ |
179 | if (group) |
180 | reg |= SATAPHYADDR_PHYRATEMODE; |
181 | /* write command */ |
182 | iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); |
183 | /* wait for ack */ |
184 | for (timeout = 0; timeout < 100; timeout++) { |
185 | val = ioread32(base + SATAPHYACK_REG); |
186 | if (val & SATAPHYACK_PHYACK) |
187 | break; |
188 | } |
189 | if (timeout >= 100) |
190 | pr_err("%s timeout\n" , __func__); |
191 | /* idle state */ |
192 | iowrite32(0, base + SATAPHYADDR_REG); |
193 | } |
194 | |
195 | static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv) |
196 | { |
197 | sata_rcar_gen1_phy_preinit(priv); |
198 | sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, val: 0x00200188, group: 0); |
199 | sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, val: 0x00200188, group: 1); |
200 | sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, val: 0x0000A061, group: 0); |
201 | sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, val: 0x20000000, group: 0); |
202 | sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, val: 0x20000000, group: 1); |
203 | sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, val: 0x28E80000, group: 0); |
204 | } |
205 | |
206 | static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv) |
207 | { |
208 | void __iomem *base = priv->base; |
209 | |
210 | iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG); |
211 | iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG); |
212 | iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG); |
213 | iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG); |
214 | iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC | |
215 | RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG); |
216 | } |
217 | |
218 | static void sata_rcar_freeze(struct ata_port *ap) |
219 | { |
220 | struct sata_rcar_priv *priv = ap->host->private_data; |
221 | |
222 | /* mask */ |
223 | iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG); |
224 | |
225 | ata_sff_freeze(ap); |
226 | } |
227 | |
228 | static void sata_rcar_thaw(struct ata_port *ap) |
229 | { |
230 | struct sata_rcar_priv *priv = ap->host->private_data; |
231 | void __iomem *base = priv->base; |
232 | |
233 | /* ack */ |
234 | iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); |
235 | |
236 | ata_sff_thaw(ap); |
237 | |
238 | /* unmask */ |
239 | iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); |
240 | } |
241 | |
242 | static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) |
243 | { |
244 | u16 *ptr = buffer; |
245 | |
246 | while (count--) { |
247 | u16 data = ioread32(reg); |
248 | |
249 | *ptr++ = data; |
250 | } |
251 | } |
252 | |
253 | static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count) |
254 | { |
255 | const u16 *ptr = buffer; |
256 | |
257 | while (count--) |
258 | iowrite32(*ptr++, reg); |
259 | } |
260 | |
261 | static u8 sata_rcar_check_status(struct ata_port *ap) |
262 | { |
263 | return ioread32(ap->ioaddr.status_addr); |
264 | } |
265 | |
266 | static u8 sata_rcar_check_altstatus(struct ata_port *ap) |
267 | { |
268 | return ioread32(ap->ioaddr.altstatus_addr); |
269 | } |
270 | |
271 | static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl) |
272 | { |
273 | iowrite32(ctl, ap->ioaddr.ctl_addr); |
274 | } |
275 | |
276 | static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device) |
277 | { |
278 | iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr); |
279 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
280 | } |
281 | |
282 | static bool sata_rcar_ata_devchk(struct ata_port *ap, unsigned int device) |
283 | { |
284 | struct ata_ioports *ioaddr = &ap->ioaddr; |
285 | u8 nsect, lbal; |
286 | |
287 | sata_rcar_dev_select(ap, device); |
288 | |
289 | iowrite32(0x55, ioaddr->nsect_addr); |
290 | iowrite32(0xaa, ioaddr->lbal_addr); |
291 | |
292 | iowrite32(0xaa, ioaddr->nsect_addr); |
293 | iowrite32(0x55, ioaddr->lbal_addr); |
294 | |
295 | iowrite32(0x55, ioaddr->nsect_addr); |
296 | iowrite32(0xaa, ioaddr->lbal_addr); |
297 | |
298 | nsect = ioread32(ioaddr->nsect_addr); |
299 | lbal = ioread32(ioaddr->lbal_addr); |
300 | |
301 | if (nsect == 0x55 && lbal == 0xaa) |
302 | return true; /* found a device */ |
303 | |
304 | return false; /* nothing found */ |
305 | } |
306 | |
307 | static int sata_rcar_wait_after_reset(struct ata_link *link, |
308 | unsigned long deadline) |
309 | { |
310 | struct ata_port *ap = link->ap; |
311 | |
312 | ata_msleep(ap, msecs: ATA_WAIT_AFTER_RESET); |
313 | |
314 | return ata_sff_wait_ready(link, deadline); |
315 | } |
316 | |
317 | static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline) |
318 | { |
319 | struct ata_ioports *ioaddr = &ap->ioaddr; |
320 | |
321 | /* software reset. causes dev0 to be selected */ |
322 | iowrite32(ap->ctl, ioaddr->ctl_addr); |
323 | udelay(20); |
324 | iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr); |
325 | udelay(20); |
326 | iowrite32(ap->ctl, ioaddr->ctl_addr); |
327 | ap->last_ctl = ap->ctl; |
328 | |
329 | /* wait the port to become ready */ |
330 | return sata_rcar_wait_after_reset(link: &ap->link, deadline); |
331 | } |
332 | |
333 | static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes, |
334 | unsigned long deadline) |
335 | { |
336 | struct ata_port *ap = link->ap; |
337 | unsigned int devmask = 0; |
338 | int rc; |
339 | u8 err; |
340 | |
341 | /* determine if device 0 is present */ |
342 | if (sata_rcar_ata_devchk(ap, device: 0)) |
343 | devmask |= 1 << 0; |
344 | |
345 | /* issue bus reset */ |
346 | rc = sata_rcar_bus_softreset(ap, deadline); |
347 | /* if link is occupied, -ENODEV too is an error */ |
348 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { |
349 | ata_link_err(link, "SRST failed (errno=%d)\n" , rc); |
350 | return rc; |
351 | } |
352 | |
353 | /* determine by signature whether we have ATA or ATAPI devices */ |
354 | classes[0] = ata_sff_dev_classify(dev: &link->device[0], present: devmask, r_err: &err); |
355 | |
356 | return 0; |
357 | } |
358 | |
359 | static void sata_rcar_tf_load(struct ata_port *ap, |
360 | const struct ata_taskfile *tf) |
361 | { |
362 | struct ata_ioports *ioaddr = &ap->ioaddr; |
363 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; |
364 | |
365 | if (tf->ctl != ap->last_ctl) { |
366 | iowrite32(tf->ctl, ioaddr->ctl_addr); |
367 | ap->last_ctl = tf->ctl; |
368 | ata_wait_idle(ap); |
369 | } |
370 | |
371 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
372 | iowrite32(tf->hob_feature, ioaddr->feature_addr); |
373 | iowrite32(tf->hob_nsect, ioaddr->nsect_addr); |
374 | iowrite32(tf->hob_lbal, ioaddr->lbal_addr); |
375 | iowrite32(tf->hob_lbam, ioaddr->lbam_addr); |
376 | iowrite32(tf->hob_lbah, ioaddr->lbah_addr); |
377 | } |
378 | |
379 | if (is_addr) { |
380 | iowrite32(tf->feature, ioaddr->feature_addr); |
381 | iowrite32(tf->nsect, ioaddr->nsect_addr); |
382 | iowrite32(tf->lbal, ioaddr->lbal_addr); |
383 | iowrite32(tf->lbam, ioaddr->lbam_addr); |
384 | iowrite32(tf->lbah, ioaddr->lbah_addr); |
385 | } |
386 | |
387 | if (tf->flags & ATA_TFLAG_DEVICE) |
388 | iowrite32(tf->device, ioaddr->device_addr); |
389 | |
390 | ata_wait_idle(ap); |
391 | } |
392 | |
393 | static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
394 | { |
395 | struct ata_ioports *ioaddr = &ap->ioaddr; |
396 | |
397 | tf->status = sata_rcar_check_status(ap); |
398 | tf->error = ioread32(ioaddr->error_addr); |
399 | tf->nsect = ioread32(ioaddr->nsect_addr); |
400 | tf->lbal = ioread32(ioaddr->lbal_addr); |
401 | tf->lbam = ioread32(ioaddr->lbam_addr); |
402 | tf->lbah = ioread32(ioaddr->lbah_addr); |
403 | tf->device = ioread32(ioaddr->device_addr); |
404 | |
405 | if (tf->flags & ATA_TFLAG_LBA48) { |
406 | iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr); |
407 | tf->hob_feature = ioread32(ioaddr->error_addr); |
408 | tf->hob_nsect = ioread32(ioaddr->nsect_addr); |
409 | tf->hob_lbal = ioread32(ioaddr->lbal_addr); |
410 | tf->hob_lbam = ioread32(ioaddr->lbam_addr); |
411 | tf->hob_lbah = ioread32(ioaddr->lbah_addr); |
412 | iowrite32(tf->ctl, ioaddr->ctl_addr); |
413 | ap->last_ctl = tf->ctl; |
414 | } |
415 | } |
416 | |
417 | static void sata_rcar_exec_command(struct ata_port *ap, |
418 | const struct ata_taskfile *tf) |
419 | { |
420 | iowrite32(tf->command, ap->ioaddr.command_addr); |
421 | ata_sff_pause(ap); |
422 | } |
423 | |
424 | static unsigned int sata_rcar_data_xfer(struct ata_queued_cmd *qc, |
425 | unsigned char *buf, |
426 | unsigned int buflen, int rw) |
427 | { |
428 | struct ata_port *ap = qc->dev->link->ap; |
429 | void __iomem *data_addr = ap->ioaddr.data_addr; |
430 | unsigned int words = buflen >> 1; |
431 | |
432 | /* Transfer multiple of 2 bytes */ |
433 | if (rw == READ) |
434 | sata_rcar_ioread16_rep(reg: data_addr, buffer: buf, count: words); |
435 | else |
436 | sata_rcar_iowrite16_rep(reg: data_addr, buffer: buf, count: words); |
437 | |
438 | /* Transfer trailing byte, if any. */ |
439 | if (unlikely(buflen & 0x01)) { |
440 | unsigned char pad[2] = { }; |
441 | |
442 | /* Point buf to the tail of buffer */ |
443 | buf += buflen - 1; |
444 | |
445 | /* |
446 | * Use io*16_rep() accessors here as well to avoid pointlessly |
447 | * swapping bytes to and from on the big endian machines... |
448 | */ |
449 | if (rw == READ) { |
450 | sata_rcar_ioread16_rep(reg: data_addr, buffer: pad, count: 1); |
451 | *buf = pad[0]; |
452 | } else { |
453 | pad[0] = *buf; |
454 | sata_rcar_iowrite16_rep(reg: data_addr, buffer: pad, count: 1); |
455 | } |
456 | words++; |
457 | } |
458 | |
459 | return words << 1; |
460 | } |
461 | |
462 | static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc) |
463 | { |
464 | int count; |
465 | struct ata_port *ap; |
466 | |
467 | /* We only need to flush incoming data when a command was running */ |
468 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) |
469 | return; |
470 | |
471 | ap = qc->ap; |
472 | /* Drain up to 64K of data before we give up this recovery method */ |
473 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) && |
474 | count < 65536; count += 2) |
475 | ioread32(ap->ioaddr.data_addr); |
476 | |
477 | if (count) |
478 | ata_port_dbg(ap, "drained %d bytes to clear DRQ\n" , count); |
479 | } |
480 | |
481 | static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg, |
482 | u32 *val) |
483 | { |
484 | if (sc_reg > SCR_ACTIVE) |
485 | return -EINVAL; |
486 | |
487 | *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2)); |
488 | return 0; |
489 | } |
490 | |
491 | static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg, |
492 | u32 val) |
493 | { |
494 | if (sc_reg > SCR_ACTIVE) |
495 | return -EINVAL; |
496 | |
497 | iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2)); |
498 | return 0; |
499 | } |
500 | |
501 | static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) |
502 | { |
503 | struct ata_port *ap = qc->ap; |
504 | struct ata_bmdma_prd *prd = ap->bmdma_prd; |
505 | struct scatterlist *sg; |
506 | unsigned int si; |
507 | |
508 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
509 | u32 addr, sg_len; |
510 | |
511 | /* |
512 | * Note: h/w doesn't support 64-bit, so we unconditionally |
513 | * truncate dma_addr_t to u32. |
514 | */ |
515 | addr = (u32)sg_dma_address(sg); |
516 | sg_len = sg_dma_len(sg); |
517 | |
518 | prd[si].addr = cpu_to_le32(addr); |
519 | prd[si].flags_len = cpu_to_le32(sg_len); |
520 | } |
521 | |
522 | /* end-of-table flag */ |
523 | prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); |
524 | } |
525 | |
526 | static enum ata_completion_errors sata_rcar_qc_prep(struct ata_queued_cmd *qc) |
527 | { |
528 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
529 | return AC_ERR_OK; |
530 | |
531 | sata_rcar_bmdma_fill_sg(qc); |
532 | |
533 | return AC_ERR_OK; |
534 | } |
535 | |
536 | static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) |
537 | { |
538 | struct ata_port *ap = qc->ap; |
539 | unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; |
540 | struct sata_rcar_priv *priv = ap->host->private_data; |
541 | void __iomem *base = priv->base; |
542 | u32 dmactl; |
543 | |
544 | /* load PRD table addr. */ |
545 | mb(); /* make sure PRD table writes are visible to controller */ |
546 | iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); |
547 | |
548 | /* specify data direction, triple-check start bit is clear */ |
549 | dmactl = ioread32(base + ATAPI_CONTROL1_REG); |
550 | dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); |
551 | if (dmactl & ATAPI_CONTROL1_START) { |
552 | dmactl &= ~ATAPI_CONTROL1_START; |
553 | dmactl |= ATAPI_CONTROL1_STOP; |
554 | } |
555 | if (!rw) |
556 | dmactl |= ATAPI_CONTROL1_RW; |
557 | iowrite32(dmactl, base + ATAPI_CONTROL1_REG); |
558 | |
559 | /* issue r/w command */ |
560 | ap->ops->sff_exec_command(ap, &qc->tf); |
561 | } |
562 | |
563 | static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) |
564 | { |
565 | struct ata_port *ap = qc->ap; |
566 | struct sata_rcar_priv *priv = ap->host->private_data; |
567 | void __iomem *base = priv->base; |
568 | u32 dmactl; |
569 | |
570 | /* start host DMA transaction */ |
571 | dmactl = ioread32(base + ATAPI_CONTROL1_REG); |
572 | dmactl &= ~ATAPI_CONTROL1_STOP; |
573 | dmactl |= ATAPI_CONTROL1_START; |
574 | iowrite32(dmactl, base + ATAPI_CONTROL1_REG); |
575 | } |
576 | |
577 | static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) |
578 | { |
579 | struct ata_port *ap = qc->ap; |
580 | struct sata_rcar_priv *priv = ap->host->private_data; |
581 | void __iomem *base = priv->base; |
582 | u32 dmactl; |
583 | |
584 | /* force termination of DMA transfer if active */ |
585 | dmactl = ioread32(base + ATAPI_CONTROL1_REG); |
586 | if (dmactl & ATAPI_CONTROL1_START) { |
587 | dmactl &= ~ATAPI_CONTROL1_START; |
588 | dmactl |= ATAPI_CONTROL1_STOP; |
589 | iowrite32(dmactl, base + ATAPI_CONTROL1_REG); |
590 | } |
591 | |
592 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ |
593 | ata_sff_dma_pause(ap); |
594 | } |
595 | |
596 | static u8 sata_rcar_bmdma_status(struct ata_port *ap) |
597 | { |
598 | struct sata_rcar_priv *priv = ap->host->private_data; |
599 | u8 host_stat = 0; |
600 | u32 status; |
601 | |
602 | status = ioread32(priv->base + ATAPI_STATUS_REG); |
603 | if (status & ATAPI_STATUS_DEVINT) |
604 | host_stat |= ATA_DMA_INTR; |
605 | if (status & ATAPI_STATUS_ACT) |
606 | host_stat |= ATA_DMA_ACTIVE; |
607 | |
608 | return host_stat; |
609 | } |
610 | |
611 | static const struct scsi_host_template sata_rcar_sht = { |
612 | ATA_BASE_SHT(DRV_NAME), |
613 | /* |
614 | * This controller allows transfer chunks up to 512MB which cross 64KB |
615 | * boundaries, therefore the DMA limits are more relaxed than standard |
616 | * ATA SFF. |
617 | */ |
618 | .sg_tablesize = ATA_MAX_PRD, |
619 | .dma_boundary = SATA_RCAR_DMA_BOUNDARY, |
620 | }; |
621 | |
622 | static struct ata_port_operations sata_rcar_port_ops = { |
623 | .inherits = &ata_bmdma_port_ops, |
624 | |
625 | .freeze = sata_rcar_freeze, |
626 | .thaw = sata_rcar_thaw, |
627 | .softreset = sata_rcar_softreset, |
628 | |
629 | .scr_read = sata_rcar_scr_read, |
630 | .scr_write = sata_rcar_scr_write, |
631 | |
632 | .sff_dev_select = sata_rcar_dev_select, |
633 | .sff_set_devctl = sata_rcar_set_devctl, |
634 | .sff_check_status = sata_rcar_check_status, |
635 | .sff_check_altstatus = sata_rcar_check_altstatus, |
636 | .sff_tf_load = sata_rcar_tf_load, |
637 | .sff_tf_read = sata_rcar_tf_read, |
638 | .sff_exec_command = sata_rcar_exec_command, |
639 | .sff_data_xfer = sata_rcar_data_xfer, |
640 | .sff_drain_fifo = sata_rcar_drain_fifo, |
641 | |
642 | .qc_prep = sata_rcar_qc_prep, |
643 | |
644 | .bmdma_setup = sata_rcar_bmdma_setup, |
645 | .bmdma_start = sata_rcar_bmdma_start, |
646 | .bmdma_stop = sata_rcar_bmdma_stop, |
647 | .bmdma_status = sata_rcar_bmdma_status, |
648 | }; |
649 | |
650 | static void sata_rcar_serr_interrupt(struct ata_port *ap) |
651 | { |
652 | struct sata_rcar_priv *priv = ap->host->private_data; |
653 | struct ata_eh_info *ehi = &ap->link.eh_info; |
654 | int freeze = 0; |
655 | u32 serror; |
656 | |
657 | serror = ioread32(priv->base + SCRSERR_REG); |
658 | if (!serror) |
659 | return; |
660 | |
661 | ata_port_dbg(ap, "SError @host_intr: 0x%x\n" , serror); |
662 | |
663 | /* first, analyze and record host port events */ |
664 | ata_ehi_clear_desc(ehi); |
665 | |
666 | if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) { |
667 | /* Setup a soft-reset EH action */ |
668 | ata_ehi_hotplugged(ehi); |
669 | ata_ehi_push_desc(ehi, fmt: "%s" , "hotplug" ); |
670 | |
671 | freeze = serror & SERR_COMM_WAKE ? 0 : 1; |
672 | } |
673 | |
674 | /* freeze or abort */ |
675 | if (freeze) |
676 | ata_port_freeze(ap); |
677 | else |
678 | ata_port_abort(ap); |
679 | } |
680 | |
681 | static void sata_rcar_ata_interrupt(struct ata_port *ap) |
682 | { |
683 | struct ata_queued_cmd *qc; |
684 | int handled = 0; |
685 | |
686 | qc = ata_qc_from_tag(ap, tag: ap->link.active_tag); |
687 | if (qc) |
688 | handled |= ata_bmdma_port_intr(ap, qc); |
689 | |
690 | /* be sure to clear ATA interrupt */ |
691 | if (!handled) |
692 | sata_rcar_check_status(ap); |
693 | } |
694 | |
695 | static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) |
696 | { |
697 | struct ata_host *host = dev_instance; |
698 | struct sata_rcar_priv *priv = host->private_data; |
699 | void __iomem *base = priv->base; |
700 | unsigned int handled = 0; |
701 | struct ata_port *ap; |
702 | u32 sataintstat; |
703 | unsigned long flags; |
704 | |
705 | spin_lock_irqsave(&host->lock, flags); |
706 | |
707 | sataintstat = ioread32(base + SATAINTSTAT_REG); |
708 | sataintstat &= SATA_RCAR_INT_MASK; |
709 | if (!sataintstat) |
710 | goto done; |
711 | /* ack */ |
712 | iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG); |
713 | |
714 | ap = host->ports[0]; |
715 | |
716 | if (sataintstat & SATAINTSTAT_ATA) |
717 | sata_rcar_ata_interrupt(ap); |
718 | |
719 | if (sataintstat & SATAINTSTAT_SERR) |
720 | sata_rcar_serr_interrupt(ap); |
721 | |
722 | handled = 1; |
723 | done: |
724 | spin_unlock_irqrestore(lock: &host->lock, flags); |
725 | |
726 | return IRQ_RETVAL(handled); |
727 | } |
728 | |
729 | static void sata_rcar_setup_port(struct ata_host *host) |
730 | { |
731 | struct ata_port *ap = host->ports[0]; |
732 | struct ata_ioports *ioaddr = &ap->ioaddr; |
733 | struct sata_rcar_priv *priv = host->private_data; |
734 | void __iomem *base = priv->base; |
735 | |
736 | ap->ops = &sata_rcar_port_ops; |
737 | ap->pio_mask = ATA_PIO4; |
738 | ap->udma_mask = ATA_UDMA6; |
739 | ap->flags |= ATA_FLAG_SATA; |
740 | |
741 | if (priv->type == RCAR_R8A7790_ES1_SATA) |
742 | ap->flags |= ATA_FLAG_NO_DIPM; |
743 | |
744 | ioaddr->cmd_addr = base + SDATA_REG; |
745 | ioaddr->ctl_addr = base + SSDEVCON_REG; |
746 | ioaddr->scr_addr = base + SCRSSTS_REG; |
747 | ioaddr->altstatus_addr = ioaddr->ctl_addr; |
748 | |
749 | ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); |
750 | ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2); |
751 | ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2); |
752 | ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2); |
753 | ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2); |
754 | ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2); |
755 | ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2); |
756 | ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2); |
757 | ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2); |
758 | ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2); |
759 | } |
760 | |
761 | static void sata_rcar_init_module(struct sata_rcar_priv *priv) |
762 | { |
763 | void __iomem *base = priv->base; |
764 | u32 val; |
765 | |
766 | /* SATA-IP reset state */ |
767 | val = ioread32(base + ATAPI_CONTROL1_REG); |
768 | val |= ATAPI_CONTROL1_RESET; |
769 | iowrite32(val, base + ATAPI_CONTROL1_REG); |
770 | |
771 | /* ISM mode, PRD mode, DTEND flag at bit 0 */ |
772 | val = ioread32(base + ATAPI_CONTROL1_REG); |
773 | val |= ATAPI_CONTROL1_ISM; |
774 | val |= ATAPI_CONTROL1_DESE; |
775 | val |= ATAPI_CONTROL1_DTA32M; |
776 | iowrite32(val, base + ATAPI_CONTROL1_REG); |
777 | |
778 | /* Release the SATA-IP from the reset state */ |
779 | val = ioread32(base + ATAPI_CONTROL1_REG); |
780 | val &= ~ATAPI_CONTROL1_RESET; |
781 | iowrite32(val, base + ATAPI_CONTROL1_REG); |
782 | |
783 | /* ack and mask */ |
784 | iowrite32(0, base + SATAINTSTAT_REG); |
785 | iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); |
786 | |
787 | /* enable interrupts */ |
788 | iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); |
789 | } |
790 | |
791 | static void sata_rcar_init_controller(struct ata_host *host) |
792 | { |
793 | struct sata_rcar_priv *priv = host->private_data; |
794 | |
795 | priv->sataint_mask = SATAINTMASK_ALL_GEN2; |
796 | |
797 | /* reset and setup phy */ |
798 | switch (priv->type) { |
799 | case RCAR_GEN1_SATA: |
800 | priv->sataint_mask = SATAINTMASK_ALL_GEN1; |
801 | sata_rcar_gen1_phy_init(priv); |
802 | break; |
803 | case RCAR_GEN2_SATA: |
804 | case RCAR_R8A7790_ES1_SATA: |
805 | sata_rcar_gen2_phy_init(priv); |
806 | break; |
807 | case RCAR_GEN3_SATA: |
808 | break; |
809 | default: |
810 | dev_warn(host->dev, "SATA phy is not initialized\n" ); |
811 | break; |
812 | } |
813 | |
814 | sata_rcar_init_module(priv); |
815 | } |
816 | |
817 | static const struct of_device_id sata_rcar_match[] = { |
818 | { |
819 | /* Deprecated by "renesas,sata-r8a7779" */ |
820 | .compatible = "renesas,rcar-sata" , |
821 | .data = (void *)RCAR_GEN1_SATA, |
822 | }, |
823 | { |
824 | .compatible = "renesas,sata-r8a7779" , |
825 | .data = (void *)RCAR_GEN1_SATA, |
826 | }, |
827 | { |
828 | .compatible = "renesas,sata-r8a7790" , |
829 | .data = (void *)RCAR_GEN2_SATA |
830 | }, |
831 | { |
832 | .compatible = "renesas,sata-r8a7790-es1" , |
833 | .data = (void *)RCAR_R8A7790_ES1_SATA |
834 | }, |
835 | { |
836 | .compatible = "renesas,sata-r8a7791" , |
837 | .data = (void *)RCAR_GEN2_SATA |
838 | }, |
839 | { |
840 | .compatible = "renesas,sata-r8a7793" , |
841 | .data = (void *)RCAR_GEN2_SATA |
842 | }, |
843 | { |
844 | .compatible = "renesas,sata-r8a7795" , |
845 | .data = (void *)RCAR_GEN3_SATA |
846 | }, |
847 | { |
848 | .compatible = "renesas,rcar-gen2-sata" , |
849 | .data = (void *)RCAR_GEN2_SATA |
850 | }, |
851 | { |
852 | .compatible = "renesas,rcar-gen3-sata" , |
853 | .data = (void *)RCAR_GEN3_SATA |
854 | }, |
855 | { /* sentinel */ } |
856 | }; |
857 | MODULE_DEVICE_TABLE(of, sata_rcar_match); |
858 | |
859 | static int sata_rcar_probe(struct platform_device *pdev) |
860 | { |
861 | struct device *dev = &pdev->dev; |
862 | struct ata_host *host; |
863 | struct sata_rcar_priv *priv; |
864 | int irq, ret; |
865 | |
866 | irq = platform_get_irq(pdev, 0); |
867 | if (irq < 0) |
868 | return irq; |
869 | |
870 | priv = devm_kzalloc(dev, size: sizeof(struct sata_rcar_priv), GFP_KERNEL); |
871 | if (!priv) |
872 | return -ENOMEM; |
873 | |
874 | priv->type = (unsigned long)of_device_get_match_data(dev); |
875 | |
876 | pm_runtime_enable(dev); |
877 | ret = pm_runtime_get_sync(dev); |
878 | if (ret < 0) |
879 | goto err_pm_put; |
880 | |
881 | host = ata_host_alloc(dev, max_ports: 1); |
882 | if (!host) { |
883 | ret = -ENOMEM; |
884 | goto err_pm_put; |
885 | } |
886 | |
887 | host->private_data = priv; |
888 | |
889 | priv->base = devm_platform_ioremap_resource(pdev, index: 0); |
890 | if (IS_ERR(ptr: priv->base)) { |
891 | ret = PTR_ERR(ptr: priv->base); |
892 | goto err_pm_put; |
893 | } |
894 | |
895 | /* setup port */ |
896 | sata_rcar_setup_port(host); |
897 | |
898 | /* initialize host controller */ |
899 | sata_rcar_init_controller(host); |
900 | |
901 | ret = ata_host_activate(host, irq, irq_handler: sata_rcar_interrupt, irq_flags: 0, |
902 | sht: &sata_rcar_sht); |
903 | if (!ret) |
904 | return 0; |
905 | |
906 | err_pm_put: |
907 | pm_runtime_put(dev); |
908 | pm_runtime_disable(dev); |
909 | return ret; |
910 | } |
911 | |
912 | static void sata_rcar_remove(struct platform_device *pdev) |
913 | { |
914 | struct ata_host *host = platform_get_drvdata(pdev); |
915 | struct sata_rcar_priv *priv = host->private_data; |
916 | void __iomem *base = priv->base; |
917 | |
918 | ata_host_detach(host); |
919 | |
920 | /* disable interrupts */ |
921 | iowrite32(0, base + ATAPI_INT_ENABLE_REG); |
922 | /* ack and mask */ |
923 | iowrite32(0, base + SATAINTSTAT_REG); |
924 | iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); |
925 | |
926 | pm_runtime_put(dev: &pdev->dev); |
927 | pm_runtime_disable(dev: &pdev->dev); |
928 | } |
929 | |
930 | #ifdef CONFIG_PM_SLEEP |
931 | static int sata_rcar_suspend(struct device *dev) |
932 | { |
933 | struct ata_host *host = dev_get_drvdata(dev); |
934 | struct sata_rcar_priv *priv = host->private_data; |
935 | void __iomem *base = priv->base; |
936 | |
937 | ata_host_suspend(host, PMSG_SUSPEND); |
938 | |
939 | /* disable interrupts */ |
940 | iowrite32(0, base + ATAPI_INT_ENABLE_REG); |
941 | /* mask */ |
942 | iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); |
943 | |
944 | pm_runtime_put(dev); |
945 | |
946 | return 0; |
947 | } |
948 | |
949 | static int sata_rcar_resume(struct device *dev) |
950 | { |
951 | struct ata_host *host = dev_get_drvdata(dev); |
952 | struct sata_rcar_priv *priv = host->private_data; |
953 | void __iomem *base = priv->base; |
954 | int ret; |
955 | |
956 | ret = pm_runtime_get_sync(dev); |
957 | if (ret < 0) { |
958 | pm_runtime_put(dev); |
959 | return ret; |
960 | } |
961 | |
962 | if (priv->type == RCAR_GEN3_SATA) { |
963 | sata_rcar_init_module(priv); |
964 | } else { |
965 | /* ack and mask */ |
966 | iowrite32(0, base + SATAINTSTAT_REG); |
967 | iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); |
968 | |
969 | /* enable interrupts */ |
970 | iowrite32(ATAPI_INT_ENABLE_SATAINT, |
971 | base + ATAPI_INT_ENABLE_REG); |
972 | } |
973 | |
974 | ata_host_resume(host); |
975 | |
976 | return 0; |
977 | } |
978 | |
979 | static int sata_rcar_restore(struct device *dev) |
980 | { |
981 | struct ata_host *host = dev_get_drvdata(dev); |
982 | int ret; |
983 | |
984 | ret = pm_runtime_get_sync(dev); |
985 | if (ret < 0) { |
986 | pm_runtime_put(dev); |
987 | return ret; |
988 | } |
989 | |
990 | sata_rcar_setup_port(host); |
991 | |
992 | /* initialize host controller */ |
993 | sata_rcar_init_controller(host); |
994 | |
995 | ata_host_resume(host); |
996 | |
997 | return 0; |
998 | } |
999 | |
1000 | static const struct dev_pm_ops sata_rcar_pm_ops = { |
1001 | .suspend = sata_rcar_suspend, |
1002 | .resume = sata_rcar_resume, |
1003 | .freeze = sata_rcar_suspend, |
1004 | .thaw = sata_rcar_resume, |
1005 | .poweroff = sata_rcar_suspend, |
1006 | .restore = sata_rcar_restore, |
1007 | }; |
1008 | #endif |
1009 | |
1010 | static struct platform_driver sata_rcar_driver = { |
1011 | .probe = sata_rcar_probe, |
1012 | .remove_new = sata_rcar_remove, |
1013 | .driver = { |
1014 | .name = DRV_NAME, |
1015 | .of_match_table = sata_rcar_match, |
1016 | #ifdef CONFIG_PM_SLEEP |
1017 | .pm = &sata_rcar_pm_ops, |
1018 | #endif |
1019 | }, |
1020 | }; |
1021 | |
1022 | module_platform_driver(sata_rcar_driver); |
1023 | |
1024 | MODULE_LICENSE("GPL" ); |
1025 | MODULE_AUTHOR("Vladimir Barinov" ); |
1026 | MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver" ); |
1027 | |