1/*
2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
21*/
22
23/*
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
26*/
27
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/sched/signal.h>
31#include <linux/mm.h>
32#include <linux/pci.h>
33#include <linux/errno.h>
34#include <linux/atm.h>
35#include <linux/atmdev.h>
36#include <linux/sonet.h>
37#include <linux/skbuff.h>
38#include <linux/time.h>
39#include <linux/delay.h>
40#include <linux/uio.h>
41#include <linux/init.h>
42#include <linux/interrupt.h>
43#include <linux/ioport.h>
44#include <linux/wait.h>
45#include <linux/slab.h>
46
47#include <asm/io.h>
48#include <linux/atomic.h>
49#include <linux/uaccess.h>
50#include <asm/string.h>
51#include <asm/byteorder.h>
52
53#include "horizon.h"
54
55#define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
56#define description_string "Madge ATM Horizon [Ultra] driver"
57#define version_string "1.2.1"
58
59static inline void __init show_version (void) {
60 printk ("%s version %s\n", description_string, version_string);
61}
62
63/*
64
65 CREDITS
66
67 Driver and documentation by:
68
69 Chris Aston Madge Networks
70 Giuliano Procida Madge Networks
71 Simon Benham Madge Networks
72 Simon Johnson Madge Networks
73 Various Others Madge Networks
74
75 Some inspiration taken from other drivers by:
76
77 Alexandru Cucos UTBv
78 Kari Mettinen University of Helsinki
79 Werner Almesberger EPFL LRC
80
81 Theory of Operation
82
83 I Hardware, detection, initialisation and shutdown.
84
85 1. Supported Hardware
86
87 This driver should handle all variants of the PCI Madge ATM adapters
88 with the Horizon chipset. These are all PCI cards supporting PIO, BM
89 DMA and a form of MMIO (registers only, not internal RAM).
90
91 The driver is only known to work with SONET and UTP Horizon Ultra
92 cards at 155Mb/s. However, code is in place to deal with both the
93 original Horizon and 25Mb/s operation.
94
95 There are two revisions of the Horizon ASIC: the original and the
96 Ultra. Details of hardware bugs are in section III.
97
98 The ASIC version can be distinguished by chip markings but is NOT
99 indicated by the PCI revision (all adapters seem to have PCI rev 1).
100
101 I believe that:
102
103 Horizon => Collage 25 PCI Adapter (UTP and STP)
104 Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
105 Ambassador x => Collage 155 PCI Server (completely different)
106
107 Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
108 have a Madge B154 plus glue logic serializer. I have also found a
109 really ancient version of this with slightly different glue. It
110 comes with the revision 0 (140-025-01) ASIC.
111
112 Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
113 output (UTP) or an HP HFBR 5205 output (SONET). It has either
114 Madge's SAMBA framer or a SUNI-lite device (early versions). It
115 comes with the revision 1 (140-027-01) ASIC.
116
117 2. Detection
118
119 All Horizon-based cards present with the same PCI Vendor and Device
120 IDs. The standard Linux 2.2 PCI API is used to locate any cards and
121 to enable bus-mastering (with appropriate latency).
122
123 ATM_LAYER_STATUS in the control register distinguishes between the
124 two possible physical layers (25 and 155). It is not clear whether
125 the 155 cards can also operate at 25Mbps. We rely on the fact that a
126 card operates at 155 if and only if it has the newer Horizon Ultra
127 ASIC.
128
129 For 155 cards the two possible framers are probed for and then set
130 up for loop-timing.
131
132 3. Initialisation
133
134 The card is reset and then put into a known state. The physical
135 layer is configured for normal operation at the appropriate speed;
136 in the case of the 155 cards, the framer is initialised with
137 line-based timing; the internal RAM is zeroed and the allocation of
138 buffers for RX and TX is made; the Burnt In Address is read and
139 copied to the ATM ESI; various policy settings for RX (VPI bits,
140 unknown VCs, oam cells) are made. Ideally all policy items should be
141 configurable at module load (if not actually on-demand), however,
142 only the vpi vs vci bit allocation can be specified at insmod.
143
144 4. Shutdown
145
146 This is in response to module_cleaup. No VCs are in use and the card
147 should be idle; it is reset.
148
149 II Driver software (as it should be)
150
151 0. Traffic Parameters
152
153 The traffic classes (not an enumeration) are currently: ATM_NONE (no
154 traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
155 (compatible with everything). Together with (perhaps only some of)
156 the following items they make up the traffic specification.
157
158 struct atm_trafprm {
159 unsigned char traffic_class; traffic class (ATM_UBR, ...)
160 int max_pcr; maximum PCR in cells per second
161 int pcr; desired PCR in cells per second
162 int min_pcr; minimum PCR in cells per second
163 int max_cdv; maximum CDV in microseconds
164 int max_sdu; maximum SDU in bytes
165 };
166
167 Note that these denote bandwidth available not bandwidth used; the
168 possibilities according to ATMF are:
169
170 Real Time (cdv and max CDT given)
171
172 CBR(pcr) pcr bandwidth always available
173 rtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too
174
175 Non Real Time
176
177 nrtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too
178 UBR()
179 ABR(mcr,pcr) mcr bandwidth always available, up to pcr (depending) too
180
181 mbs is max burst size (bucket)
182 pcr and scr have associated cdvt values
183 mcr is like scr but has no cdtv
184 cdtv may differ at each hop
185
186 Some of the above items are qos items (as opposed to traffic
187 parameters). We have nothing to do with qos. All except ABR can have
188 their traffic parameters converted to GCRA parameters. The GCRA may
189 be implemented as a (real-number) leaky bucket. The GCRA can be used
190 in complicated ways by switches and in simpler ways by end-stations.
191 It can be used both to filter incoming cells and shape out-going
192 cells.
193
194 ATM Linux actually supports:
195
196 ATM_NONE() (no traffic in this direction)
197 ATM_UBR(max_frame_size)
198 ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
199
200 0 or ATM_MAX_PCR are used to indicate maximum available PCR
201
202 A traffic specification consists of the AAL type and separate
203 traffic specifications for either direction. In ATM Linux it is:
204
205 struct atm_qos {
206 struct atm_trafprm txtp;
207 struct atm_trafprm rxtp;
208 unsigned char aal;
209 };
210
211 AAL types are:
212
213 ATM_NO_AAL AAL not specified
214 ATM_AAL0 "raw" ATM cells
215 ATM_AAL1 AAL1 (CBR)
216 ATM_AAL2 AAL2 (VBR)
217 ATM_AAL34 AAL3/4 (data)
218 ATM_AAL5 AAL5 (data)
219 ATM_SAAL signaling AAL
220
221 The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
222 it does not implement AAL 3/4 SAR and it has a different notion of
223 "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
224 supported by this driver.
225
226 The Horizon has limited support for ABR (including UBR), VBR and
227 CBR. Each TX channel has a bucket (containing up to 31 cell units)
228 and two timers (PCR and SCR) associated with it that can be used to
229 govern cell emissions and host notification (in the case of ABR this
230 is presumably so that RM cells may be emitted at appropriate times).
231 The timers may either be disabled or may be set to any of 240 values
232 (determined by the clock crystal, a fixed (?) per-device divider, a
233 configurable divider and a configurable timer preload value).
234
235 At the moment only UBR and CBR are supported by the driver. VBR will
236 be supported as soon as ATM for Linux supports it. ABR support is
237 very unlikely as RM cell handling is completely up to the driver.
238
239 1. TX (TX channel setup and TX transfer)
240
241 The TX half of the driver owns the TX Horizon registers. The TX
242 component in the IRQ handler is the BM completion handler. This can
243 only be entered when tx_busy is true (enforced by hardware). The
244 other TX component can only be entered when tx_busy is false
245 (enforced by driver). So TX is single-threaded.
246
247 Apart from a minor optimisation to not re-select the last channel,
248 the TX send component works as follows:
249
250 Atomic test and set tx_busy until we succeed; we should implement
251 some sort of timeout so that tx_busy will never be stuck at true.
252
253 If no TX channel is set up for this VC we wait for an idle one (if
254 necessary) and set it up.
255
256 At this point we have a TX channel ready for use. We wait for enough
257 buffers to become available then start a TX transmit (set the TX
258 descriptor, schedule transfer, exit).
259
260 The IRQ component handles TX completion (stats, free buffer, tx_busy
261 unset, exit). We also re-schedule further transfers for the same
262 frame if needed.
263
264 TX setup in more detail:
265
266 TX open is a nop, the relevant information is held in the hrz_vcc
267 (vcc->dev_data) structure and is "cached" on the card.
268
269 TX close gets the TX lock and clears the channel from the "cache".
270
271 2. RX (Data Available and RX transfer)
272
273 The RX half of the driver owns the RX registers. There are two RX
274 components in the IRQ handler: the data available handler deals with
275 fresh data that has arrived on the card, the BM completion handler
276 is very similar to the TX completion handler. The data available
277 handler grabs the rx_lock and it is only released once the data has
278 been discarded or completely transferred to the host. The BM
279 completion handler only runs when the lock is held; the data
280 available handler is locked out over the same period.
281
282 Data available on the card triggers an interrupt. If the data is not
283 suitable for our existing RX channels or we cannot allocate a buffer
284 it is flushed. Otherwise an RX receive is scheduled. Multiple RX
285 transfers may be scheduled for the same frame.
286
287 RX setup in more detail:
288
289 RX open...
290 RX close...
291
292 III Hardware Bugs
293
294 0. Byte vs Word addressing of adapter RAM.
295
296 A design feature; see the .h file (especially the memory map).
297
298 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
299
300 The host must not start a transmit direction transfer at a
301 non-four-byte boundary in host memory. Instead the host should
302 perform a byte, or a two byte, or one byte followed by two byte
303 transfer in order to start the rest of the transfer on a four byte
304 boundary. RX is OK.
305
306 Simultaneous transmit and receive direction bus master transfers are
307 not allowed.
308
309 The simplest solution to these two is to always do PIO (never DMA)
310 in the TX direction on the original Horizon. More complicated
311 solutions are likely to hurt my brain.
312
313 2. Loss of buffer on close VC
314
315 When a VC is being closed, the buffer associated with it is not
316 returned to the pool. The host must store the reference to this
317 buffer and when opening a new VC then give it to that new VC.
318
319 The host intervention currently consists of stacking such a buffer
320 pointer at VC close and checking the stack at VC open.
321
322 3. Failure to close a VC
323
324 If a VC is currently receiving a frame then closing the VC may fail
325 and the frame continues to be received.
326
327 The solution is to make sure any received frames are flushed when
328 ready. This is currently done just before the solution to 2.
329
330 4. PCI bus (original Horizon only, fixed in Ultra)
331
332 Reading from the data port prior to initialisation will hang the PCI
333 bus. Just don't do that then! We don't.
334
335 IV To Do List
336
337 . Timer code may be broken.
338
339 . Allow users to specify buffer allocation split for TX and RX.
340
341 . Deal once and for all with buggy VC close.
342
343 . Handle interrupted and/or non-blocking operations.
344
345 . Change some macros to functions and move from .h to .c.
346
347 . Try to limit the number of TX frames each VC may have queued, in
348 order to reduce the chances of TX buffer exhaustion.
349
350 . Implement VBR (bucket and timers not understood) and ABR (need to
351 do RM cells manually); also no Linux support for either.
352
353 . Implement QoS changes on open VCs (involves extracting parts of VC open
354 and close into separate functions and using them to make changes).
355
356*/
357
358/********** globals **********/
359
360static void do_housekeeping (struct timer_list *t);
361
362static unsigned short debug = 0;
363static unsigned short vpi_bits = 0;
364static int max_tx_size = 9000;
365static int max_rx_size = 9000;
366static unsigned char pci_lat = 0;
367
368/********** access functions **********/
369
370/* Read / Write Horizon registers */
371static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) {
372 outl (cpu_to_le32 (data), dev->iobase + reg);
373}
374
375static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) {
376 return le32_to_cpu (inl (dev->iobase + reg));
377}
378
379static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) {
380 outw (cpu_to_le16 (data), dev->iobase + reg);
381}
382
383static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {
384 return le16_to_cpu (inw (dev->iobase + reg));
385}
386
387static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
388 outsb (dev->iobase + reg, addr, len);
389}
390
391static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
392 insb (dev->iobase + reg, addr, len);
393}
394
395/* Read / Write to a given address in Horizon buffer memory.
396 Interrupts must be disabled between the address register and data
397 port accesses as these must form an atomic operation. */
398static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) {
399 // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
400 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
401 wr_regl (dev, MEMORY_PORT_OFF, data);
402}
403
404static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) {
405 // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
406 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
407 return rd_regl (dev, MEMORY_PORT_OFF);
408}
409
410static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) {
411 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000);
412 wr_regl (dev, MEMORY_PORT_OFF, data);
413}
414
415static inline u32 rd_framer (const hrz_dev * dev, u32 addr) {
416 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000);
417 return rd_regl (dev, MEMORY_PORT_OFF);
418}
419
420/********** specialised access functions **********/
421
422/* RX */
423
424static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) {
425 wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel);
426 return;
427}
428
429static void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) {
430 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)
431 ;
432 return;
433}
434
435static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) {
436 wr_regw (dev, RX_CHANNEL_PORT_OFF, channel);
437 return;
438}
439
440static void WAIT_UPDATE_COMPLETE (hrz_dev * dev) {
441 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)
442 ;
443 return;
444}
445
446/* TX */
447
448static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) {
449 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel);
450 return;
451}
452
453/* Update or query one configuration parameter of a particular channel. */
454
455static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) {
456 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
457 chan * TX_CHANNEL_CONFIG_MULT | mode);
458 wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value);
459 return;
460}
461
462/********** dump functions **********/
463
464static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
465#ifdef DEBUG_HORIZON
466 unsigned int i;
467 unsigned char * data = skb->data;
468 PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
469 for (i=0; i<skb->len && i < 256;i++)
470 PRINTDM (DBG_DATA, "%02x ", data[i]);
471 PRINTDE (DBG_DATA,"");
472#else
473 (void) prefix;
474 (void) vc;
475 (void) skb;
476#endif
477 return;
478}
479
480static inline void dump_regs (hrz_dev * dev) {
481#ifdef DEBUG_HORIZON
482 PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG));
483 PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
484 PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
485 PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
486 PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF));
487 PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF));
488#else
489 (void) dev;
490#endif
491 return;
492}
493
494static inline void dump_framer (hrz_dev * dev) {
495#ifdef DEBUG_HORIZON
496 unsigned int i;
497 PRINTDB (DBG_REGS, "framer registers:");
498 for (i = 0; i < 0x10; ++i)
499 PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i));
500 PRINTDE (DBG_REGS,"");
501#else
502 (void) dev;
503#endif
504 return;
505}
506
507/********** VPI/VCI <-> (RX) channel conversions **********/
508
509/* RX channels are 10 bit integers, these fns are quite paranoid */
510
511static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) {
512 unsigned short vci_bits = 10 - vpi_bits;
513 if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) {
514 *channel = vpi<<vci_bits | vci;
515 return *channel ? 0 : -EINVAL;
516 }
517 return -EINVAL;
518}
519
520/********** decode RX queue entries **********/
521
522static inline u16 rx_q_entry_to_length (u32 x) {
523 return x & RX_Q_ENTRY_LENGTH_MASK;
524}
525
526static inline u16 rx_q_entry_to_rx_channel (u32 x) {
527 return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK;
528}
529
530/* Cell Transmit Rate Values
531 *
532 * the cell transmit rate (cells per sec) can be set to a variety of
533 * different values by specifying two parameters: a timer preload from
534 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
535 * an exponent from 0 to 14; the special value 15 disables the timer).
536 *
537 * cellrate = baserate / (preload * 2^divider)
538 *
539 * The maximum cell rate that can be specified is therefore just the
540 * base rate. Halving the preload is equivalent to adding 1 to the
541 * divider and so values 1 to 8 of the preload are redundant except
542 * in the case of a maximal divider (14).
543 *
544 * Given a desired cell rate, an algorithm to determine the preload
545 * and divider is:
546 *
547 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
548 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
549 * if x <= 16 then set p = x, d = 0 (high rates), done
550 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
551 * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
552 * we find the range (n will be between 1 and 14), set d = n
553 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
554 *
555 * The algorithm used below is a minor variant of the above.
556 *
557 * The base rate is derived from the oscillator frequency (Hz) using a
558 * fixed divider:
559 *
560 * baserate = freq / 32 in the case of some Unknown Card
561 * baserate = freq / 8 in the case of the Horizon 25
562 * baserate = freq / 8 in the case of the Horizon Ultra 155
563 *
564 * The Horizon cards have oscillators and base rates as follows:
565 *
566 * Card Oscillator Base Rate
567 * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq)
568 * Horizon 25 32 MHz 4 MHz
569 * Horizon Ultra 155 40 MHz 5 MHz
570 *
571 * The following defines give the base rates in Hz. These were
572 * previously a factor of 100 larger, no doubt someone was using
573 * cps*100.
574 */
575
576#define BR_UKN 1031250l
577#define BR_HRZ 4000000l
578#define BR_ULT 5000000l
579
580// d is an exponent
581#define CR_MIND 0
582#define CR_MAXD 14
583
584// p ranges from 1 to a power of 2
585#define CR_MAXPEXP 4
586
587static int make_rate (const hrz_dev * dev, u32 c, rounding r,
588 u16 * bits, unsigned int * actual)
589{
590 // note: rounding the rate down means rounding 'p' up
591 const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ;
592
593 u32 div = CR_MIND;
594 u32 pre;
595
596 // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
597 // the tests below. We could think harder about exact possibilities
598 // of failure...
599
600 unsigned long br_man = br;
601 unsigned int br_exp = 0;
602
603 PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c,
604 r == round_up ? "up" : r == round_down ? "down" : "nearest");
605
606 // avoid div by zero
607 if (!c) {
608 PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!");
609 return -EINVAL;
610 }
611
612 while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) {
613 br_man = br_man >> 1;
614 ++br_exp;
615 }
616 // (br >>br_exp) <<br_exp == br and
617 // br_exp <= CR_MAXPEXP+CR_MIND
618
619 if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) {
620 // Equivalent to: B <= (c << (MAXPEXP+MIND))
621 // take care of rounding
622 switch (r) {
623 case round_down:
624 pre = DIV_ROUND_UP(br, c<<div);
625 // but p must be non-zero
626 if (!pre)
627 pre = 1;
628 break;
629 case round_nearest:
630 pre = DIV_ROUND_CLOSEST(br, c<<div);
631 // but p must be non-zero
632 if (!pre)
633 pre = 1;
634 break;
635 default: /* round_up */
636 pre = br/(c<<div);
637 // but p must be non-zero
638 if (!pre)
639 return -EINVAL;
640 }
641 PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div);
642 goto got_it;
643 }
644
645 // at this point we have
646 // d == MIND and (c << (MAXPEXP+MIND)) < B
647 while (div < CR_MAXD) {
648 div++;
649 if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) {
650 // Equivalent to: B <= (c << (MAXPEXP+d))
651 // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
652 // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
653 // MAXP/2 < B/c2^d <= MAXP
654 // take care of rounding
655 switch (r) {
656 case round_down:
657 pre = DIV_ROUND_UP(br, c<<div);
658 break;
659 case round_nearest:
660 pre = DIV_ROUND_CLOSEST(br, c<<div);
661 break;
662 default: /* round_up */
663 pre = br/(c<<div);
664 }
665 PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div);
666 goto got_it;
667 }
668 }
669 // at this point we have
670 // d == MAXD and (c << (MAXPEXP+MAXD)) < B
671 // but we cannot go any higher
672 // take care of rounding
673 if (r == round_down)
674 return -EINVAL;
675 pre = 1 << CR_MAXPEXP;
676 PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div);
677got_it:
678 // paranoia
679 if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) {
680 PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u",
681 div, pre);
682 return -EINVAL;
683 } else {
684 if (bits)
685 *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1);
686 if (actual) {
687 *actual = DIV_ROUND_UP(br, pre<<div);
688 PRINTD (DBG_QOS, "actual rate: %u", *actual);
689 }
690 return 0;
691 }
692}
693
694static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol,
695 u16 * bit_pattern, unsigned int * actual) {
696 unsigned int my_actual;
697
698 PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u",
699 c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol);
700
701 if (!actual)
702 // actual rate is not returned
703 actual = &my_actual;
704
705 if (make_rate (dev, c, round_nearest, bit_pattern, actual))
706 // should never happen as round_nearest always succeeds
707 return -1;
708
709 if (c - tol <= *actual && *actual <= c + tol)
710 // within tolerance
711 return 0;
712 else
713 // intolerant, try rounding instead
714 return make_rate (dev, c, r, bit_pattern, actual);
715}
716
717/********** Listen on a VC **********/
718
719static int hrz_open_rx (hrz_dev * dev, u16 channel) {
720 // is there any guarantee that we don't get two simulataneous
721 // identical calls of this function from different processes? yes
722 // rate_lock
723 unsigned long flags;
724 u32 channel_type; // u16?
725
726 u16 buf_ptr = RX_CHANNEL_IDLE;
727
728 rx_ch_desc * rx_desc = &memmap->rx_descs[channel];
729
730 PRINTD (DBG_FLOW, "hrz_open_rx %x", channel);
731
732 spin_lock_irqsave (&dev->mem_lock, flags);
733 channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
734 spin_unlock_irqrestore (&dev->mem_lock, flags);
735
736 // very serious error, should never occur
737 if (channel_type != RX_CHANNEL_DISABLED) {
738 PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open");
739 return -EBUSY; // clean up?
740 }
741
742 // Give back spare buffer
743 if (dev->noof_spare_buffers) {
744 buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers];
745 PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr);
746 // should never occur
747 if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) {
748 // but easy to recover from
749 PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE");
750 buf_ptr = RX_CHANNEL_IDLE;
751 }
752 } else {
753 PRINTD (DBG_VCC, "using IDLE buffer pointer");
754 }
755
756 // Channel is currently disabled so change its status to idle
757
758 // do we really need to save the flags again?
759 spin_lock_irqsave (&dev->mem_lock, flags);
760
761 wr_mem (dev, &rx_desc->wr_buf_type,
762 buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME);
763 if (buf_ptr != RX_CHANNEL_IDLE)
764 wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr);
765
766 spin_unlock_irqrestore (&dev->mem_lock, flags);
767
768 // rxer->rate = make_rate (qos->peak_cells);
769
770 PRINTD (DBG_FLOW, "hrz_open_rx ok");
771
772 return 0;
773}
774
775#if 0
776/********** change vc rate for a given vc **********/
777
778static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) {
779 rxer->rate = make_rate (qos->peak_cells);
780}
781#endif
782
783/********** free an skb (as per ATM device driver documentation) **********/
784
785static void hrz_kfree_skb (struct sk_buff * skb) {
786 if (ATM_SKB(skb)->vcc->pop) {
787 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
788 } else {
789 dev_kfree_skb_any (skb);
790 }
791}
792
793/********** cancel listen on a VC **********/
794
795static void hrz_close_rx (hrz_dev * dev, u16 vc) {
796 unsigned long flags;
797
798 u32 value;
799
800 u32 r1, r2;
801
802 rx_ch_desc * rx_desc = &memmap->rx_descs[vc];
803
804 int was_idle = 0;
805
806 spin_lock_irqsave (&dev->mem_lock, flags);
807 value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
808 spin_unlock_irqrestore (&dev->mem_lock, flags);
809
810 if (value == RX_CHANNEL_DISABLED) {
811 // I suppose this could happen once we deal with _NONE traffic properly
812 PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc);
813 return;
814 }
815 if (value == RX_CHANNEL_IDLE)
816 was_idle = 1;
817
818 spin_lock_irqsave (&dev->mem_lock, flags);
819
820 for (;;) {
821 wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED);
822
823 if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED)
824 break;
825
826 was_idle = 0;
827 }
828
829 if (was_idle) {
830 spin_unlock_irqrestore (&dev->mem_lock, flags);
831 return;
832 }
833
834 WAIT_FLUSH_RX_COMPLETE(dev);
835
836 // XXX Is this all really necessary? We can rely on the rx_data_av
837 // handler to discard frames that remain queued for delivery. If the
838 // worry is that immediately reopening the channel (perhaps by a
839 // different process) may cause some data to be mis-delivered then
840 // there may still be a simpler solution (such as busy-waiting on
841 // rx_busy once the channel is disabled or before a new one is
842 // opened - does this leave any holes?). Arguably setting up and
843 // tearing down the TX and RX halves of each virtual circuit could
844 // most safely be done within ?x_busy protected regions.
845
846 // OK, current changes are that Simon's marker is disabled and we DO
847 // look for NULL rxer elsewhere. The code here seems flush frames
848 // and then remember the last dead cell belonging to the channel
849 // just disabled - the cell gets relinked at the next vc_open.
850 // However, when all VCs are closed or only a few opened there are a
851 // handful of buffers that are unusable.
852
853 // Does anyone feel like documenting spare_buffers properly?
854 // Does anyone feel like fixing this in a nicer way?
855
856 // Flush any data which is left in the channel
857 for (;;) {
858 // Change the rx channel port to something different to the RX
859 // channel we are trying to close to force Horizon to flush the rx
860 // channel read and write pointers.
861
862 u16 other = vc^(RX_CHANS/2);
863
864 SELECT_RX_CHANNEL (dev, other);
865 WAIT_UPDATE_COMPLETE (dev);
866
867 r1 = rd_mem (dev, &rx_desc->rd_buf_type);
868
869 // Select this RX channel. Flush doesn't seem to work unless we
870 // select an RX channel before hand
871
872 SELECT_RX_CHANNEL (dev, vc);
873 WAIT_UPDATE_COMPLETE (dev);
874
875 // Attempt to flush a frame on this RX channel
876
877 FLUSH_RX_CHANNEL (dev, vc);
878 WAIT_FLUSH_RX_COMPLETE (dev);
879
880 // Force Horizon to flush rx channel read and write pointers as before
881
882 SELECT_RX_CHANNEL (dev, other);
883 WAIT_UPDATE_COMPLETE (dev);
884
885 r2 = rd_mem (dev, &rx_desc->rd_buf_type);
886
887 PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2);
888
889 if (r1 == r2) {
890 dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1;
891 break;
892 }
893 }
894
895#if 0
896 {
897 rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];
898 rx_q_entry * rd_ptr = dev->rx_q_entry;
899
900 PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr);
901
902 while (rd_ptr != wr_ptr) {
903 u32 x = rd_mem (dev, (HDW *) rd_ptr);
904
905 if (vc == rx_q_entry_to_rx_channel (x)) {
906 x |= SIMONS_DODGEY_MARKER;
907
908 PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey");
909
910 wr_mem (dev, (HDW *) rd_ptr, x);
911 }
912
913 if (rd_ptr == dev->rx_q_wrap)
914 rd_ptr = dev->rx_q_reset;
915 else
916 rd_ptr++;
917 }
918 }
919#endif
920
921 spin_unlock_irqrestore (&dev->mem_lock, flags);
922
923 return;
924}
925
926/********** schedule RX transfers **********/
927
928// Note on tail recursion: a GCC developer said that it is not likely
929// to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
930// are sure it does as you may otherwise overflow the kernel stack.
931
932// giving this fn a return value would help GCC, allegedly
933
934static void rx_schedule (hrz_dev * dev, int irq) {
935 unsigned int rx_bytes;
936
937 int pio_instead = 0;
938#ifndef TAILRECURSIONWORKS
939 pio_instead = 1;
940 while (pio_instead) {
941#endif
942 // bytes waiting for RX transfer
943 rx_bytes = dev->rx_bytes;
944
945#if 0
946 spin_count = 0;
947 while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) {
948 PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!");
949 if (++spin_count > 10) {
950 PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion");
951 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
952 clear_bit (rx_busy, &dev->flags);
953 hrz_kfree_skb (dev->rx_skb);
954 return;
955 }
956 }
957#endif
958
959 // this code follows the TX code but (at the moment) there is only
960 // one region - the skb itself. I don't know if this will change,
961 // but it doesn't hurt to have the code here, disabled.
962
963 if (rx_bytes) {
964 // start next transfer within same region
965 if (rx_bytes <= MAX_PIO_COUNT) {
966 PRINTD (DBG_RX|DBG_BUS, "(pio)");
967 pio_instead = 1;
968 }
969 if (rx_bytes <= MAX_TRANSFER_COUNT) {
970 PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)");
971 dev->rx_bytes = 0;
972 } else {
973 PRINTD (DBG_RX|DBG_BUS, "(continuing multi)");
974 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
975 rx_bytes = MAX_TRANSFER_COUNT;
976 }
977 } else {
978 // rx_bytes == 0 -- we're between regions
979 // regions remaining to transfer
980#if 0
981 unsigned int rx_regions = dev->rx_regions;
982#else
983 unsigned int rx_regions = 0;
984#endif
985
986 if (rx_regions) {
987#if 0
988 // start a new region
989 dev->rx_addr = dev->rx_iovec->iov_base;
990 rx_bytes = dev->rx_iovec->iov_len;
991 ++dev->rx_iovec;
992 dev->rx_regions = rx_regions - 1;
993
994 if (rx_bytes <= MAX_PIO_COUNT) {
995 PRINTD (DBG_RX|DBG_BUS, "(pio)");
996 pio_instead = 1;
997 }
998 if (rx_bytes <= MAX_TRANSFER_COUNT) {
999 PRINTD (DBG_RX|DBG_BUS, "(full region)");
1000 dev->rx_bytes = 0;
1001 } else {
1002 PRINTD (DBG_RX|DBG_BUS, "(start multi region)");
1003 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
1004 rx_bytes = MAX_TRANSFER_COUNT;
1005 }
1006#endif
1007 } else {
1008 // rx_regions == 0
1009 // that's all folks - end of frame
1010 struct sk_buff * skb = dev->rx_skb;
1011 // dev->rx_iovec = 0;
1012
1013 FLUSH_RX_CHANNEL (dev, dev->rx_channel);
1014
1015 dump_skb ("<<<", dev->rx_channel, skb);
1016
1017 PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len);
1018
1019 {
1020 struct atm_vcc * vcc = ATM_SKB(skb)->vcc;
1021 // VC layer stats
1022 atomic_inc(&vcc->stats->rx);
1023 __net_timestamp(skb);
1024 // end of our responsibility
1025 vcc->push (vcc, skb);
1026 }
1027 }
1028 }
1029
1030 // note: writing RX_COUNT clears any interrupt condition
1031 if (rx_bytes) {
1032 if (pio_instead) {
1033 if (irq)
1034 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1035 rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes);
1036 } else {
1037 wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr));
1038 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes);
1039 }
1040 dev->rx_addr += rx_bytes;
1041 } else {
1042 if (irq)
1043 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1044 // allow another RX thread to start
1045 YELLOW_LED_ON(dev);
1046 clear_bit (rx_busy, &dev->flags);
1047 PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev);
1048 }
1049
1050#ifdef TAILRECURSIONWORKS
1051 // and we all bless optimised tail calls
1052 if (pio_instead)
1053 return rx_schedule (dev, 0);
1054 return;
1055#else
1056 // grrrrrrr!
1057 irq = 0;
1058 }
1059 return;
1060#endif
1061}
1062
1063/********** handle RX bus master complete events **********/
1064
1065static void rx_bus_master_complete_handler (hrz_dev * dev) {
1066 if (test_bit (rx_busy, &dev->flags)) {
1067 rx_schedule (dev, 1);
1068 } else {
1069 PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion");
1070 // clear interrupt condition on adapter
1071 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1072 }
1073 return;
1074}
1075
1076/********** (queue to) become the next TX thread **********/
1077
1078static int tx_hold (hrz_dev * dev) {
1079 PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
1080 wait_event_interruptible(dev->tx_queue, (!test_and_set_bit(tx_busy, &dev->flags)));
1081 PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
1082 if (signal_pending (current))
1083 return -1;
1084 PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
1085 return 0;
1086}
1087
1088/********** allow another TX thread to start **********/
1089
1090static inline void tx_release (hrz_dev * dev) {
1091 clear_bit (tx_busy, &dev->flags);
1092 PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev);
1093 wake_up_interruptible (&dev->tx_queue);
1094}
1095
1096/********** schedule TX transfers **********/
1097
1098static void tx_schedule (hrz_dev * const dev, int irq) {
1099 unsigned int tx_bytes;
1100
1101 int append_desc = 0;
1102
1103 int pio_instead = 0;
1104#ifndef TAILRECURSIONWORKS
1105 pio_instead = 1;
1106 while (pio_instead) {
1107#endif
1108 // bytes in current region waiting for TX transfer
1109 tx_bytes = dev->tx_bytes;
1110
1111#if 0
1112 spin_count = 0;
1113 while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) {
1114 PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!");
1115 if (++spin_count > 10) {
1116 PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion");
1117 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1118 tx_release (dev);
1119 hrz_kfree_skb (dev->tx_skb);
1120 return;
1121 }
1122 }
1123#endif
1124
1125 if (tx_bytes) {
1126 // start next transfer within same region
1127 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1128 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1129 pio_instead = 1;
1130 }
1131 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1132 PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)");
1133 if (!dev->tx_iovec) {
1134 // end of last region
1135 append_desc = 1;
1136 }
1137 dev->tx_bytes = 0;
1138 } else {
1139 PRINTD (DBG_TX|DBG_BUS, "(continuing multi)");
1140 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1141 tx_bytes = MAX_TRANSFER_COUNT;
1142 }
1143 } else {
1144 // tx_bytes == 0 -- we're between regions
1145 // regions remaining to transfer
1146 unsigned int tx_regions = dev->tx_regions;
1147
1148 if (tx_regions) {
1149 // start a new region
1150 dev->tx_addr = dev->tx_iovec->iov_base;
1151 tx_bytes = dev->tx_iovec->iov_len;
1152 ++dev->tx_iovec;
1153 dev->tx_regions = tx_regions - 1;
1154
1155 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1156 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1157 pio_instead = 1;
1158 }
1159 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1160 PRINTD (DBG_TX|DBG_BUS, "(full region)");
1161 dev->tx_bytes = 0;
1162 } else {
1163 PRINTD (DBG_TX|DBG_BUS, "(start multi region)");
1164 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1165 tx_bytes = MAX_TRANSFER_COUNT;
1166 }
1167 } else {
1168 // tx_regions == 0
1169 // that's all folks - end of frame
1170 struct sk_buff * skb = dev->tx_skb;
1171 dev->tx_iovec = NULL;
1172
1173 // VC layer stats
1174 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
1175
1176 // free the skb
1177 hrz_kfree_skb (skb);
1178 }
1179 }
1180
1181 // note: writing TX_COUNT clears any interrupt condition
1182 if (tx_bytes) {
1183 if (pio_instead) {
1184 if (irq)
1185 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1186 wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes);
1187 if (append_desc)
1188 wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len));
1189 } else {
1190 wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr));
1191 if (append_desc)
1192 wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len));
1193 wr_regl (dev, MASTER_TX_COUNT_REG_OFF,
1194 append_desc
1195 ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC
1196 : tx_bytes);
1197 }
1198 dev->tx_addr += tx_bytes;
1199 } else {
1200 if (irq)
1201 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1202 YELLOW_LED_ON(dev);
1203 tx_release (dev);
1204 }
1205
1206#ifdef TAILRECURSIONWORKS
1207 // and we all bless optimised tail calls
1208 if (pio_instead)
1209 return tx_schedule (dev, 0);
1210 return;
1211#else
1212 // grrrrrrr!
1213 irq = 0;
1214 }
1215 return;
1216#endif
1217}
1218
1219/********** handle TX bus master complete events **********/
1220
1221static void tx_bus_master_complete_handler (hrz_dev * dev) {
1222 if (test_bit (tx_busy, &dev->flags)) {
1223 tx_schedule (dev, 1);
1224 } else {
1225 PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion");
1226 // clear interrupt condition on adapter
1227 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1228 }
1229 return;
1230}
1231
1232/********** move RX Q pointer to next item in circular buffer **********/
1233
1234// called only from IRQ sub-handler
1235static u32 rx_queue_entry_next (hrz_dev * dev) {
1236 u32 rx_queue_entry;
1237 spin_lock (&dev->mem_lock);
1238 rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry);
1239 if (dev->rx_q_entry == dev->rx_q_wrap)
1240 dev->rx_q_entry = dev->rx_q_reset;
1241 else
1242 dev->rx_q_entry++;
1243 wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset);
1244 spin_unlock (&dev->mem_lock);
1245 return rx_queue_entry;
1246}
1247
1248/********** handle RX data received by device **********/
1249
1250// called from IRQ handler
1251static void rx_data_av_handler (hrz_dev * dev) {
1252 u32 rx_queue_entry;
1253 u32 rx_queue_entry_flags;
1254 u16 rx_len;
1255 u16 rx_channel;
1256
1257 PRINTD (DBG_FLOW, "hrz_data_av_handler");
1258
1259 // try to grab rx lock (not possible during RX bus mastering)
1260 if (test_and_set_bit (rx_busy, &dev->flags)) {
1261 PRINTD (DBG_RX, "locked out of rx lock");
1262 return;
1263 }
1264 PRINTD (DBG_RX, "set rx_busy for dev %p", dev);
1265 // lock is cleared if we fail now, o/w after bus master completion
1266
1267 YELLOW_LED_OFF(dev);
1268
1269 rx_queue_entry = rx_queue_entry_next (dev);
1270
1271 rx_len = rx_q_entry_to_length (rx_queue_entry);
1272 rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry);
1273
1274 WAIT_FLUSH_RX_COMPLETE (dev);
1275
1276 SELECT_RX_CHANNEL (dev, rx_channel);
1277
1278 PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry);
1279 rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER);
1280
1281 if (!rx_len) {
1282 // (at least) bus-mastering breaks if we try to handle a
1283 // zero-length frame, besides AAL5 does not support them
1284 PRINTK (KERN_ERR, "zero-length frame!");
1285 rx_queue_entry_flags &= ~RX_COMPLETE_FRAME;
1286 }
1287
1288 if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) {
1289 PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!");
1290 }
1291 if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) {
1292 struct atm_vcc * atm_vcc;
1293
1294 PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len);
1295
1296 atm_vcc = dev->rxer[rx_channel];
1297 // if no vcc is assigned to this channel, we should drop the frame
1298 // (is this what SIMONS etc. was trying to achieve?)
1299
1300 if (atm_vcc) {
1301
1302 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
1303
1304 if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
1305
1306 struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC);
1307 if (skb) {
1308 // remember this so we can push it later
1309 dev->rx_skb = skb;
1310 // remember this so we can flush it later
1311 dev->rx_channel = rx_channel;
1312
1313 // prepare socket buffer
1314 skb_put (skb, rx_len);
1315 ATM_SKB(skb)->vcc = atm_vcc;
1316
1317 // simple transfer
1318 // dev->rx_regions = 0;
1319 // dev->rx_iovec = 0;
1320 dev->rx_bytes = rx_len;
1321 dev->rx_addr = skb->data;
1322 PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)",
1323 skb->data, rx_len);
1324
1325 // do the business
1326 rx_schedule (dev, 0);
1327 return;
1328
1329 } else {
1330 PRINTD (DBG_SKB|DBG_WARN, "failed to get skb");
1331 }
1332
1333 } else {
1334 PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel);
1335 // do we count this?
1336 }
1337
1338 } else {
1339 PRINTK (KERN_WARNING, "dropped over-size frame");
1340 // do we count this?
1341 }
1342
1343 } else {
1344 PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)");
1345 // do we count this?
1346 }
1347
1348 } else {
1349 // Wait update complete ? SPONG
1350 }
1351
1352 // RX was aborted
1353 YELLOW_LED_ON(dev);
1354
1355 FLUSH_RX_CHANNEL (dev,rx_channel);
1356 clear_bit (rx_busy, &dev->flags);
1357
1358 return;
1359}
1360
1361/********** interrupt handler **********/
1362
1363static irqreturn_t interrupt_handler(int irq, void *dev_id)
1364{
1365 hrz_dev *dev = dev_id;
1366 u32 int_source;
1367 unsigned int irq_ok;
1368
1369 PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id);
1370
1371 // definitely for us
1372 irq_ok = 0;
1373 while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF)
1374 & INTERESTING_INTERRUPTS)) {
1375 // In the interests of fairness, the handlers below are
1376 // called in sequence and without immediate return to the head of
1377 // the while loop. This is only of issue for slow hosts (or when
1378 // debugging messages are on). Really slow hosts may find a fast
1379 // sender keeps them permanently in the IRQ handler. :(
1380
1381 // (only an issue for slow hosts) RX completion goes before
1382 // rx_data_av as the former implies rx_busy and so the latter
1383 // would just abort. If it reschedules another transfer
1384 // (continuing the same frame) then it will not clear rx_busy.
1385
1386 // (only an issue for slow hosts) TX completion goes before RX
1387 // data available as it is a much shorter routine - there is the
1388 // chance that any further transfers it schedules will be complete
1389 // by the time of the return to the head of the while loop
1390
1391 if (int_source & RX_BUS_MASTER_COMPLETE) {
1392 ++irq_ok;
1393 PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted");
1394 rx_bus_master_complete_handler (dev);
1395 }
1396 if (int_source & TX_BUS_MASTER_COMPLETE) {
1397 ++irq_ok;
1398 PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted");
1399 tx_bus_master_complete_handler (dev);
1400 }
1401 if (int_source & RX_DATA_AV) {
1402 ++irq_ok;
1403 PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted");
1404 rx_data_av_handler (dev);
1405 }
1406 }
1407 if (irq_ok) {
1408 PRINTD (DBG_IRQ, "work done: %u", irq_ok);
1409 } else {
1410 PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source);
1411 }
1412
1413 PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
1414 if (irq_ok)
1415 return IRQ_HANDLED;
1416 return IRQ_NONE;
1417}
1418
1419/********** housekeeping **********/
1420
1421static void do_housekeeping (struct timer_list *t) {
1422 // just stats at the moment
1423 hrz_dev * dev = from_timer(dev, t, housekeeping);
1424
1425 // collect device-specific (not driver/atm-linux) stats here
1426 dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);
1427 dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);
1428 dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);
1429 dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);
1430
1431 mod_timer (&dev->housekeeping, jiffies + HZ/10);
1432
1433 return;
1434}
1435
1436/********** find an idle channel for TX and set it up **********/
1437
1438// called with tx_busy set
1439static short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) {
1440 unsigned short idle_channels;
1441 short tx_channel = -1;
1442 unsigned int spin_count;
1443 PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev);
1444
1445 // better would be to fail immediately, the caller can then decide whether
1446 // to wait or drop (depending on whether this is UBR etc.)
1447 spin_count = 0;
1448 while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {
1449 PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel");
1450 // delay a bit here
1451 if (++spin_count > 100) {
1452 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel");
1453 return -EBUSY;
1454 }
1455 }
1456
1457 // got an idle channel
1458 {
1459 // tx_idle ensures we look for idle channels in RR order
1460 int chan = dev->tx_idle;
1461
1462 int keep_going = 1;
1463 while (keep_going) {
1464 if (idle_channels & (1<<chan)) {
1465 tx_channel = chan;
1466 keep_going = 0;
1467 }
1468 ++chan;
1469 if (chan == TX_CHANS)
1470 chan = 0;
1471 }
1472
1473 dev->tx_idle = chan;
1474 }
1475
1476 // set up the channel we found
1477 {
1478 // Initialise the cell header in the transmit channel descriptor
1479 // a.k.a. prepare the channel and remember that we have done so.
1480
1481 tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel];
1482 u32 rd_ptr;
1483 u32 wr_ptr;
1484 u16 channel = vcc->channel;
1485
1486 unsigned long flags;
1487 spin_lock_irqsave (&dev->mem_lock, flags);
1488
1489 // Update the transmit channel record.
1490 dev->tx_channel_record[tx_channel] = channel;
1491
1492 // xBR channel
1493 update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS,
1494 vcc->tx_xbr_bits);
1495
1496 // Update the PCR counter preload value etc.
1497 update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS,
1498 vcc->tx_pcr_bits);
1499
1500#if 0
1501 if (vcc->tx_xbr_bits == VBR_RATE_TYPE) {
1502 // SCR timer
1503 update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS,
1504 vcc->tx_scr_bits);
1505
1506 // Bucket size...
1507 update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS,
1508 vcc->tx_bucket_bits);
1509
1510 // ... and fullness
1511 update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS,
1512 vcc->tx_bucket_bits);
1513 }
1514#endif
1515
1516 // Initialise the read and write buffer pointers
1517 rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK;
1518 wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK;
1519
1520 // idle TX channels should have identical pointers
1521 if (rd_ptr != wr_ptr) {
1522 PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!");
1523 // spin_unlock... return -E...
1524 // I wonder if gcc would get rid of one of the pointer aliases
1525 }
1526 PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.",
1527 rd_ptr, wr_ptr);
1528
1529 switch (vcc->aal) {
1530 case aal0:
1531 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0");
1532 rd_ptr |= CHANNEL_TYPE_RAW_CELLS;
1533 wr_ptr |= CHANNEL_TYPE_RAW_CELLS;
1534 break;
1535 case aal34:
1536 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34");
1537 rd_ptr |= CHANNEL_TYPE_AAL3_4;
1538 wr_ptr |= CHANNEL_TYPE_AAL3_4;
1539 break;
1540 case aal5:
1541 rd_ptr |= CHANNEL_TYPE_AAL5;
1542 wr_ptr |= CHANNEL_TYPE_AAL5;
1543 // Initialise the CRC
1544 wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC);
1545 break;
1546 }
1547
1548 wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr);
1549 wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr);
1550
1551 // Write the Cell Header
1552 // Payload Type, CLP and GFC would go here if non-zero
1553 wr_mem (dev, &tx_desc->cell_header, channel);
1554
1555 spin_unlock_irqrestore (&dev->mem_lock, flags);
1556 }
1557
1558 return tx_channel;
1559}
1560
1561/********** send a frame **********/
1562
1563static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
1564 unsigned int spin_count;
1565 int free_buffers;
1566 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
1567 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
1568 u16 channel = vcc->channel;
1569
1570 u32 buffers_required;
1571
1572 /* signed for error return */
1573 short tx_channel;
1574
1575 PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u",
1576 channel, skb->data, skb->len);
1577
1578 dump_skb (">>>", channel, skb);
1579
1580 if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) {
1581 PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel);
1582 hrz_kfree_skb (skb);
1583 return -EIO;
1584 }
1585
1586 // don't understand this
1587 ATM_SKB(skb)->vcc = atm_vcc;
1588
1589 if (skb->len > atm_vcc->qos.txtp.max_sdu) {
1590 PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
1591 hrz_kfree_skb (skb);
1592 return -EIO;
1593 }
1594
1595 if (!channel) {
1596 PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel");
1597 hrz_kfree_skb (skb);
1598 return -EIO;
1599 }
1600
1601#if 0
1602 {
1603 // where would be a better place for this? housekeeping?
1604 u16 status;
1605 pci_read_config_word (dev->pci_dev, PCI_STATUS, &status);
1606 if (status & PCI_STATUS_REC_MASTER_ABORT) {
1607 PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)");
1608 status &= ~PCI_STATUS_REC_MASTER_ABORT;
1609 pci_write_config_word (dev->pci_dev, PCI_STATUS, status);
1610 if (test_bit (tx_busy, &dev->flags)) {
1611 hrz_kfree_skb (dev->tx_skb);
1612 tx_release (dev);
1613 }
1614 }
1615 }
1616#endif
1617
1618#ifdef DEBUG_HORIZON
1619 /* wey-hey! */
1620 if (channel == 1023) {
1621 unsigned int i;
1622 unsigned short d = 0;
1623 char * s = skb->data;
1624 if (*s++ == 'D') {
1625 for (i = 0; i < 4; ++i)
1626 d = (d << 4) | hex_to_bin(*s++);
1627 PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d);
1628 }
1629 }
1630#endif
1631
1632 // wait until TX is free and grab lock
1633 if (tx_hold (dev)) {
1634 hrz_kfree_skb (skb);
1635 return -ERESTARTSYS;
1636 }
1637
1638 // Wait for enough space to be available in transmit buffer memory.
1639
1640 // should be number of cells needed + 2 (according to hardware docs)
1641 // = ((framelen+8)+47) / 48 + 2
1642 // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
1643 buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3;
1644
1645 // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
1646 spin_count = 0;
1647 while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {
1648 PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d",
1649 free_buffers, buffers_required);
1650 // what is the appropriate delay? implement a timeout? (depending on line speed?)
1651 // mdelay (1);
1652 // what happens if we kill (current_pid, SIGKILL) ?
1653 schedule();
1654 if (++spin_count > 1000) {
1655 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d",
1656 free_buffers, buffers_required);
1657 tx_release (dev);
1658 hrz_kfree_skb (skb);
1659 return -ERESTARTSYS;
1660 }
1661 }
1662
1663 // Select a channel to transmit the frame on.
1664 if (channel == dev->last_vc) {
1665 PRINTD (DBG_TX, "last vc hack: hit");
1666 tx_channel = dev->tx_last;
1667 } else {
1668 PRINTD (DBG_TX, "last vc hack: miss");
1669 // Are we currently transmitting this VC on one of the channels?
1670 for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel)
1671 if (dev->tx_channel_record[tx_channel] == channel) {
1672 PRINTD (DBG_TX, "vc already on channel: hit");
1673 break;
1674 }
1675 if (tx_channel == TX_CHANS) {
1676 PRINTD (DBG_TX, "vc already on channel: miss");
1677 // Find and set up an idle channel.
1678 tx_channel = setup_idle_tx_channel (dev, vcc);
1679 if (tx_channel < 0) {
1680 PRINTD (DBG_TX|DBG_ERR, "failed to get channel");
1681 tx_release (dev);
1682 return tx_channel;
1683 }
1684 }
1685
1686 PRINTD (DBG_TX, "got channel");
1687 SELECT_TX_CHANNEL(dev, tx_channel);
1688
1689 dev->last_vc = channel;
1690 dev->tx_last = tx_channel;
1691 }
1692
1693 PRINTD (DBG_TX, "using channel %u", tx_channel);
1694
1695 YELLOW_LED_OFF(dev);
1696
1697 // TX start transfer
1698
1699 {
1700 unsigned int tx_len = skb->len;
1701 unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags;
1702 // remember this so we can free it later
1703 dev->tx_skb = skb;
1704
1705 if (tx_iovcnt) {
1706 // scatter gather transfer
1707 dev->tx_regions = tx_iovcnt;
1708 dev->tx_iovec = NULL; /* @@@ needs rewritten */
1709 dev->tx_bytes = 0;
1710 PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)",
1711 skb->data, tx_len);
1712 tx_release (dev);
1713 hrz_kfree_skb (skb);
1714 return -EIO;
1715 } else {
1716 // simple transfer
1717 dev->tx_regions = 0;
1718 dev->tx_iovec = NULL;
1719 dev->tx_bytes = tx_len;
1720 dev->tx_addr = skb->data;
1721 PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)",
1722 skb->data, tx_len);
1723 }
1724
1725 // and do the business
1726 tx_schedule (dev, 0);
1727
1728 }
1729
1730 return 0;
1731}
1732
1733/********** reset a card **********/
1734
1735static void hrz_reset (const hrz_dev * dev) {
1736 u32 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1737
1738 // why not set RESET_HORIZON to one and wait for the card to
1739 // reassert that bit as zero? Like so:
1740 control_0_reg = control_0_reg & RESET_HORIZON;
1741 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1742 while (control_0_reg & RESET_HORIZON)
1743 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1744
1745 // old reset code retained:
1746 wr_regl (dev, CONTROL_0_REG, control_0_reg |
1747 RESET_ATM | RESET_RX | RESET_TX | RESET_HOST);
1748 // just guessing here
1749 udelay (1000);
1750
1751 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1752}
1753
1754/********** read the burnt in address **********/
1755
1756static void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl)
1757{
1758 wr_regl (dev, CONTROL_0_REG, ctrl);
1759 udelay (5);
1760}
1761
1762static void CLOCK_IT (const hrz_dev *dev, u32 ctrl)
1763{
1764 // DI must be valid around rising SK edge
1765 WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK);
1766 WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK);
1767}
1768
1769static u16 read_bia(const hrz_dev *dev, u16 addr)
1770{
1771 u32 ctrl = rd_regl (dev, CONTROL_0_REG);
1772
1773 const unsigned int addr_bits = 6;
1774 const unsigned int data_bits = 16;
1775
1776 unsigned int i;
1777
1778 u16 res;
1779
1780 ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI);
1781 WRITE_IT_WAIT(dev, ctrl);
1782
1783 // wake Serial EEPROM and send 110 (READ) command
1784 ctrl |= (SEEPROM_CS | SEEPROM_DI);
1785 CLOCK_IT(dev, ctrl);
1786
1787 ctrl |= SEEPROM_DI;
1788 CLOCK_IT(dev, ctrl);
1789
1790 ctrl &= ~SEEPROM_DI;
1791 CLOCK_IT(dev, ctrl);
1792
1793 for (i=0; i<addr_bits; i++) {
1794 if (addr & (1 << (addr_bits-1)))
1795 ctrl |= SEEPROM_DI;
1796 else
1797 ctrl &= ~SEEPROM_DI;
1798
1799 CLOCK_IT(dev, ctrl);
1800
1801 addr = addr << 1;
1802 }
1803
1804 // we could check that we have DO = 0 here
1805 ctrl &= ~SEEPROM_DI;
1806
1807 res = 0;
1808 for (i=0;i<data_bits;i++) {
1809 res = res >> 1;
1810
1811 CLOCK_IT(dev, ctrl);
1812
1813 if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO)
1814 res |= (1 << (data_bits-1));
1815 }
1816
1817 ctrl &= ~(SEEPROM_SK | SEEPROM_CS);
1818 WRITE_IT_WAIT(dev, ctrl);
1819
1820 return res;
1821}
1822
1823/********** initialise a card **********/
1824
1825static int hrz_init(hrz_dev *dev)
1826{
1827 int onefivefive;
1828
1829 u16 chan;
1830
1831 int buff_count;
1832
1833 HDW * mem;
1834
1835 cell_buf * tx_desc;
1836 cell_buf * rx_desc;
1837
1838 u32 ctrl;
1839
1840 ctrl = rd_regl (dev, CONTROL_0_REG);
1841 PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl);
1842 onefivefive = ctrl & ATM_LAYER_STATUS;
1843
1844 if (onefivefive)
1845 printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)");
1846 else
1847 printk (DEV_LABEL ": Horizon (at 25 MBps)");
1848
1849 printk (":");
1850 // Reset the card to get everything in a known state
1851
1852 printk (" reset");
1853 hrz_reset (dev);
1854
1855 // Clear all the buffer memory
1856
1857 printk (" clearing memory");
1858
1859 for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem)
1860 wr_mem (dev, mem, 0);
1861
1862 printk (" tx channels");
1863
1864 // All transmit eight channels are set up as AAL5 ABR channels with
1865 // a 16us cell spacing. Why?
1866
1867 // Channel 0 gets the free buffer at 100h, channel 1 gets the free
1868 // buffer at 110h etc.
1869
1870 for (chan = 0; chan < TX_CHANS; ++chan) {
1871 tx_ch_desc * tx_desc = &memmap->tx_descs[chan];
1872 cell_buf * buf = &memmap->inittxbufs[chan];
1873
1874 // initialise the read and write buffer pointers
1875 wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf));
1876 wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf));
1877
1878 // set the status of the initial buffers to empty
1879 wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY);
1880 }
1881
1882 // Use space bufn3 at the moment for tx buffers
1883
1884 printk (" tx buffers");
1885
1886 tx_desc = memmap->bufn3;
1887
1888 wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY);
1889
1890 for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) {
1891 wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY);
1892 tx_desc++;
1893 }
1894
1895 wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY);
1896
1897 // Initialise the transmit free buffer count
1898 wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE);
1899
1900 printk (" rx channels");
1901
1902 // Initialise all of the receive channels to be AAL5 disabled with
1903 // an interrupt threshold of 0
1904
1905 for (chan = 0; chan < RX_CHANS; ++chan) {
1906 rx_ch_desc * rx_desc = &memmap->rx_descs[chan];
1907
1908 wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED);
1909 }
1910
1911 printk (" rx buffers");
1912
1913 // Use space bufn4 at the moment for rx buffers
1914
1915 rx_desc = memmap->bufn4;
1916
1917 wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY);
1918
1919 for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) {
1920 wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY);
1921
1922 rx_desc++;
1923 }
1924
1925 wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY);
1926
1927 // Initialise the receive free buffer count
1928 wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE);
1929
1930 // Initialize Horizons registers
1931
1932 // TX config
1933 wr_regw (dev, TX_CONFIG_OFF,
1934 ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE);
1935
1936 // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
1937 wr_regw (dev, RX_CONFIG_OFF,
1938 DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits);
1939
1940 // RX line config
1941 wr_regw (dev, RX_LINE_CONFIG_OFF,
1942 LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4);
1943
1944 // Set the max AAL5 cell count to be just enough to contain the
1945 // largest AAL5 frame that the user wants to receive
1946 wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF,
1947 DIV_ROUND_UP(max_rx_size + ATM_AAL5_TRAILER, ATM_CELL_PAYLOAD));
1948
1949 // Enable receive
1950 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1951
1952 printk (" control");
1953
1954 // Drive the OE of the LEDs then turn the green LED on
1955 ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED;
1956 wr_regl (dev, CONTROL_0_REG, ctrl);
1957
1958 // Test for a 155-capable card
1959
1960 if (onefivefive) {
1961 // Select 155 mode... make this a choice (or: how do we detect
1962 // external line speed and switch?)
1963 ctrl |= ATM_LAYER_SELECT;
1964 wr_regl (dev, CONTROL_0_REG, ctrl);
1965
1966 // test SUNI-lite vs SAMBA
1967
1968 // Register 0x00 in the SUNI will have some of bits 3-7 set, and
1969 // they will always be zero for the SAMBA. Ha! Bloody hardware
1970 // engineers. It'll never work.
1971
1972 if (rd_framer (dev, 0) & 0x00f0) {
1973 // SUNI
1974 printk (" SUNI");
1975
1976 // Reset, just in case
1977 wr_framer (dev, 0x00, 0x0080);
1978 wr_framer (dev, 0x00, 0x0000);
1979
1980 // Configure transmit FIFO
1981 wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002);
1982
1983 // Set line timed mode
1984 wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001);
1985 } else {
1986 // SAMBA
1987 printk (" SAMBA");
1988
1989 // Reset, just in case
1990 wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001);
1991 wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001);
1992
1993 // Turn off diagnostic loopback and enable line-timed mode
1994 wr_framer (dev, 0, 0x0002);
1995
1996 // Turn on transmit outputs
1997 wr_framer (dev, 2, 0x0B80);
1998 }
1999 } else {
2000 // Select 25 mode
2001 ctrl &= ~ATM_LAYER_SELECT;
2002
2003 // Madge B154 setup
2004 // none required?
2005 }
2006
2007 printk (" LEDs");
2008
2009 GREEN_LED_ON(dev);
2010 YELLOW_LED_ON(dev);
2011
2012 printk (" ESI=");
2013
2014 {
2015 u16 b = 0;
2016 int i;
2017 u8 * esi = dev->atm_dev->esi;
2018
2019 // in the card I have, EEPROM
2020 // addresses 0, 1, 2 contain 0
2021 // addresess 5, 6 etc. contain ffff
2022 // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
2023 // the read_bia routine gets the BIA in Ethernet bit order
2024
2025 for (i=0; i < ESI_LEN; ++i) {
2026 if (i % 2 == 0)
2027 b = read_bia (dev, i/2 + 2);
2028 else
2029 b = b >> 8;
2030 esi[i] = b & 0xFF;
2031 printk ("%02x", esi[i]);
2032 }
2033 }
2034
2035 // Enable RX_Q and ?X_COMPLETE interrupts only
2036 wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS);
2037 printk (" IRQ on");
2038
2039 printk (".\n");
2040
2041 return onefivefive;
2042}
2043
2044/********** check max_sdu **********/
2045
2046static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) {
2047 PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu");
2048
2049 switch (aal) {
2050 case aal0:
2051 if (!(tp->max_sdu)) {
2052 PRINTD (DBG_QOS, "defaulting max_sdu");
2053 tp->max_sdu = ATM_AAL0_SDU;
2054 } else if (tp->max_sdu != ATM_AAL0_SDU) {
2055 PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu");
2056 return -EINVAL;
2057 }
2058 break;
2059 case aal34:
2060 if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) {
2061 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2062 tp->max_sdu = ATM_MAX_AAL34_PDU;
2063 }
2064 break;
2065 case aal5:
2066 if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) {
2067 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2068 tp->max_sdu = max_frame_size;
2069 }
2070 break;
2071 }
2072 return 0;
2073}
2074
2075/********** check pcr **********/
2076
2077// something like this should be part of ATM Linux
2078static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) {
2079 // we are assuming non-UBR, and non-special values of pcr
2080 if (tp->min_pcr == ATM_MAX_PCR)
2081 PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR");
2082 else if (tp->min_pcr < 0)
2083 PRINTD (DBG_QOS, "luser gave negative min_pcr");
2084 else if (tp->min_pcr && tp->min_pcr > pcr)
2085 PRINTD (DBG_QOS, "pcr less than min_pcr");
2086 else
2087 // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
2088 // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
2089 // [this would get rid of next two conditionals]
2090 if ((0) && tp->max_pcr == ATM_MAX_PCR)
2091 PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR");
2092 else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0)
2093 PRINTD (DBG_QOS, "luser gave negative max_pcr");
2094 else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr)
2095 PRINTD (DBG_QOS, "pcr greater than max_pcr");
2096 else {
2097 // each limit unspecified or not violated
2098 PRINTD (DBG_QOS, "xBR(pcr) OK");
2099 return 0;
2100 }
2101 PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
2102 pcr, tp->min_pcr, tp->pcr, tp->max_pcr);
2103 return -EINVAL;
2104}
2105
2106/********** open VC **********/
2107
2108static int hrz_open (struct atm_vcc *atm_vcc)
2109{
2110 int error;
2111 u16 channel;
2112
2113 struct atm_qos * qos;
2114 struct atm_trafprm * txtp;
2115 struct atm_trafprm * rxtp;
2116
2117 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2118 hrz_vcc vcc;
2119 hrz_vcc * vccp; // allocated late
2120 short vpi = atm_vcc->vpi;
2121 int vci = atm_vcc->vci;
2122 PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci);
2123
2124#ifdef ATM_VPI_UNSPEC
2125 // UNSPEC is deprecated, remove this code eventually
2126 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
2127 PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
2128 return -EINVAL;
2129 }
2130#endif
2131
2132 error = vpivci_to_channel (&channel, vpi, vci);
2133 if (error) {
2134 PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
2135 return error;
2136 }
2137
2138 vcc.channel = channel;
2139 // max speed for the moment
2140 vcc.tx_rate = 0x0;
2141
2142 qos = &atm_vcc->qos;
2143
2144 // check AAL and remember it
2145 switch (qos->aal) {
2146 case ATM_AAL0:
2147 // we would if it were 48 bytes and not 52!
2148 PRINTD (DBG_QOS|DBG_VCC, "AAL0");
2149 vcc.aal = aal0;
2150 break;
2151 case ATM_AAL34:
2152 // we would if I knew how do the SAR!
2153 PRINTD (DBG_QOS|DBG_VCC, "AAL3/4");
2154 vcc.aal = aal34;
2155 break;
2156 case ATM_AAL5:
2157 PRINTD (DBG_QOS|DBG_VCC, "AAL5");
2158 vcc.aal = aal5;
2159 break;
2160 default:
2161 PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!");
2162 return -EINVAL;
2163 }
2164
2165 // TX traffic parameters
2166
2167 // there are two, interrelated problems here: 1. the reservation of
2168 // PCR is not a binary choice, we are given bounds and/or a
2169 // desirable value; 2. the device is only capable of certain values,
2170 // most of which are not integers. It is almost certainly acceptable
2171 // to be off by a maximum of 1 to 10 cps.
2172
2173 // Pragmatic choice: always store an integral PCR as that which has
2174 // been allocated, even if we allocate a little (or a lot) less,
2175 // after rounding. The actual allocation depends on what we can
2176 // manage with our rate selection algorithm. The rate selection
2177 // algorithm is given an integral PCR and a tolerance and told
2178 // whether it should round the value up or down if the tolerance is
2179 // exceeded; it returns: a) the actual rate selected (rounded up to
2180 // the nearest integer), b) a bit pattern to feed to the timer
2181 // register, and c) a failure value if no applicable rate exists.
2182
2183 // Part of the job is done by atm_pcr_goal which gives us a PCR
2184 // specification which says: EITHER grab the maximum available PCR
2185 // (and perhaps a lower bound which we musn't pass), OR grab this
2186 // amount, rounding down if you have to (and perhaps a lower bound
2187 // which we musn't pass) OR grab this amount, rounding up if you
2188 // have to (and perhaps an upper bound which we musn't pass). If any
2189 // bounds ARE passed we fail. Note that rounding is only rounding to
2190 // match device limitations, we do not round down to satisfy
2191 // bandwidth availability even if this would not violate any given
2192 // lower bound.
2193
2194 // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
2195 // (say) so this is not even a binary fixpoint cell rate (but this
2196 // device can do it). To avoid this sort of hassle we use a
2197 // tolerance parameter (currently fixed at 10 cps).
2198
2199 PRINTD (DBG_QOS, "TX:");
2200
2201 txtp = &qos->txtp;
2202
2203 // set up defaults for no traffic
2204 vcc.tx_rate = 0;
2205 // who knows what would actually happen if you try and send on this?
2206 vcc.tx_xbr_bits = IDLE_RATE_TYPE;
2207 vcc.tx_pcr_bits = CLOCK_DISABLE;
2208#if 0
2209 vcc.tx_scr_bits = CLOCK_DISABLE;
2210 vcc.tx_bucket_bits = 0;
2211#endif
2212
2213 if (txtp->traffic_class != ATM_NONE) {
2214 error = check_max_sdu (vcc.aal, txtp, max_tx_size);
2215 if (error) {
2216 PRINTD (DBG_QOS, "TX max_sdu check failed");
2217 return error;
2218 }
2219
2220 switch (txtp->traffic_class) {
2221 case ATM_UBR: {
2222 // we take "the PCR" as a rate-cap
2223 // not reserved
2224 vcc.tx_rate = 0;
2225 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL);
2226 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2227 break;
2228 }
2229#if 0
2230 case ATM_ABR: {
2231 // reserve min, allow up to max
2232 vcc.tx_rate = 0; // ?
2233 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
2234 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2235 break;
2236 }
2237#endif
2238 case ATM_CBR: {
2239 int pcr = atm_pcr_goal (txtp);
2240 rounding r;
2241 if (!pcr) {
2242 // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
2243 // should really have: once someone gets unlimited bandwidth
2244 // that no more non-UBR channels can be opened until the
2245 // unlimited one closes?? For the moment, round_down means
2246 // greedy people actually get something and not nothing
2247 r = round_down;
2248 // slight race (no locking) here so we may get -EAGAIN
2249 // later; the greedy bastards would deserve it :)
2250 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2251 pcr = dev->tx_avail;
2252 } else if (pcr < 0) {
2253 r = round_down;
2254 pcr = -pcr;
2255 } else {
2256 r = round_up;
2257 }
2258 error = make_rate_with_tolerance (dev, pcr, r, 10,
2259 &vcc.tx_pcr_bits, &vcc.tx_rate);
2260 if (error) {
2261 PRINTD (DBG_QOS, "could not make rate from TX PCR");
2262 return error;
2263 }
2264 // not really clear what further checking is needed
2265 error = atm_pcr_check (txtp, vcc.tx_rate);
2266 if (error) {
2267 PRINTD (DBG_QOS, "TX PCR failed consistency check");
2268 return error;
2269 }
2270 vcc.tx_xbr_bits = CBR_RATE_TYPE;
2271 break;
2272 }
2273#if 0
2274 case ATM_VBR: {
2275 int pcr = atm_pcr_goal (txtp);
2276 // int scr = atm_scr_goal (txtp);
2277 int scr = pcr/2; // just for fun
2278 unsigned int mbs = 60; // just for fun
2279 rounding pr;
2280 rounding sr;
2281 unsigned int bucket;
2282 if (!pcr) {
2283 pr = round_nearest;
2284 pcr = 1<<30;
2285 } else if (pcr < 0) {
2286 pr = round_down;
2287 pcr = -pcr;
2288 } else {
2289 pr = round_up;
2290 }
2291 error = make_rate_with_tolerance (dev, pcr, pr, 10,
2292 &vcc.tx_pcr_bits, 0);
2293 if (!scr) {
2294 // see comments for PCR with CBR above
2295 sr = round_down;
2296 // slight race (no locking) here so we may get -EAGAIN
2297 // later; the greedy bastards would deserve it :)
2298 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2299 scr = dev->tx_avail;
2300 } else if (scr < 0) {
2301 sr = round_down;
2302 scr = -scr;
2303 } else {
2304 sr = round_up;
2305 }
2306 error = make_rate_with_tolerance (dev, scr, sr, 10,
2307 &vcc.tx_scr_bits, &vcc.tx_rate);
2308 if (error) {
2309 PRINTD (DBG_QOS, "could not make rate from TX SCR");
2310 return error;
2311 }
2312 // not really clear what further checking is needed
2313 // error = atm_scr_check (txtp, vcc.tx_rate);
2314 if (error) {
2315 PRINTD (DBG_QOS, "TX SCR failed consistency check");
2316 return error;
2317 }
2318 // bucket calculations (from a piece of paper...) cell bucket
2319 // capacity must be largest integer smaller than m(p-s)/p + 1
2320 // where m = max burst size, p = pcr, s = scr
2321 bucket = mbs*(pcr-scr)/pcr;
2322 if (bucket*pcr != mbs*(pcr-scr))
2323 bucket += 1;
2324 if (bucket > BUCKET_MAX_SIZE) {
2325 PRINTD (DBG_QOS, "shrinking bucket from %u to %u",
2326 bucket, BUCKET_MAX_SIZE);
2327 bucket = BUCKET_MAX_SIZE;
2328 }
2329 vcc.tx_xbr_bits = VBR_RATE_TYPE;
2330 vcc.tx_bucket_bits = bucket;
2331 break;
2332 }
2333#endif
2334 default: {
2335 PRINTD (DBG_QOS, "unsupported TX traffic class");
2336 return -EINVAL;
2337 }
2338 }
2339 }
2340
2341 // RX traffic parameters
2342
2343 PRINTD (DBG_QOS, "RX:");
2344
2345 rxtp = &qos->rxtp;
2346
2347 // set up defaults for no traffic
2348 vcc.rx_rate = 0;
2349
2350 if (rxtp->traffic_class != ATM_NONE) {
2351 error = check_max_sdu (vcc.aal, rxtp, max_rx_size);
2352 if (error) {
2353 PRINTD (DBG_QOS, "RX max_sdu check failed");
2354 return error;
2355 }
2356 switch (rxtp->traffic_class) {
2357 case ATM_UBR: {
2358 // not reserved
2359 break;
2360 }
2361#if 0
2362 case ATM_ABR: {
2363 // reserve min
2364 vcc.rx_rate = 0; // ?
2365 break;
2366 }
2367#endif
2368 case ATM_CBR: {
2369 int pcr = atm_pcr_goal (rxtp);
2370 if (!pcr) {
2371 // slight race (no locking) here so we may get -EAGAIN
2372 // later; the greedy bastards would deserve it :)
2373 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2374 pcr = dev->rx_avail;
2375 } else if (pcr < 0) {
2376 pcr = -pcr;
2377 }
2378 vcc.rx_rate = pcr;
2379 // not really clear what further checking is needed
2380 error = atm_pcr_check (rxtp, vcc.rx_rate);
2381 if (error) {
2382 PRINTD (DBG_QOS, "RX PCR failed consistency check");
2383 return error;
2384 }
2385 break;
2386 }
2387#if 0
2388 case ATM_VBR: {
2389 // int scr = atm_scr_goal (rxtp);
2390 int scr = 1<<16; // just for fun
2391 if (!scr) {
2392 // slight race (no locking) here so we may get -EAGAIN
2393 // later; the greedy bastards would deserve it :)
2394 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2395 scr = dev->rx_avail;
2396 } else if (scr < 0) {
2397 scr = -scr;
2398 }
2399 vcc.rx_rate = scr;
2400 // not really clear what further checking is needed
2401 // error = atm_scr_check (rxtp, vcc.rx_rate);
2402 if (error) {
2403 PRINTD (DBG_QOS, "RX SCR failed consistency check");
2404 return error;
2405 }
2406 break;
2407 }
2408#endif
2409 default: {
2410 PRINTD (DBG_QOS, "unsupported RX traffic class");
2411 return -EINVAL;
2412 }
2413 }
2414 }
2415
2416
2417 // late abort useful for diagnostics
2418 if (vcc.aal != aal5) {
2419 PRINTD (DBG_QOS, "AAL not supported");
2420 return -EINVAL;
2421 }
2422
2423 // get space for our vcc stuff and copy parameters into it
2424 vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL);
2425 if (!vccp) {
2426 PRINTK (KERN_ERR, "out of memory!");
2427 return -ENOMEM;
2428 }
2429 *vccp = vcc;
2430
2431 // clear error and grab cell rate resource lock
2432 error = 0;
2433 spin_lock (&dev->rate_lock);
2434
2435 if (vcc.tx_rate > dev->tx_avail) {
2436 PRINTD (DBG_QOS, "not enough TX PCR left");
2437 error = -EAGAIN;
2438 }
2439
2440 if (vcc.rx_rate > dev->rx_avail) {
2441 PRINTD (DBG_QOS, "not enough RX PCR left");
2442 error = -EAGAIN;
2443 }
2444
2445 if (!error) {
2446 // really consume cell rates
2447 dev->tx_avail -= vcc.tx_rate;
2448 dev->rx_avail -= vcc.rx_rate;
2449 PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR",
2450 vcc.tx_rate, vcc.rx_rate);
2451 }
2452
2453 // release lock and exit on error
2454 spin_unlock (&dev->rate_lock);
2455 if (error) {
2456 PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources");
2457 kfree (vccp);
2458 return error;
2459 }
2460
2461 // this is "immediately before allocating the connection identifier
2462 // in hardware" - so long as the next call does not fail :)
2463 set_bit(ATM_VF_ADDR,&atm_vcc->flags);
2464
2465 // any errors here are very serious and should never occur
2466
2467 if (rxtp->traffic_class != ATM_NONE) {
2468 if (dev->rxer[channel]) {
2469 PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX");
2470 error = -EBUSY;
2471 }
2472 if (!error)
2473 error = hrz_open_rx (dev, channel);
2474 if (error) {
2475 kfree (vccp);
2476 return error;
2477 }
2478 // this link allows RX frames through
2479 dev->rxer[channel] = atm_vcc;
2480 }
2481
2482 // success, set elements of atm_vcc
2483 atm_vcc->dev_data = (void *) vccp;
2484
2485 // indicate readiness
2486 set_bit(ATM_VF_READY,&atm_vcc->flags);
2487
2488 return 0;
2489}
2490
2491/********** close VC **********/
2492
2493static void hrz_close (struct atm_vcc * atm_vcc) {
2494 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2495 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
2496 u16 channel = vcc->channel;
2497 PRINTD (DBG_VCC|DBG_FLOW, "hrz_close");
2498
2499 // indicate unreadiness
2500 clear_bit(ATM_VF_READY,&atm_vcc->flags);
2501
2502 if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
2503 unsigned int i;
2504
2505 // let any TX on this channel that has started complete
2506 // no restart, just keep trying
2507 while (tx_hold (dev))
2508 ;
2509 // remove record of any tx_channel having been setup for this channel
2510 for (i = 0; i < TX_CHANS; ++i)
2511 if (dev->tx_channel_record[i] == channel) {
2512 dev->tx_channel_record[i] = -1;
2513 break;
2514 }
2515 if (dev->last_vc == channel)
2516 dev->tx_last = -1;
2517 tx_release (dev);
2518 }
2519
2520 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
2521 // disable RXing - it tries quite hard
2522 hrz_close_rx (dev, channel);
2523 // forget the vcc - no more skbs will be pushed
2524 if (atm_vcc != dev->rxer[channel])
2525 PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p",
2526 "arghhh! we're going to die!",
2527 atm_vcc, dev->rxer[channel]);
2528 dev->rxer[channel] = NULL;
2529 }
2530
2531 // atomically release our rate reservation
2532 spin_lock (&dev->rate_lock);
2533 PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR",
2534 vcc->tx_rate, vcc->rx_rate);
2535 dev->tx_avail += vcc->tx_rate;
2536 dev->rx_avail += vcc->rx_rate;
2537 spin_unlock (&dev->rate_lock);
2538
2539 // free our structure
2540 kfree (vcc);
2541 // say the VPI/VCI is free again
2542 clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
2543}
2544
2545#if 0
2546static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2547 void *optval, int optlen) {
2548 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2549 PRINTD (DBG_FLOW|DBG_VCC, "hrz_getsockopt");
2550 switch (level) {
2551 case SOL_SOCKET:
2552 switch (optname) {
2553// case SO_BCTXOPT:
2554// break;
2555// case SO_BCRXOPT:
2556// break;
2557 default:
2558 return -ENOPROTOOPT;
2559 };
2560 break;
2561 }
2562 return -EINVAL;
2563}
2564
2565static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2566 void *optval, unsigned int optlen) {
2567 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2568 PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt");
2569 switch (level) {
2570 case SOL_SOCKET:
2571 switch (optname) {
2572// case SO_BCTXOPT:
2573// break;
2574// case SO_BCRXOPT:
2575// break;
2576 default:
2577 return -ENOPROTOOPT;
2578 };
2579 break;
2580 }
2581 return -EINVAL;
2582}
2583#endif
2584
2585#if 0
2586static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) {
2587 hrz_dev * dev = HRZ_DEV(atm_dev);
2588 PRINTD (DBG_FLOW, "hrz_ioctl");
2589 return -1;
2590}
2591
2592unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) {
2593 hrz_dev * dev = HRZ_DEV(atm_dev);
2594 PRINTD (DBG_FLOW, "hrz_phy_get");
2595 return 0;
2596}
2597
2598static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value,
2599 unsigned long addr) {
2600 hrz_dev * dev = HRZ_DEV(atm_dev);
2601 PRINTD (DBG_FLOW, "hrz_phy_put");
2602}
2603
2604static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) {
2605 hrz_dev * dev = HRZ_DEV(vcc->dev);
2606 PRINTD (DBG_FLOW, "hrz_change_qos");
2607 return -1;
2608}
2609#endif
2610
2611/********** proc file contents **********/
2612
2613static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
2614 hrz_dev * dev = HRZ_DEV(atm_dev);
2615 int left = *pos;
2616 PRINTD (DBG_FLOW, "hrz_proc_read");
2617
2618 /* more diagnostics here? */
2619
2620#if 0
2621 if (!left--) {
2622 unsigned int count = sprintf (page, "vbr buckets:");
2623 unsigned int i;
2624 for (i = 0; i < TX_CHANS; ++i)
2625 count += sprintf (page, " %u/%u",
2626 query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS),
2627 query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS));
2628 count += sprintf (page+count, ".\n");
2629 return count;
2630 }
2631#endif
2632
2633 if (!left--)
2634 return sprintf (page,
2635 "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
2636 dev->tx_cell_count, dev->rx_cell_count,
2637 dev->hec_error_count, dev->unassigned_cell_count);
2638
2639 if (!left--)
2640 return sprintf (page,
2641 "free cell buffers: TX %hu, RX %hu+%hu.\n",
2642 rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),
2643 rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),
2644 dev->noof_spare_buffers);
2645
2646 if (!left--)
2647 return sprintf (page,
2648 "cps remaining: TX %u, RX %u\n",
2649 dev->tx_avail, dev->rx_avail);
2650
2651 return 0;
2652}
2653
2654static const struct atmdev_ops hrz_ops = {
2655 .open = hrz_open,
2656 .close = hrz_close,
2657 .send = hrz_send,
2658 .proc_read = hrz_proc_read,
2659 .owner = THIS_MODULE,
2660};
2661
2662static int hrz_probe(struct pci_dev *pci_dev,
2663 const struct pci_device_id *pci_ent)
2664{
2665 hrz_dev * dev;
2666 int err = 0;
2667
2668 // adapter slot free, read resources from PCI configuration space
2669 u32 iobase = pci_resource_start (pci_dev, 0);
2670 u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1));
2671 unsigned int irq;
2672 unsigned char lat;
2673
2674 PRINTD (DBG_FLOW, "hrz_probe");
2675
2676 if (pci_enable_device(pci_dev))
2677 return -EINVAL;
2678
2679 /* XXX DEV_LABEL is a guess */
2680 if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL)) {
2681 err = -EINVAL;
2682 goto out_disable;
2683 }
2684
2685 dev = kzalloc(sizeof(hrz_dev), GFP_KERNEL);
2686 if (!dev) {
2687 // perhaps we should be nice: deregister all adapters and abort?
2688 PRINTD(DBG_ERR, "out of memory");
2689 err = -ENOMEM;
2690 goto out_release;
2691 }
2692
2693 pci_set_drvdata(pci_dev, dev);
2694
2695 // grab IRQ and install handler - move this someplace more sensible
2696 irq = pci_dev->irq;
2697 if (request_irq(irq,
2698 interrupt_handler,
2699 IRQF_SHARED, /* irqflags guess */
2700 DEV_LABEL, /* name guess */
2701 dev)) {
2702 PRINTD(DBG_WARN, "request IRQ failed!");
2703 err = -EINVAL;
2704 goto out_free;
2705 }
2706
2707 PRINTD(DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
2708 iobase, irq, membase);
2709
2710 dev->atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &hrz_ops, -1,
2711 NULL);
2712 if (!(dev->atm_dev)) {
2713 PRINTD(DBG_ERR, "failed to register Madge ATM adapter");
2714 err = -EINVAL;
2715 goto out_free_irq;
2716 }
2717
2718 PRINTD(DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
2719 dev->atm_dev->number, dev, dev->atm_dev);
2720 dev->atm_dev->dev_data = (void *) dev;
2721 dev->pci_dev = pci_dev;
2722
2723 // enable bus master accesses
2724 pci_set_master(pci_dev);
2725
2726 // frobnicate latency (upwards, usually)
2727 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &lat);
2728 if (pci_lat) {
2729 PRINTD(DBG_INFO, "%s PCI latency timer from %hu to %hu",
2730 "changing", lat, pci_lat);
2731 pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat);
2732 } else if (lat < MIN_PCI_LATENCY) {
2733 PRINTK(KERN_INFO, "%s PCI latency timer from %hu to %hu",
2734 "increasing", lat, MIN_PCI_LATENCY);
2735 pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY);
2736 }
2737
2738 dev->iobase = iobase;
2739 dev->irq = irq;
2740 dev->membase = membase;
2741
2742 dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0];
2743 dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1];
2744
2745 // these next three are performance hacks
2746 dev->last_vc = -1;
2747 dev->tx_last = -1;
2748 dev->tx_idle = 0;
2749
2750 dev->tx_regions = 0;
2751 dev->tx_bytes = 0;
2752 dev->tx_skb = NULL;
2753 dev->tx_iovec = NULL;
2754
2755 dev->tx_cell_count = 0;
2756 dev->rx_cell_count = 0;
2757 dev->hec_error_count = 0;
2758 dev->unassigned_cell_count = 0;
2759
2760 dev->noof_spare_buffers = 0;
2761
2762 {
2763 unsigned int i;
2764 for (i = 0; i < TX_CHANS; ++i)
2765 dev->tx_channel_record[i] = -1;
2766 }
2767
2768 dev->flags = 0;
2769
2770 // Allocate cell rates and remember ASIC version
2771 // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2772 // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
2773 // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
2774
2775 if (hrz_init(dev)) {
2776 // to be really pedantic, this should be ATM_OC3c_PCR
2777 dev->tx_avail = ATM_OC3_PCR;
2778 dev->rx_avail = ATM_OC3_PCR;
2779 set_bit(ultra, &dev->flags); // NOT "|= ultra" !
2780 } else {
2781 dev->tx_avail = ((25600000/8)*26)/(27*53);
2782 dev->rx_avail = ((25600000/8)*26)/(27*53);
2783 PRINTD(DBG_WARN, "Buggy ASIC: no TX bus-mastering.");
2784 }
2785
2786 // rate changes spinlock
2787 spin_lock_init(&dev->rate_lock);
2788
2789 // on-board memory access spinlock; we want atomic reads and
2790 // writes to adapter memory (handles IRQ and SMP)
2791 spin_lock_init(&dev->mem_lock);
2792
2793 init_waitqueue_head(&dev->tx_queue);
2794
2795 // vpi in 0..4, vci in 6..10
2796 dev->atm_dev->ci_range.vpi_bits = vpi_bits;
2797 dev->atm_dev->ci_range.vci_bits = 10-vpi_bits;
2798
2799 timer_setup(&dev->housekeeping, do_housekeeping, 0);
2800 mod_timer(&dev->housekeeping, jiffies);
2801
2802out:
2803 return err;
2804
2805out_free_irq:
2806 free_irq(irq, dev);
2807out_free:
2808 kfree(dev);
2809out_release:
2810 release_region(iobase, HRZ_IO_EXTENT);
2811out_disable:
2812 pci_disable_device(pci_dev);
2813 goto out;
2814}
2815
2816static void hrz_remove_one(struct pci_dev *pci_dev)
2817{
2818 hrz_dev *dev;
2819
2820 dev = pci_get_drvdata(pci_dev);
2821
2822 PRINTD(DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
2823 del_timer_sync(&dev->housekeeping);
2824 hrz_reset(dev);
2825 atm_dev_deregister(dev->atm_dev);
2826 free_irq(dev->irq, dev);
2827 release_region(dev->iobase, HRZ_IO_EXTENT);
2828 kfree(dev);
2829
2830 pci_disable_device(pci_dev);
2831}
2832
2833static void __init hrz_check_args (void) {
2834#ifdef DEBUG_HORIZON
2835 PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
2836#else
2837 if (debug)
2838 PRINTK (KERN_NOTICE, "no debug support in this image");
2839#endif
2840
2841 if (vpi_bits > HRZ_MAX_VPI)
2842 PRINTK (KERN_ERR, "vpi_bits has been limited to %hu",
2843 vpi_bits = HRZ_MAX_VPI);
2844
2845 if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT)
2846 PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu",
2847 max_tx_size = TX_AAL5_LIMIT);
2848
2849 if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT)
2850 PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu",
2851 max_rx_size = RX_AAL5_LIMIT);
2852
2853 return;
2854}
2855
2856MODULE_AUTHOR(maintainer_string);
2857MODULE_DESCRIPTION(description_string);
2858MODULE_LICENSE("GPL");
2859module_param(debug, ushort, 0644);
2860module_param(vpi_bits, ushort, 0);
2861module_param(max_tx_size, int, 0);
2862module_param(max_rx_size, int, 0);
2863module_param(pci_lat, byte, 0);
2864MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
2865MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs");
2866MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames");
2867MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames");
2868MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
2869
2870static const struct pci_device_id hrz_pci_tbl[] = {
2871 { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, PCI_ANY_ID, PCI_ANY_ID,
2872 0, 0, 0 },
2873 { 0, }
2874};
2875
2876MODULE_DEVICE_TABLE(pci, hrz_pci_tbl);
2877
2878static struct pci_driver hrz_driver = {
2879 .name = "horizon",
2880 .probe = hrz_probe,
2881 .remove = hrz_remove_one,
2882 .id_table = hrz_pci_tbl,
2883};
2884
2885/********** module entry **********/
2886
2887static int __init hrz_module_init (void) {
2888 BUILD_BUG_ON(sizeof(struct MEMMAP) != 128*1024/4);
2889
2890 show_version();
2891
2892 // check arguments
2893 hrz_check_args();
2894
2895 // get the juice
2896 return pci_register_driver(&hrz_driver);
2897}
2898
2899/********** module exit **********/
2900
2901static void __exit hrz_module_exit (void) {
2902 PRINTD (DBG_FLOW, "cleanup_module");
2903
2904 pci_unregister_driver(&hrz_driver);
2905}
2906
2907module_init(hrz_module_init);
2908module_exit(hrz_module_exit);
2909