1/******************************************************************************
2 Device driver for Interphase ATM PCI adapter cards
3 Author: Peter Wang <pwang@iphase.com>
4 Interphase Corporation <www.iphase.com>
5 Version: 1.0
6 iphase.h: This is the header file for iphase.c.
7*******************************************************************************
8
9 This software may be used and distributed according to the terms
10 of the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on this skeleton fall under the GPL and must retain
12 the authorship (implicit copyright) notice.
13
14 This program is distributed in the hope that it will be useful, but
15 WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 General Public License for more details.
18
19 Modified from an incomplete driver for Interphase 5575 1KVC 1M card which
20 was originally written by Monalisa Agrawal at UNH. Now this driver
21 supports a variety of varients of Interphase ATM PCI (i)Chip adapter
22 card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM)
23 in terms of PHY type, the size of control memory and the size of
24 packet memory. The following are the change log and history:
25
26 Bugfix the Mona's UBR driver.
27 Modify the basic memory allocation and dma logic.
28 Port the driver to the latest kernel from 2.0.46.
29 Complete the ABR logic of the driver, and added the ABR work-
30 around for the hardware anormalies.
31 Add the CBR support.
32 Add the flow control logic to the driver to allow rate-limit VC.
33 Add 4K VC support to the board with 512K control memory.
34 Add the support of all the variants of the Interphase ATM PCI
35 (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
36 (25M UTP25) and x531 (DS3 and E3).
37 Add SMP support.
38
39 Support and updates available at: ftp://ftp.iphase.com/pub/atm
40
41*******************************************************************************/
42
43#ifndef IPHASE_H
44#define IPHASE_H
45
46
47/************************ IADBG DEFINE *********************************/
48/* IADebugFlag Bit Map */
49#define IF_IADBG_INIT_ADAPTER 0x00000001 // init adapter info
50#define IF_IADBG_TX 0x00000002 // debug TX
51#define IF_IADBG_RX 0x00000004 // debug RX
52#define IF_IADBG_QUERY_INFO 0x00000008 // debug Request call
53#define IF_IADBG_SHUTDOWN 0x00000010 // debug shutdown event
54#define IF_IADBG_INTR 0x00000020 // debug interrupt DPC
55#define IF_IADBG_TXPKT 0x00000040 // debug TX PKT
56#define IF_IADBG_RXPKT 0x00000080 // debug RX PKT
57#define IF_IADBG_ERR 0x00000100 // debug system error
58#define IF_IADBG_EVENT 0x00000200 // debug event
59#define IF_IADBG_DIS_INTR 0x00001000 // debug disable interrupt
60#define IF_IADBG_EN_INTR 0x00002000 // debug enable interrupt
61#define IF_IADBG_LOUD 0x00004000 // debugging info
62#define IF_IADBG_VERY_LOUD 0x00008000 // excessive debugging info
63#define IF_IADBG_CBR 0x00100000 //
64#define IF_IADBG_UBR 0x00200000 //
65#define IF_IADBG_ABR 0x00400000 //
66#define IF_IADBG_DESC 0x01000000 //
67#define IF_IADBG_SUNI_STAT 0x02000000 // suni statistics
68#define IF_IADBG_RESET 0x04000000
69
70#define IF_IADBG(f) if (IADebugFlag & (f))
71
72#ifdef CONFIG_ATM_IA_DEBUG /* Debug build */
73
74#define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }
75#define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }
76#define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }
77
78#define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
79#define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
80#define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }
81#define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }
82#define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }
83
84#define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }
85#define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }
86#define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }
87
88#define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }
89#define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }
90#define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }
91#define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }
92
93#define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }
94#define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }
95#define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }
96#define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }
97#define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }
98
99#else /* free build */
100#define IF_LOUD(A)
101#define IF_VERY_LOUD(A)
102#define IF_INIT_ADAPTER(A)
103#define IF_INIT(A)
104#define IF_SUNI_STAT(A)
105#define IF_PVC_CHKPKT(A)
106#define IF_QUERY_INFO(A)
107#define IF_COPY_OVER(A)
108#define IF_HANG(A)
109#define IF_INTR(A)
110#define IF_DIS_INTR(A)
111#define IF_EN_INTR(A)
112#define IF_TX(A)
113#define IF_RX(A)
114#define IF_TXDEBUG(A)
115#define IF_VC(A)
116#define IF_ERR(A)
117#define IF_CBR(A)
118#define IF_UBR(A)
119#define IF_ABR(A)
120#define IF_SHUTDOWN(A)
121#define DbgPrint(A)
122#define IF_EVENT(A)
123#define IF_TXPKT(A)
124#define IF_RXPKT(A)
125#endif /* CONFIG_ATM_IA_DEBUG */
126
127#define isprint(a) ((a >=' ')&&(a <= '~'))
128#define ATM_DESC(skb) (skb->protocol)
129#define IA_SKB_STATE(skb) (skb->protocol)
130#define IA_DLED 1
131#define IA_TX_DONE 2
132
133/* iadbg defines */
134#define IA_CMD 0x7749
135typedef struct {
136 int cmd;
137 int sub_cmd;
138 int len;
139 u32 maddr;
140 int status;
141 void __user *buf;
142} IA_CMDBUF, *PIA_CMDBUF;
143
144/* cmds */
145#define MEMDUMP 0x01
146
147/* sub_cmds */
148#define MEMDUMP_SEGREG 0x2
149#define MEMDUMP_DEV 0x1
150#define MEMDUMP_REASSREG 0x3
151#define MEMDUMP_FFL 0x4
152#define READ_REG 0x5
153#define WAKE_DBG_WAIT 0x6
154
155/************************ IADBG DEFINE END ***************************/
156
157#define Boolean(x) ((x) ? 1 : 0)
158#define NR_VCI 1024 /* number of VCIs */
159#define NR_VCI_LD 10 /* log2(NR_VCI) */
160#define NR_VCI_4K 4096 /* number of VCIs */
161#define NR_VCI_4K_LD 12 /* log2(NR_VCI) */
162#define MEM_VALID 0xfffffff0 /* mask base address with this */
163
164#ifndef PCI_VENDOR_ID_IPHASE
165#define PCI_VENDOR_ID_IPHASE 0x107e
166#endif
167#ifndef PCI_DEVICE_ID_IPHASE_5575
168#define PCI_DEVICE_ID_IPHASE_5575 0x0008
169#endif
170#define DEV_LABEL "ia"
171#define PCR 207692
172#define ICR 100000
173#define MCR 0
174#define TBE 1000
175#define FRTT 1
176#define RIF 2
177#define RDF 4
178#define NRMCODE 5 /* 0 - 7 */
179#define TRMCODE 3 /* 0 - 7 */
180#define CDFCODE 6
181#define ATDFCODE 2 /* 0 - 15 */
182
183/*---------------------- Packet/Cell Memory ------------------------*/
184#define TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */
185#define DFL_TX_BUF_SZ 10240 /* 10 K buffers */
186#define DFL_TX_BUFFERS 50 /* number of packet buffers for Tx
187 - descriptor 0 unused */
188#define REASS_RAM_SIZE 0x10000 /* for 64K 1K VC board */
189#define RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */
190#define DFL_RX_BUF_SZ 10240 /* 10k buffers */
191#define DFL_RX_BUFFERS 50 /* number of packet buffers for Rx
192 - descriptor 0 unused */
193
194struct cpcs_trailer
195{
196 u_short control;
197 u_short length;
198 u_int crc32;
199};
200
201struct cpcs_trailer_desc
202{
203 struct cpcs_trailer *cpcs;
204 dma_addr_t dma_addr;
205};
206
207struct ia_vcc
208{
209 int rxing;
210 int txing;
211 int NumCbrEntry;
212 u32 pcr;
213 u32 saved_tx_quota;
214 int flow_inc;
215 struct sk_buff_head txing_skb;
216 int ltimeout;
217 u8 vc_desc_cnt;
218
219};
220
221struct abr_vc_table
222{
223 u_char status;
224 u_char rdf;
225 u_short air;
226 u_int res[3];
227 u_int req_rm_cell_data1;
228 u_int req_rm_cell_data2;
229 u_int add_rm_cell_data1;
230 u_int add_rm_cell_data2;
231};
232
233/* 32 byte entries */
234struct main_vc
235{
236 u_short type;
237#define ABR 0x8000
238#define UBR 0xc000
239#define CBR 0x0000
240 /* ABR fields */
241 u_short nrm;
242 u_short trm;
243 u_short rm_timestamp_hi;
244 u_short rm_timestamp_lo:8,
245 crm:8;
246 u_short remainder; /* ABR and UBR fields - last 10 bits*/
247 u_short next_vc_sched;
248 u_short present_desc; /* all classes */
249 u_short last_cell_slot; /* ABR and UBR */
250 u_short pcr;
251 u_short fraction;
252 u_short icr;
253 u_short atdf;
254 u_short mcr;
255 u_short acr;
256 u_short unack:8,
257 status:8; /* all classes */
258#define UIOLI 0x80
259#define CRC_APPEND 0x40 /* for status field - CRC-32 append */
260#define ABR_STATE 0x02
261
262};
263
264
265/* 8 byte entries */
266struct ext_vc
267{
268 u_short atm_hdr1;
269 u_short atm_hdr2;
270 u_short last_desc;
271 u_short out_of_rate_link; /* reserved for UBR and CBR */
272};
273
274
275#define DLE_ENTRIES 256
276#define DMA_INT_ENABLE 0x0002 /* use for both Tx and Rx */
277#define TX_DLE_PSI 0x0001
278#define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)
279
280/* Descriptor List Entries (DLE) */
281struct dle
282{
283 u32 sys_pkt_addr;
284 u32 local_pkt_addr;
285 u32 bytes;
286 u16 prq_wr_ptr_data;
287 u16 mode;
288};
289
290struct dle_q
291{
292 struct dle *start;
293 struct dle *end;
294 struct dle *read;
295 struct dle *write;
296};
297
298struct free_desc_q
299{
300 int desc; /* Descriptor number */
301 struct free_desc_q *next;
302};
303
304struct tx_buf_desc {
305 unsigned short desc_mode;
306 unsigned short vc_index;
307 unsigned short res1; /* reserved field */
308 unsigned short bytes;
309 unsigned short buf_start_hi;
310 unsigned short buf_start_lo;
311 unsigned short res2[10]; /* reserved field */
312};
313
314
315struct rx_buf_desc {
316 unsigned short desc_mode;
317 unsigned short vc_index;
318 unsigned short vpi;
319 unsigned short bytes;
320 unsigned short buf_start_hi;
321 unsigned short buf_start_lo;
322 unsigned short dma_start_hi;
323 unsigned short dma_start_lo;
324 unsigned short crc_upper;
325 unsigned short crc_lower;
326 unsigned short res:8, timeout:8;
327 unsigned short res2[5]; /* reserved field */
328};
329
330/*--------SAR stuff ---------------------*/
331
332#define EPROM_SIZE 0x40000 /* says 64K in the docs ??? */
333#define MAC1_LEN 4
334#define MAC2_LEN 2
335
336/*------------ PCI Memory Space Map, 128K SAR memory ----------------*/
337#define IPHASE5575_PCI_CONFIG_REG_BASE 0x0000
338#define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */
339#define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000
340#define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000
341#define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000
342#define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE
343#define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000
344#define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000
345
346/*------------ Bus interface control registers -----------------*/
347#define IPHASE5575_BUS_CONTROL_REG 0x00
348#define IPHASE5575_BUS_STATUS_REG 0x01 /* actual offset 0x04 */
349#define IPHASE5575_MAC1 0x02
350#define IPHASE5575_REV 0x03
351#define IPHASE5575_MAC2 0x03 /*actual offset 0x0e-reg 0x0c*/
352#define IPHASE5575_EXT_RESET 0x04
353#define IPHASE5575_INT_RESET 0x05 /* addr 1c ?? reg 0x06 */
354#define IPHASE5575_PCI_ADDR_PAGE 0x07 /* reg 0x08, 0x09 ?? */
355#define IPHASE5575_EEPROM_ACCESS 0x0a /* actual offset 0x28 */
356#define IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b
357#define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c
358#define IPHASE5575_CELL_FIFO_READ_PTR 0x0d
359#define IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e
360#define IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f /* actual offset 0x3c */
361
362/* Bus Interface Control Register bits */
363#define CTRL_FE_RST 0x80000000
364#define CTRL_LED 0x40000000
365#define CTRL_25MBPHY 0x10000000
366#define CTRL_ENCMBMEM 0x08000000
367#define CTRL_ENOFFSEG 0x01000000
368#define CTRL_ERRMASK 0x00400000
369#define CTRL_DLETMASK 0x00100000
370#define CTRL_DLERMASK 0x00080000
371#define CTRL_FEMASK 0x00040000
372#define CTRL_SEGMASK 0x00020000
373#define CTRL_REASSMASK 0x00010000
374#define CTRL_CSPREEMPT 0x00002000
375#define CTRL_B128 0x00000200
376#define CTRL_B64 0x00000100
377#define CTRL_B48 0x00000080
378#define CTRL_B32 0x00000040
379#define CTRL_B16 0x00000020
380#define CTRL_B8 0x00000010
381
382/* Bus Interface Status Register bits */
383#define STAT_CMEMSIZ 0xc0000000
384#define STAT_ADPARCK 0x20000000
385#define STAT_RESVD 0x1fffff80
386#define STAT_ERRINT 0x00000040
387#define STAT_MARKINT 0x00000020
388#define STAT_DLETINT 0x00000010
389#define STAT_DLERINT 0x00000008
390#define STAT_FEINT 0x00000004
391#define STAT_SEGINT 0x00000002
392#define STAT_REASSINT 0x00000001
393
394
395/*--------------- Segmentation control registers -----------------*/
396/* The segmentation registers are 16 bits access and the addresses
397 are defined as such so the addresses are the actual "offsets" */
398#define IDLEHEADHI 0x00
399#define IDLEHEADLO 0x01
400#define MAXRATE 0x02
401/* Values for MAXRATE register for 155Mbps and 25.6 Mbps operation */
402#define RATE155 0x64b1 // 16 bits float format
403#define MAX_ATM_155 352768 // Cells/second p.118
404#define RATE25 0x5f9d
405
406#define STPARMS 0x03
407#define STPARMS_1K 0x008c
408#define STPARMS_2K 0x0049
409#define STPARMS_4K 0x0026
410#define COMP_EN 0x4000
411#define CBR_EN 0x2000
412#define ABR_EN 0x0800
413#define UBR_EN 0x0400
414
415#define ABRUBR_ARB 0x04
416#define RM_TYPE 0x05
417/*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/
418#define RM_TYPE_4_0 0x0100
419
420#define SEG_COMMAND_REG 0x17
421/* Values for the command register */
422#define RESET_SEG 0x0055
423#define RESET_SEG_STATE 0x00aa
424#define RESET_TX_CELL_CTR 0x00cc
425
426#define CBR_PTR_BASE 0x20
427#define ABR_SBPTR_BASE 0x22
428#define UBR_SBPTR_BASE 0x23
429#define ABRWQ_BASE 0x26
430#define UBRWQ_BASE 0x27
431#define VCT_BASE 0x28
432#define VCTE_BASE 0x29
433#define CBR_TAB_BEG 0x2c
434#define CBR_TAB_END 0x2d
435#define PRQ_ST_ADR 0x30
436#define PRQ_ED_ADR 0x31
437#define PRQ_RD_PTR 0x32
438#define PRQ_WR_PTR 0x33
439#define TCQ_ST_ADR 0x34
440#define TCQ_ED_ADR 0x35
441#define TCQ_RD_PTR 0x36
442#define TCQ_WR_PTR 0x37
443#define SEG_QUEUE_BASE 0x40
444#define SEG_DESC_BASE 0x41
445#define MODE_REG_0 0x45
446#define T_ONLINE 0x0002 /* (i)chipSAR is online */
447
448#define MODE_REG_1 0x46
449#define MODE_REG_1_VAL 0x0400 /*for propoer device operation*/
450
451#define SEG_INTR_STATUS_REG 0x47
452#define SEG_MASK_REG 0x48
453#define TRANSMIT_DONE 0x0200
454#define TCQ_NOT_EMPTY 0x1000 /* this can be used for both the interrupt
455 status registers as well as the mask register */
456
457#define CELL_CTR_HIGH_AUTO 0x49
458#define CELL_CTR_HIGH_NOAUTO 0xc9
459#define CELL_CTR_LO_AUTO 0x4a
460#define CELL_CTR_LO_NOAUTO 0xca
461
462/* Diagnostic registers */
463#define NEXTDESC 0x59
464#define NEXTVC 0x5a
465#define PSLOTCNT 0x5d
466#define NEWDN 0x6a
467#define NEWVC 0x6b
468#define SBPTR 0x6c
469#define ABRWQ_WRPTR 0x6f
470#define ABRWQ_RDPTR 0x70
471#define UBRWQ_WRPTR 0x71
472#define UBRWQ_RDPTR 0x72
473#define CBR_VC 0x73
474#define ABR_SBVC 0x75
475#define UBR_SBVC 0x76
476#define ABRNEXTLINK 0x78
477#define UBRNEXTLINK 0x79
478
479
480/*----------------- Reassembly control registers ---------------------*/
481/* The reassembly registers are 16 bits access and the addresses
482 are defined as such so the addresses are the actual "offsets" */
483#define MODE_REG 0x00
484#define R_ONLINE 0x0002 /* (i)chip is online */
485#define IGN_RAW_FL 0x0004
486
487#define PROTOCOL_ID 0x01
488#define REASS_MASK_REG 0x02
489#define REASS_INTR_STATUS_REG 0x03
490/* Interrupt Status register bits */
491#define RX_PKT_CTR_OF 0x8000
492#define RX_ERR_CTR_OF 0x4000
493#define RX_CELL_CTR_OF 0x1000
494#define RX_FREEQ_EMPT 0x0200
495#define RX_EXCPQ_FL 0x0080
496#define RX_RAWQ_FL 0x0010
497#define RX_EXCP_RCVD 0x0008
498#define RX_PKT_RCVD 0x0004
499#define RX_RAW_RCVD 0x0001
500
501#define DRP_PKT_CNTR 0x04
502#define ERR_CNTR 0x05
503#define RAW_BASE_ADR 0x08
504#define CELL_CTR0 0x0c
505#define CELL_CTR1 0x0d
506#define REASS_COMMAND_REG 0x0f
507/* Values for command register */
508#define RESET_REASS 0x0055
509#define RESET_REASS_STATE 0x00aa
510#define RESET_DRP_PKT_CNTR 0x00f1
511#define RESET_ERR_CNTR 0x00f2
512#define RESET_CELL_CNTR 0x00f8
513#define RESET_REASS_ALL_REGS 0x00ff
514
515#define REASS_DESC_BASE 0x10
516#define VC_LKUP_BASE 0x11
517#define REASS_TABLE_BASE 0x12
518#define REASS_QUEUE_BASE 0x13
519#define PKT_TM_CNT 0x16
520#define TMOUT_RANGE 0x17
521#define INTRVL_CNTR 0x18
522#define TMOUT_INDX 0x19
523#define VP_LKUP_BASE 0x1c
524#define VP_FILTER 0x1d
525#define ABR_LKUP_BASE 0x1e
526#define FREEQ_ST_ADR 0x24
527#define FREEQ_ED_ADR 0x25
528#define FREEQ_RD_PTR 0x26
529#define FREEQ_WR_PTR 0x27
530#define PCQ_ST_ADR 0x28
531#define PCQ_ED_ADR 0x29
532#define PCQ_RD_PTR 0x2a
533#define PCQ_WR_PTR 0x2b
534#define EXCP_Q_ST_ADR 0x2c
535#define EXCP_Q_ED_ADR 0x2d
536#define EXCP_Q_RD_PTR 0x2e
537#define EXCP_Q_WR_PTR 0x2f
538#define CC_FIFO_ST_ADR 0x34
539#define CC_FIFO_ED_ADR 0x35
540#define CC_FIFO_RD_PTR 0x36
541#define CC_FIFO_WR_PTR 0x37
542#define STATE_REG 0x38
543#define BUF_SIZE 0x42
544#define XTRA_RM_OFFSET 0x44
545#define DRP_PKT_CNTR_NC 0x84
546#define ERR_CNTR_NC 0x85
547#define CELL_CNTR0_NC 0x8c
548#define CELL_CNTR1_NC 0x8d
549
550/* State Register bits */
551#define EXCPQ_EMPTY 0x0040
552#define PCQ_EMPTY 0x0010
553#define FREEQ_EMPTY 0x0004
554
555
556/*----------------- Front End registers/ DMA control --------------*/
557/* There is a lot of documentation error regarding these offsets ???
558 eg:- 2 offsets given 800, a00 for rx counter
559 similarly many others
560 Remember again that the offsets are to be 4*register number, so
561 correct the #defines here
562*/
563#define IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */
564#define IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */
565#define IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */
566#define IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */
567
568/*--------------------------- RAM ---------------------------*/
569/* These memory maps are actually offsets from the segmentation and reassembly RAM base addresses */
570
571/* Segmentation Control Memory map */
572#define TX_DESC_BASE 0x0000 /* Buffer Decriptor Table */
573#define TX_COMP_Q 0x1000 /* Transmit Complete Queue */
574#define PKT_RDY_Q 0x1400 /* Packet Ready Queue */
575#define CBR_SCHED_TABLE 0x1800 /* CBR Table */
576#define UBR_SCHED_TABLE 0x3000 /* UBR Table */
577#define UBR_WAIT_Q 0x4000 /* UBR Wait Queue */
578#define ABR_SCHED_TABLE 0x5000 /* ABR Table */
579#define ABR_WAIT_Q 0x5800 /* ABR Wait Queue */
580#define EXT_VC_TABLE 0x6000 /* Extended VC Table */
581#define MAIN_VC_TABLE 0x8000 /* Main VC Table */
582#define SCHEDSZ 1024 /* ABR and UBR Scheduling Table size */
583#define TX_DESC_TABLE_SZ 128 /* Number of entries in the Transmit
584 Buffer Descriptor Table */
585
586/* These are used as table offsets in Descriptor Table address generation */
587#define DESC_MODE 0x0
588#define VC_INDEX 0x1
589#define BYTE_CNT 0x3
590#define PKT_START_HI 0x4
591#define PKT_START_LO 0x5
592
593/* Descriptor Mode Word Bits */
594#define EOM_EN 0x0800
595#define AAL5 0x0100
596#define APP_CRC32 0x0400
597#define CMPL_INT 0x1000
598
599#define TABLE_ADDRESS(db, dn, to) \
600 (((unsigned long)(db & 0x04)) << 16) | (dn << 5) | (to << 1)
601
602/* Reassembly Control Memory Map */
603#define RX_DESC_BASE 0x0000 /* Buffer Descriptor Table */
604#define VP_TABLE 0x5c00 /* VP Table */
605#define EXCEPTION_Q 0x5e00 /* Exception Queue */
606#define FREE_BUF_DESC_Q 0x6000 /* Free Buffer Descriptor Queue */
607#define PKT_COMP_Q 0x6800 /* Packet Complete Queue */
608#define REASS_TABLE 0x7000 /* Reassembly Table */
609#define RX_VC_TABLE 0x7800 /* VC Table */
610#define ABR_VC_TABLE 0x8000 /* ABR VC Table */
611#define RX_DESC_TABLE_SZ 736 /* Number of entries in the Receive
612 Buffer Descriptor Table */
613#define VP_TABLE_SZ 256 /* Number of entries in VPTable */
614#define RX_VC_TABLE_SZ 1024 /* Number of entries in VC Table */
615#define REASS_TABLE_SZ 1024 /* Number of entries in Reassembly Table */
616 /* Buffer Descriptor Table */
617#define RX_ACT 0x8000
618#define RX_VPVC 0x4000
619#define RX_CNG 0x0040
620#define RX_CER 0x0008
621#define RX_PTE 0x0004
622#define RX_OFL 0x0002
623#define NUM_RX_EXCP 32
624
625/* Reassembly Table */
626#define NO_AAL5_PKT 0x0000
627#define AAL5_PKT_REASSEMBLED 0x4000
628#define AAL5_PKT_TERMINATED 0x8000
629#define RAW_PKT 0xc000
630#define REASS_ABR 0x2000
631
632/*-------------------- Base Registers --------------------*/
633#define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE
634#define RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE
635#define PHY_BASE IPHASE5575_FRONT_END_REG_BASE
636#define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE
637#define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE
638
639typedef volatile u_int ffreg_t;
640typedef u_int rreg_t;
641
642typedef struct _ffredn_t {
643 ffreg_t idlehead_high; /* Idle cell header (high) */
644 ffreg_t idlehead_low; /* Idle cell header (low) */
645 ffreg_t maxrate; /* Maximum rate */
646 ffreg_t stparms; /* Traffic Management Parameters */
647 ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
648 ffreg_t rm_type; /* */
649 u_int filler5[0x17 - 0x06];
650 ffreg_t cmd_reg; /* Command register */
651 u_int filler18[0x20 - 0x18];
652 ffreg_t cbr_base; /* CBR Pointer Base */
653 ffreg_t vbr_base; /* VBR Pointer Base */
654 ffreg_t abr_base; /* ABR Pointer Base */
655 ffreg_t ubr_base; /* UBR Pointer Base */
656 u_int filler24;
657 ffreg_t vbrwq_base; /* VBR Wait Queue Base */
658 ffreg_t abrwq_base; /* ABR Wait Queue Base */
659 ffreg_t ubrwq_base; /* UBR Wait Queue Base */
660 ffreg_t vct_base; /* Main VC Table Base */
661 ffreg_t vcte_base; /* Extended Main VC Table Base */
662 u_int filler2a[0x2C - 0x2A];
663 ffreg_t cbr_tab_beg; /* CBR Table Begin */
664 ffreg_t cbr_tab_end; /* CBR Table End */
665 ffreg_t cbr_pointer; /* CBR Pointer */
666 u_int filler2f[0x30 - 0x2F];
667 ffreg_t prq_st_adr; /* Packet Ready Queue Start Address */
668 ffreg_t prq_ed_adr; /* Packet Ready Queue End Address */
669 ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
670 ffreg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
671 ffreg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
672 ffreg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
673 ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
674 ffreg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
675 u_int filler38[0x40 - 0x38];
676 ffreg_t queue_base; /* Base address for PRQ and TCQ */
677 ffreg_t desc_base; /* Base address of descriptor table */
678 u_int filler42[0x45 - 0x42];
679 ffreg_t mode_reg_0; /* Mode register 0 */
680 ffreg_t mode_reg_1; /* Mode register 1 */
681 ffreg_t intr_status_reg;/* Interrupt Status register */
682 ffreg_t mask_reg; /* Mask Register */
683 ffreg_t cell_ctr_high1; /* Total cell transfer count (high) */
684 ffreg_t cell_ctr_lo1; /* Total cell transfer count (low) */
685 ffreg_t state_reg; /* Status register */
686 u_int filler4c[0x58 - 0x4c];
687 ffreg_t curr_desc_num; /* Contains the current descriptor num */
688 ffreg_t next_desc; /* Next descriptor */
689 ffreg_t next_vc; /* Next VC */
690 u_int filler5b[0x5d - 0x5b];
691 ffreg_t present_slot_cnt;/* Present slot count */
692 u_int filler5e[0x6a - 0x5e];
693 ffreg_t new_desc_num; /* New descriptor number */
694 ffreg_t new_vc; /* New VC */
695 ffreg_t sched_tbl_ptr; /* Schedule table pointer */
696 ffreg_t vbrwq_wptr; /* VBR wait queue write pointer */
697 ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */
698 ffreg_t abrwq_wptr; /* ABR wait queue write pointer */
699 ffreg_t abrwq_rptr; /* ABR wait queue read pointer */
700 ffreg_t ubrwq_wptr; /* UBR wait queue write pointer */
701 ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */
702 ffreg_t cbr_vc; /* CBR VC */
703 ffreg_t vbr_sb_vc; /* VBR SB VC */
704 ffreg_t abr_sb_vc; /* ABR SB VC */
705 ffreg_t ubr_sb_vc; /* UBR SB VC */
706 ffreg_t vbr_next_link; /* VBR next link */
707 ffreg_t abr_next_link; /* ABR next link */
708 ffreg_t ubr_next_link; /* UBR next link */
709 u_int filler7a[0x7c-0x7a];
710 ffreg_t out_rate_head; /* Out of rate head */
711 u_int filler7d[0xca-0x7d]; /* pad out to full address space */
712 ffreg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
713 ffreg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
714 u_int fillercc[0x100-0xcc]; /* pad out to full address space */
715} ffredn_t;
716
717typedef struct _rfredn_t {
718 rreg_t mode_reg_0; /* Mode register 0 */
719 rreg_t protocol_id; /* Protocol ID */
720 rreg_t mask_reg; /* Mask Register */
721 rreg_t intr_status_reg;/* Interrupt status register */
722 rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */
723 rreg_t err_cntr; /* Error Counter (cleared on read) */
724 u_int filler6[0x08 - 0x06];
725 rreg_t raw_base_adr; /* Base addr for raw cell Q */
726 u_int filler2[0x0c - 0x09];
727 rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */
728 rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */
729 u_int filler3[0x0f - 0x0e];
730 rreg_t cmd_reg; /* Command register */
731 rreg_t desc_base; /* Base address for description table */
732 rreg_t vc_lkup_base; /* Base address for VC lookup table */
733 rreg_t reass_base; /* Base address for reassembler table */
734 rreg_t queue_base; /* Base address for Communication queue */
735 u_int filler14[0x16 - 0x14];
736 rreg_t pkt_tm_cnt; /* Packet Timeout and count register */
737 rreg_t tmout_range; /* Range of reassembley IDs for timeout */
738 rreg_t intrvl_cntr; /* Packet aging interval counter */
739 rreg_t tmout_indx; /* index of pkt being tested for aging */
740 u_int filler1a[0x1c - 0x1a];
741 rreg_t vp_lkup_base; /* Base address for VP lookup table */
742 rreg_t vp_filter; /* VP filter register */
743 rreg_t abr_lkup_base; /* Base address of ABR VC Table */
744 u_int filler1f[0x24 - 0x1f];
745 rreg_t fdq_st_adr; /* Free desc queue start address */
746 rreg_t fdq_ed_adr; /* Free desc queue end address */
747 rreg_t fdq_rd_ptr; /* Free desc queue read pointer */
748 rreg_t fdq_wr_ptr; /* Free desc queue write pointer */
749 rreg_t pcq_st_adr; /* Packet Complete queue start address */
750 rreg_t pcq_ed_adr; /* Packet Complete queue end address */
751 rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */
752 rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */
753 rreg_t excp_st_adr; /* Exception queue start address */
754 rreg_t excp_ed_adr; /* Exception queue end address */
755 rreg_t excp_rd_ptr; /* Exception queue read pointer */
756 rreg_t excp_wr_ptr; /* Exception queue write pointer */
757 u_int filler30[0x34 - 0x30];
758 rreg_t raw_st_adr; /* Raw Cell start address */
759 rreg_t raw_ed_adr; /* Raw Cell end address */
760 rreg_t raw_rd_ptr; /* Raw Cell read pointer */
761 rreg_t raw_wr_ptr; /* Raw Cell write pointer */
762 rreg_t state_reg; /* State Register */
763 u_int filler39[0x42 - 0x39];
764 rreg_t buf_size; /* Buffer size */
765 u_int filler43;
766 rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */
767 u_int filler45[0x84 - 0x45];
768 rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */
769 rreg_t err_cntr_nc; /* Error Counter, Not clear on read */
770 u_int filler86[0x8c - 0x86];
771 rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */
772 rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */
773 u_int filler8e[0x100-0x8e]; /* pad out to full address space */
774} rfredn_t;
775
776typedef struct {
777 /* Atlantic */
778 ffredn_t ffredn; /* F FRED */
779 rfredn_t rfredn; /* R FRED */
780} ia_regs_t;
781
782typedef struct {
783 u_short f_vc_type; /* VC type */
784 u_short f_nrm; /* Nrm */
785 u_short f_nrmexp; /* Nrm Exp */
786 u_short reserved6; /* */
787 u_short f_crm; /* Crm */
788 u_short reserved10; /* Reserved */
789 u_short reserved12; /* Reserved */
790 u_short reserved14; /* Reserved */
791 u_short last_cell_slot; /* last_cell_slot_count */
792 u_short f_pcr; /* Peak Cell Rate */
793 u_short fraction; /* fraction */
794 u_short f_icr; /* Initial Cell Rate */
795 u_short f_cdf; /* */
796 u_short f_mcr; /* Minimum Cell Rate */
797 u_short f_acr; /* Allowed Cell Rate */
798 u_short f_status; /* */
799} f_vc_abr_entry;
800
801typedef struct {
802 u_short r_status_rdf; /* status + RDF */
803 u_short r_air; /* AIR */
804 u_short reserved4[14]; /* Reserved */
805} r_vc_abr_entry;
806
807#define MRM 3
808
809typedef struct srv_cls_param {
810 u32 class_type; /* CBR/VBR/ABR/UBR; use the enum above */
811 u32 pcr; /* Peak Cell Rate (24-bit) */
812 /* VBR parameters */
813 u32 scr; /* sustainable cell rate */
814 u32 max_burst_size; /* ?? cell rate or data rate */
815
816 /* ABR only UNI 4.0 Parameters */
817 u32 mcr; /* Min Cell Rate (24-bit) */
818 u32 icr; /* Initial Cell Rate (24-bit) */
819 u32 tbe; /* Transient Buffer Exposure (24-bit) */
820 u32 frtt; /* Fixed Round Trip Time (24-bit) */
821
822#if 0 /* Additional Parameters of TM 4.0 */
823bits 31 30 29 28 27-25 24-22 21-19 18-9
824-----------------------------------------------------------------------------
825| NRM present | TRM prsnt | CDF prsnt | ADTF prsnt | NRM | TRM | CDF | ADTF |
826-----------------------------------------------------------------------------
827#endif /* 0 */
828
829 u8 nrm; /* Max # of Cells for each forward RM
830 cell (3-bit) */
831 u8 trm; /* Time between forward RM cells (3-bit) */
832 u16 adtf; /* ACR Decrease Time Factor (10-bit) */
833 u8 cdf; /* Cutoff Decrease Factor (3-bit) */
834 u8 rif; /* Rate Increment Factor (4-bit) */
835 u8 rdf; /* Rate Decrease Factor (4-bit) */
836 u8 reserved; /* 8 bits to keep structure word aligned */
837} srv_cls_param_t;
838
839struct testTable_t {
840 u16 lastTime;
841 u16 fract;
842 u8 vc_status;
843};
844
845typedef struct {
846 u16 vci;
847 u16 error;
848} RX_ERROR_Q;
849
850typedef struct {
851 u8 active: 1;
852 u8 abr: 1;
853 u8 ubr: 1;
854 u8 cnt: 5;
855#define VC_ACTIVE 0x01
856#define VC_ABR 0x02
857#define VC_UBR 0x04
858} vcstatus_t;
859
860struct ia_rfL_t {
861 u32 fdq_st; /* Free desc queue start address */
862 u32 fdq_ed; /* Free desc queue end address */
863 u32 fdq_rd; /* Free desc queue read pointer */
864 u32 fdq_wr; /* Free desc queue write pointer */
865 u32 pcq_st; /* Packet Complete queue start address */
866 u32 pcq_ed; /* Packet Complete queue end address */
867 u32 pcq_rd; /* Packet Complete queue read pointer */
868 u32 pcq_wr; /* Packet Complete queue write pointer */
869};
870
871struct ia_ffL_t {
872 u32 prq_st; /* Packet Ready Queue Start Address */
873 u32 prq_ed; /* Packet Ready Queue End Address */
874 u32 prq_wr; /* Packet Ready Queue write pointer */
875 u32 tcq_st; /* Transmit Complete Queue Start Address*/
876 u32 tcq_ed; /* Transmit Complete Queue End Address */
877 u32 tcq_rd; /* Transmit Complete Queue read pointer */
878};
879
880struct desc_tbl_t {
881 u32 timestamp;
882 struct ia_vcc *iavcc;
883 struct sk_buff *txskb;
884};
885
886typedef struct ia_rtn_q {
887 struct desc_tbl_t data;
888 struct ia_rtn_q *next, *tail;
889} IARTN_Q;
890
891#define SUNI_LOSV 0x04
892enum ia_suni {
893 SUNI_MASTER_RESET = 0x000, /* SUNI Master Reset and Identity */
894 SUNI_MASTER_CONFIG = 0x004, /* SUNI Master Configuration */
895 SUNI_MASTER_INTR_STAT = 0x008, /* SUNI Master Interrupt Status */
896 SUNI_RESERVED1 = 0x00c, /* Reserved */
897 SUNI_MASTER_CLK_MONITOR = 0x010, /* SUNI Master Clock Monitor */
898 SUNI_MASTER_CONTROL = 0x014, /* SUNI Master Clock Monitor */
899 /* Reserved (10) */
900 SUNI_RSOP_CONTROL = 0x040, /* RSOP Control/Interrupt Enable */
901 SUNI_RSOP_STATUS = 0x044, /* RSOP Status/Interrupt States */
902 SUNI_RSOP_SECTION_BIP8L = 0x048, /* RSOP Section BIP-8 LSB */
903 SUNI_RSOP_SECTION_BIP8M = 0x04c, /* RSOP Section BIP-8 MSB */
904
905 SUNI_TSOP_CONTROL = 0x050, /* TSOP Control */
906 SUNI_TSOP_DIAG = 0x054, /* TSOP Disgnostics */
907 /* Reserved (2) */
908 SUNI_RLOP_CS = 0x060, /* RLOP Control/Status */
909 SUNI_RLOP_INTR = 0x064, /* RLOP Interrupt Enable/Status */
910 SUNI_RLOP_LINE_BIP24L = 0x068, /* RLOP Line BIP-24 LSB */
911 SUNI_RLOP_LINE_BIP24 = 0x06c, /* RLOP Line BIP-24 */
912 SUNI_RLOP_LINE_BIP24M = 0x070, /* RLOP Line BIP-24 MSB */
913 SUNI_RLOP_LINE_FEBEL = 0x074, /* RLOP Line FEBE LSB */
914 SUNI_RLOP_LINE_FEBE = 0x078, /* RLOP Line FEBE */
915 SUNI_RLOP_LINE_FEBEM = 0x07c, /* RLOP Line FEBE MSB */
916
917 SUNI_TLOP_CONTROL = 0x080, /* TLOP Control */
918 SUNI_TLOP_DISG = 0x084, /* TLOP Disgnostics */
919 /* Reserved (14) */
920 SUNI_RPOP_CS = 0x0c0, /* RPOP Status/Control */
921 SUNI_RPOP_INTR = 0x0c4, /* RPOP Interrupt/Status */
922 SUNI_RPOP_RESERVED = 0x0c8, /* RPOP Reserved */
923 SUNI_RPOP_INTR_ENA = 0x0cc, /* RPOP Interrupt Enable */
924 /* Reserved (3) */
925 SUNI_RPOP_PATH_SIG = 0x0dc, /* RPOP Path Signal Label */
926 SUNI_RPOP_BIP8L = 0x0e0, /* RPOP Path BIP-8 LSB */
927 SUNI_RPOP_BIP8M = 0x0e4, /* RPOP Path BIP-8 MSB */
928 SUNI_RPOP_FEBEL = 0x0e8, /* RPOP Path FEBE LSB */
929 SUNI_RPOP_FEBEM = 0x0ec, /* RPOP Path FEBE MSB */
930 /* Reserved (4) */
931 SUNI_TPOP_CNTRL_DAIG = 0x100, /* TPOP Control/Disgnostics */
932 SUNI_TPOP_POINTER_CTRL = 0x104, /* TPOP Pointer Control */
933 SUNI_TPOP_SOURCER_CTRL = 0x108, /* TPOP Source Control */
934 /* Reserved (2) */
935 SUNI_TPOP_ARB_PRTL = 0x114, /* TPOP Arbitrary Pointer LSB */
936 SUNI_TPOP_ARB_PRTM = 0x118, /* TPOP Arbitrary Pointer MSB */
937 SUNI_TPOP_RESERVED2 = 0x11c, /* TPOP Reserved */
938 SUNI_TPOP_PATH_SIG = 0x120, /* TPOP Path Signal Lable */
939 SUNI_TPOP_PATH_STATUS = 0x124, /* TPOP Path Status */
940 /* Reserved (6) */
941 SUNI_RACP_CS = 0x140, /* RACP Control/Status */
942 SUNI_RACP_INTR = 0x144, /* RACP Interrupt Enable/Status */
943 SUNI_RACP_HDR_PATTERN = 0x148, /* RACP Match Header Pattern */
944 SUNI_RACP_HDR_MASK = 0x14c, /* RACP Match Header Mask */
945 SUNI_RACP_CORR_HCS = 0x150, /* RACP Correctable HCS Error Count */
946 SUNI_RACP_UNCORR_HCS = 0x154, /* RACP Uncorrectable HCS Err Count */
947 /* Reserved (10) */
948 SUNI_TACP_CONTROL = 0x180, /* TACP Control */
949 SUNI_TACP_IDLE_HDR_PAT = 0x184, /* TACP Idle Cell Header Pattern */
950 SUNI_TACP_IDLE_PAY_PAY = 0x188, /* TACP Idle Cell Payld Octet Patrn */
951 /* Reserved (5) */
952 /* Reserved (24) */
953 /* FIXME: unused but name conflicts.
954 * SUNI_MASTER_TEST = 0x200, SUNI Master Test */
955 SUNI_RESERVED_TEST = 0x204 /* SUNI Reserved for Test */
956};
957
958typedef struct _SUNI_STATS_
959{
960 u32 valid; // 1 = oc3 PHY card
961 u32 carrier_detect; // GPIN input
962 // RSOP: receive section overhead processor
963 u16 rsop_oof_state; // 1 = out of frame
964 u16 rsop_lof_state; // 1 = loss of frame
965 u16 rsop_los_state; // 1 = loss of signal
966 u32 rsop_los_count; // loss of signal count
967 u32 rsop_bse_count; // section BIP-8 error count
968 // RLOP: receive line overhead processor
969 u16 rlop_ferf_state; // 1 = far end receive failure
970 u16 rlop_lais_state; // 1 = line AIS
971 u32 rlop_lbe_count; // BIP-24 count
972 u32 rlop_febe_count; // FEBE count;
973 // RPOP: receive path overhead processor
974 u16 rpop_lop_state; // 1 = LOP
975 u16 rpop_pais_state; // 1 = path AIS
976 u16 rpop_pyel_state; // 1 = path yellow alert
977 u32 rpop_bip_count; // path BIP-8 error count
978 u32 rpop_febe_count; // path FEBE error count
979 u16 rpop_psig; // path signal label value
980 // RACP: receive ATM cell processor
981 u16 racp_hp_state; // hunt/presync state
982 u32 racp_fu_count; // FIFO underrun count
983 u32 racp_fo_count; // FIFO overrun count
984 u32 racp_chcs_count; // correctable HCS error count
985 u32 racp_uchcs_count; // uncorrectable HCS error count
986} IA_SUNI_STATS;
987
988typedef struct iadev_priv {
989 /*-----base pointers into (i)chipSAR+ address space */
990 u32 __iomem *phy; /* Base pointer into phy (SUNI). */
991 u32 __iomem *dma; /* Base pointer into DMA control registers. */
992 u32 __iomem *reg; /* Base pointer to SAR registers. */
993 u32 __iomem *seg_reg; /* base pointer to segmentation engine
994 internal registers */
995 u32 __iomem *reass_reg; /* base pointer to reassemble engine
996 internal registers */
997 u32 __iomem *ram; /* base pointer to SAR RAM */
998 void __iomem *seg_ram;
999 void __iomem *reass_ram;
1000 struct dle_q tx_dle_q;
1001 struct free_desc_q *tx_free_desc_qhead;
1002 struct sk_buff_head tx_dma_q, tx_backlog;
1003 spinlock_t tx_lock;
1004 IARTN_Q tx_return_q;
1005 u32 close_pending;
1006 wait_queue_head_t close_wait;
1007 wait_queue_head_t timeout_wait;
1008 struct cpcs_trailer_desc *tx_buf;
1009 u16 num_tx_desc, tx_buf_sz, rate_limit;
1010 u32 tx_cell_cnt, tx_pkt_cnt;
1011 void __iomem *MAIN_VC_TABLE_ADDR, *EXT_VC_TABLE_ADDR, *ABR_SCHED_TABLE_ADDR;
1012 struct dle_q rx_dle_q;
1013 struct free_desc_q *rx_free_desc_qhead;
1014 struct sk_buff_head rx_dma_q;
1015 spinlock_t rx_lock;
1016 struct atm_vcc **rx_open; /* list of all open VCs */
1017 u16 num_rx_desc, rx_buf_sz, rxing;
1018 u32 rx_pkt_ram, rx_tmp_cnt;
1019 unsigned long rx_tmp_jif;
1020 void __iomem *RX_DESC_BASE_ADDR;
1021 u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
1022 struct atm_dev *next_board; /* other iphase devices */
1023 struct pci_dev *pci;
1024 int mem;
1025 unsigned int real_base; /* real and virtual base address */
1026 void __iomem *base;
1027 unsigned int pci_map_size; /*pci map size of board */
1028 unsigned char irq;
1029 unsigned char bus;
1030 unsigned char dev_fn;
1031 u_short phy_type;
1032 u_short num_vc, memSize, memType;
1033 struct ia_ffL_t ffL;
1034 struct ia_rfL_t rfL;
1035 /* Suni stat */
1036 // IA_SUNI_STATS suni_stats;
1037 unsigned char carrier_detect;
1038 /* CBR related */
1039 // transmit DMA & Receive
1040 unsigned int tx_dma_cnt; // number of elements on dma queue
1041 unsigned int rx_dma_cnt; // number of elements on rx dma queue
1042 unsigned int NumEnabledCBR; // number of CBR VCI's enabled. CBR
1043 // receive MARK for Cell FIFO
1044 unsigned int rx_mark_cnt; // number of elements on mark queue
1045 unsigned int CbrTotEntries; // Total CBR Entries in Scheduling Table.
1046 unsigned int CbrRemEntries; // Remaining CBR Entries in Scheduling Table.
1047 unsigned int CbrEntryPt; // CBR Sched Table Entry Point.
1048 unsigned int Granularity; // CBR Granularity given Table Size.
1049 /* ABR related */
1050 unsigned int sum_mcr, sum_cbr, LineRate;
1051 unsigned int n_abr;
1052 struct desc_tbl_t *desc_tbl;
1053 u_short host_tcq_wr;
1054 struct testTable_t **testTable;
1055 dma_addr_t tx_dle_dma;
1056 dma_addr_t rx_dle_dma;
1057} IADEV;
1058
1059
1060#define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)
1061#define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
1062
1063/******************* IDT77105 25MB/s PHY DEFINE *****************************/
1064enum ia_mb25 {
1065 MB25_MASTER_CTRL = 0x00, /* Master control */
1066 MB25_INTR_STATUS = 0x04, /* Interrupt status */
1067 MB25_DIAG_CONTROL = 0x08, /* Diagnostic control */
1068 MB25_LED_HEC = 0x0c, /* LED driver and HEC status/control */
1069 MB25_LOW_BYTE_COUNTER = 0x10,
1070 MB25_HIGH_BYTE_COUNTER = 0x14
1071};
1072
1073/*
1074 * Master Control
1075 */
1076#define MB25_MC_UPLO 0x80 /* UPLO */
1077#define MB25_MC_DREC 0x40 /* Discard receive cell errors */
1078#define MB25_MC_ECEIO 0x20 /* Enable Cell Error Interrupts Only */
1079#define MB25_MC_TDPC 0x10 /* Transmit data parity check */
1080#define MB25_MC_DRIC 0x08 /* Discard receive idle cells */
1081#define MB25_MC_HALTTX 0x04 /* Halt Tx */
1082#define MB25_MC_UMS 0x02 /* UTOPIA mode select */
1083#define MB25_MC_ENABLED 0x01 /* Enable interrupt */
1084
1085/*
1086 * Interrupt Status
1087 */
1088#define MB25_IS_GSB 0x40 /* GOOD Symbol Bit */
1089#define MB25_IS_HECECR 0x20 /* HEC error cell received */
1090#define MB25_IS_SCR 0x10 /* "Short Cell" Received */
1091#define MB25_IS_TPE 0x08 /* Trnamsit Parity Error */
1092#define MB25_IS_RSCC 0x04 /* Receive Signal Condition change */
1093#define MB25_IS_RCSE 0x02 /* Received Cell Symbol Error */
1094#define MB25_IS_RFIFOO 0x01 /* Received FIFO Overrun */
1095
1096/*
1097 * Diagnostic Control
1098 */
1099#define MB25_DC_FTXCD 0x80 /* Force TxClav deassert */
1100#define MB25_DC_RXCOS 0x40 /* RxClav operation select */
1101#define MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */
1102#define MB25_DC_RLFLUSH 0x10 /* Clear receive FIFO */
1103#define MB25_DC_IXPE 0x08 /* Insert xmit payload error */
1104#define MB25_DC_IXHECE 0x04 /* Insert Xmit HEC Error */
1105#define MB25_DC_LB_MASK 0x03 /* Loopback control mask */
1106
1107#define MB25_DC_LL 0x03 /* Line Loopback */
1108#define MB25_DC_PL 0x02 /* PHY Loopback */
1109#define MB25_DC_NM 0x00
1110
1111#define FE_MASK 0x00F0
1112#define FE_MULTI_MODE 0x0000
1113#define FE_SINGLE_MODE 0x0010
1114#define FE_UTP_OPTION 0x0020
1115#define FE_25MBIT_PHY 0x0040
1116#define FE_DS3_PHY 0x0080 /* DS3 */
1117#define FE_E3_PHY 0x0090 /* E3 */
1118
1119/*********************** SUNI_PM7345 PHY DEFINE HERE *********************/
1120enum suni_pm7345 {
1121 SUNI_CONFIG = 0x000, /* SUNI Configuration */
1122 SUNI_INTR_ENBL = 0x004, /* SUNI Interrupt Enable */
1123 SUNI_INTR_STAT = 0x008, /* SUNI Interrupt Status */
1124 SUNI_CONTROL = 0x00c, /* SUNI Control */
1125 SUNI_ID_RESET = 0x010, /* SUNI Reset and Identity */
1126 SUNI_DATA_LINK_CTRL = 0x014,
1127 SUNI_RBOC_CONF_INTR_ENBL = 0x018,
1128 SUNI_RBOC_STAT = 0x01c,
1129 SUNI_DS3_FRM_CFG = 0x020,
1130 SUNI_DS3_FRM_INTR_ENBL = 0x024,
1131 SUNI_DS3_FRM_INTR_STAT = 0x028,
1132 SUNI_DS3_FRM_STAT = 0x02c,
1133 SUNI_RFDL_CFG = 0x030,
1134 SUNI_RFDL_ENBL_STAT = 0x034,
1135 SUNI_RFDL_STAT = 0x038,
1136 SUNI_RFDL_DATA = 0x03c,
1137 SUNI_PMON_CHNG = 0x040,
1138 SUNI_PMON_INTR_ENBL_STAT = 0x044,
1139 /* SUNI_RESERVED1 (0x13 - 0x11) */
1140 SUNI_PMON_LCV_EVT_CNT_LSB = 0x050,
1141 SUNI_PMON_LCV_EVT_CNT_MSB = 0x054,
1142 SUNI_PMON_FBE_EVT_CNT_LSB = 0x058,
1143 SUNI_PMON_FBE_EVT_CNT_MSB = 0x05c,
1144 SUNI_PMON_SEZ_DET_CNT_LSB = 0x060,
1145 SUNI_PMON_SEZ_DET_CNT_MSB = 0x064,
1146 SUNI_PMON_PE_EVT_CNT_LSB = 0x068,
1147 SUNI_PMON_PE_EVT_CNT_MSB = 0x06c,
1148 SUNI_PMON_PPE_EVT_CNT_LSB = 0x070,
1149 SUNI_PMON_PPE_EVT_CNT_MSB = 0x074,
1150 SUNI_PMON_FEBE_EVT_CNT_LSB = 0x078,
1151 SUNI_PMON_FEBE_EVT_CNT_MSB = 0x07c,
1152 SUNI_DS3_TRAN_CFG = 0x080,
1153 SUNI_DS3_TRAN_DIAG = 0x084,
1154 /* SUNI_RESERVED2 (0x23 - 0x21) */
1155 SUNI_XFDL_CFG = 0x090,
1156 SUNI_XFDL_INTR_ST = 0x094,
1157 SUNI_XFDL_XMIT_DATA = 0x098,
1158 SUNI_XBOC_CODE = 0x09c,
1159 SUNI_SPLR_CFG = 0x0a0,
1160 SUNI_SPLR_INTR_EN = 0x0a4,
1161 SUNI_SPLR_INTR_ST = 0x0a8,
1162 SUNI_SPLR_STATUS = 0x0ac,
1163 SUNI_SPLT_CFG = 0x0b0,
1164 SUNI_SPLT_CNTL = 0x0b4,
1165 SUNI_SPLT_DIAG_G1 = 0x0b8,
1166 SUNI_SPLT_F1 = 0x0bc,
1167 SUNI_CPPM_LOC_METERS = 0x0c0,
1168 SUNI_CPPM_CHG_OF_CPPM_PERF_METR = 0x0c4,
1169 SUNI_CPPM_B1_ERR_CNT_LSB = 0x0c8,
1170 SUNI_CPPM_B1_ERR_CNT_MSB = 0x0cc,
1171 SUNI_CPPM_FRAMING_ERR_CNT_LSB = 0x0d0,
1172 SUNI_CPPM_FRAMING_ERR_CNT_MSB = 0x0d4,
1173 SUNI_CPPM_FEBE_CNT_LSB = 0x0d8,
1174 SUNI_CPPM_FEBE_CNT_MSB = 0x0dc,
1175 SUNI_CPPM_HCS_ERR_CNT_LSB = 0x0e0,
1176 SUNI_CPPM_HCS_ERR_CNT_MSB = 0x0e4,
1177 SUNI_CPPM_IDLE_UN_CELL_CNT_LSB = 0x0e8,
1178 SUNI_CPPM_IDLE_UN_CELL_CNT_MSB = 0x0ec,
1179 SUNI_CPPM_RCV_CELL_CNT_LSB = 0x0f0,
1180 SUNI_CPPM_RCV_CELL_CNT_MSB = 0x0f4,
1181 SUNI_CPPM_XMIT_CELL_CNT_LSB = 0x0f8,
1182 SUNI_CPPM_XMIT_CELL_CNT_MSB = 0x0fc,
1183 SUNI_RXCP_CTRL = 0x100,
1184 SUNI_RXCP_FCTRL = 0x104,
1185 SUNI_RXCP_INTR_EN_STS = 0x108,
1186 SUNI_RXCP_IDLE_PAT_H1 = 0x10c,
1187 SUNI_RXCP_IDLE_PAT_H2 = 0x110,
1188 SUNI_RXCP_IDLE_PAT_H3 = 0x114,
1189 SUNI_RXCP_IDLE_PAT_H4 = 0x118,
1190 SUNI_RXCP_IDLE_MASK_H1 = 0x11c,
1191 SUNI_RXCP_IDLE_MASK_H2 = 0x120,
1192 SUNI_RXCP_IDLE_MASK_H3 = 0x124,
1193 SUNI_RXCP_IDLE_MASK_H4 = 0x128,
1194 SUNI_RXCP_CELL_PAT_H1 = 0x12c,
1195 SUNI_RXCP_CELL_PAT_H2 = 0x130,
1196 SUNI_RXCP_CELL_PAT_H3 = 0x134,
1197 SUNI_RXCP_CELL_PAT_H4 = 0x138,
1198 SUNI_RXCP_CELL_MASK_H1 = 0x13c,
1199 SUNI_RXCP_CELL_MASK_H2 = 0x140,
1200 SUNI_RXCP_CELL_MASK_H3 = 0x144,
1201 SUNI_RXCP_CELL_MASK_H4 = 0x148,
1202 SUNI_RXCP_HCS_CS = 0x14c,
1203 SUNI_RXCP_LCD_CNT_THRESHOLD = 0x150,
1204 /* SUNI_RESERVED3 (0x57 - 0x54) */
1205 SUNI_TXCP_CTRL = 0x160,
1206 SUNI_TXCP_INTR_EN_STS = 0x164,
1207 SUNI_TXCP_IDLE_PAT_H1 = 0x168,
1208 SUNI_TXCP_IDLE_PAT_H2 = 0x16c,
1209 SUNI_TXCP_IDLE_PAT_H3 = 0x170,
1210 SUNI_TXCP_IDLE_PAT_H4 = 0x174,
1211 SUNI_TXCP_IDLE_PAT_H5 = 0x178,
1212 SUNI_TXCP_IDLE_PAYLOAD = 0x17c,
1213 SUNI_E3_FRM_FRAM_OPTIONS = 0x180,
1214 SUNI_E3_FRM_MAINT_OPTIONS = 0x184,
1215 SUNI_E3_FRM_FRAM_INTR_ENBL = 0x188,
1216 SUNI_E3_FRM_FRAM_INTR_IND_STAT = 0x18c,
1217 SUNI_E3_FRM_MAINT_INTR_ENBL = 0x190,
1218 SUNI_E3_FRM_MAINT_INTR_IND = 0x194,
1219 SUNI_E3_FRM_MAINT_STAT = 0x198,
1220 SUNI_RESERVED4 = 0x19c,
1221 SUNI_E3_TRAN_FRAM_OPTIONS = 0x1a0,
1222 SUNI_E3_TRAN_STAT_DIAG_OPTIONS = 0x1a4,
1223 SUNI_E3_TRAN_BIP_8_ERR_MASK = 0x1a8,
1224 SUNI_E3_TRAN_MAINT_ADAPT_OPTS = 0x1ac,
1225 SUNI_TTB_CTRL = 0x1b0,
1226 SUNI_TTB_TRAIL_TRACE_ID_STAT = 0x1b4,
1227 SUNI_TTB_IND_ADDR = 0x1b8,
1228 SUNI_TTB_IND_DATA = 0x1bc,
1229 SUNI_TTB_EXP_PAYLOAD_TYPE = 0x1c0,
1230 SUNI_TTB_PAYLOAD_TYPE_CTRL_STAT = 0x1c4,
1231 /* SUNI_PAD5 (0x7f - 0x71) */
1232 SUNI_MASTER_TEST = 0x200,
1233 /* SUNI_PAD6 (0xff - 0x80) */
1234};
1235
1236#define SUNI_PM7345_T suni_pm7345_t
1237#define SUNI_PM7345 0x20 /* Suni chip type */
1238#define SUNI_PM5346 0x30 /* Suni chip type */
1239/*
1240 * SUNI_PM7345 Configuration
1241 */
1242#define SUNI_PM7345_CLB 0x01 /* Cell loopback */
1243#define SUNI_PM7345_PLB 0x02 /* Payload loopback */
1244#define SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */
1245#define SUNI_PM7345_LLB 0x80 /* Line loopback */
1246#define SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */
1247#define SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */
1248#define SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */
1249#define SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */
1250/*
1251 * DS3 FRMR Interrupt Enable
1252 */
1253#define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */
1254#define SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */
1255#define SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */
1256#define SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/
1257#define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */
1258#define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/
1259#define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */
1260#define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */
1261
1262/*
1263 * DS3 FRMR Status
1264 */
1265#define SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */
1266#define SUNI_DS3_REDV 0x40 /* DS3 RED state */
1267#define SUNI_DS3_CBITV 0x20 /* Application ID channel state */
1268#define SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/
1269#define SUNI_DS3_IDLV 0x08 /* Idle signal state */
1270#define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/
1271#define SUNI_DS3_OOFV 0x02 /* Out of frame state */
1272#define SUNI_DS3_LOSV 0x01 /* Loss of signal state */
1273
1274/*
1275 * E3 FRMR Interrupt/Status
1276 */
1277#define SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */
1278#define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */
1279#define SUNI_E3_LCVI 0x10 /* Line code violation intr */
1280#define SUNI_E3_COFAI 0x08 /* Change of frame align intr */
1281#define SUNI_E3_OOFI 0x04 /* Out of frame intr status */
1282#define SUNI_E3_LOS 0x02 /* Loss of signal state */
1283#define SUNI_E3_OOF 0x01 /* Out of frame state */
1284
1285/*
1286 * E3 FRMR Maintenance Status
1287 */
1288#define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/
1289#define SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */
1290#define SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/
1291
1292/*
1293 * RXCP Control/Status
1294 */
1295#define SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */
1296#define SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */
1297#define SUNI_DS3_HCSADD 0x20 /* Add coset poly */
1298#define SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/
1299#define SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */
1300#define SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */
1301#define SUNI_DS3_OOCDV 0x02 /* Cell delineation state */
1302#define SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */
1303
1304/*
1305 * RXCP Interrupt Enable/Status
1306 */
1307#define SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */
1308#define SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */
1309#define SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */
1310#define SUNI_DS3_OOCDI 0x10 /* SYNC state */
1311#define SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */
1312#define SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */
1313#define SUNI_DS3_FOVRI 0x02 /* FIFO overrun */
1314#define SUNI_DS3_FUDRI 0x01 /* FIFO underrun */
1315
1316///////////////////SUNI_PM7345 PHY DEFINE END /////////////////////////////
1317
1318/* ia_eeprom define*/
1319#define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/
1320#define MEM_SIZE_128K 0x0000 /* board has 128k buffer */
1321#define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */
1322#define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */
1323 /* 0x3 to 0xF are reserved for future */
1324
1325#define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */
1326#define FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */
1327#define FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */
1328#define FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */
1329
1330#define NOVRAM_SIZE 64
1331#define CMD_LEN 10
1332
1333/***********
1334 *
1335 * Switches and defines for header files.
1336 *
1337 * The following defines are used to turn on and off
1338 * various options in the header files. Primarily useful
1339 * for debugging.
1340 *
1341 ***********/
1342
1343/*
1344 * a list of the commands that can be sent to the NOVRAM
1345 */
1346
1347#define EXTEND 0x100
1348#define IAWRITE 0x140
1349#define IAREAD 0x180
1350#define ERASE 0x1c0
1351
1352#define EWDS 0x00
1353#define WRAL 0x10
1354#define ERAL 0x20
1355#define EWEN 0x30
1356
1357/*
1358 * these bits duplicate the hw_flip.h register settings
1359 * note: how the data in / out bits are defined in the flipper specification
1360 */
1361
1362#define NVCE 0x02
1363#define NVSK 0x01
1364#define NVDO 0x08
1365#define NVDI 0x04
1366/***********************
1367 *
1368 * This define ands the value and the current config register and puts
1369 * the result in the config register
1370 *
1371 ***********************/
1372
1373#define CFG_AND(val) { \
1374 u32 t; \
1375 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1376 t &= (val); \
1377 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1378 }
1379
1380/***********************
1381 *
1382 * This define ors the value and the current config register and puts
1383 * the result in the config register
1384 *
1385 ***********************/
1386
1387#define CFG_OR(val) { \
1388 u32 t; \
1389 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1390 t |= (val); \
1391 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1392 }
1393
1394/***********************
1395 *
1396 * Send a command to the NOVRAM, the command is in cmd.
1397 *
1398 * clear CE and SK. Then assert CE.
1399 * Clock each of the command bits out in the correct order with SK
1400 * exit with CE still asserted
1401 *
1402 ***********************/
1403
1404#define NVRAM_CMD(cmd) { \
1405 int i; \
1406 u_short c = cmd; \
1407 CFG_AND(~(NVCE|NVSK)); \
1408 CFG_OR(NVCE); \
1409 for (i=0; i<CMD_LEN; i++) { \
1410 NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
1411 c <<= 1; \
1412 } \
1413 }
1414
1415/***********************
1416 *
1417 * clear the CE, this must be used after each command is complete
1418 *
1419 ***********************/
1420
1421#define NVRAM_CLR_CE {CFG_AND(~NVCE)}
1422
1423/***********************
1424 *
1425 * clock the data bit in bitval out to the NOVRAM. The bitval must be
1426 * a 1 or 0, or the clockout operation is undefined
1427 *
1428 ***********************/
1429
1430#define NVRAM_CLKOUT(bitval) { \
1431 CFG_AND(~NVDI); \
1432 CFG_OR((bitval) ? NVDI : 0); \
1433 CFG_OR(NVSK); \
1434 CFG_AND( ~NVSK); \
1435 }
1436
1437/***********************
1438 *
1439 * clock the data bit in and return a 1 or 0, depending on the value
1440 * that was received from the NOVRAM
1441 *
1442 ***********************/
1443
1444#define NVRAM_CLKIN(value) { \
1445 u32 _t; \
1446 CFG_OR(NVSK); \
1447 CFG_AND(~NVSK); \
1448 _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1449 value = (_t & NVDO) ? 1 : 0; \
1450 }
1451
1452
1453#endif /* IPHASE_H */
1454