1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * ps3vram - Use extra PS3 video ram as block device. |
4 | * |
5 | * Copyright 2009 Sony Corporation |
6 | * |
7 | * Based on the MTD ps3vram driver, which is |
8 | * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com> |
9 | * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr> |
10 | */ |
11 | |
12 | #include <linux/blkdev.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/module.h> |
15 | #include <linux/proc_fs.h> |
16 | #include <linux/seq_file.h> |
17 | #include <linux/slab.h> |
18 | |
19 | #include <asm/cell-regs.h> |
20 | #include <asm/firmware.h> |
21 | #include <asm/lv1call.h> |
22 | #include <asm/ps3.h> |
23 | #include <asm/ps3gpu.h> |
24 | |
25 | |
26 | #define DEVICE_NAME "ps3vram" |
27 | |
28 | |
29 | #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */ |
30 | #define XDR_IOIF 0x0c000000 |
31 | |
32 | #define FIFO_BASE XDR_IOIF |
33 | #define FIFO_SIZE (64 * 1024) |
34 | |
35 | #define DMA_PAGE_SIZE (4 * 1024) |
36 | |
37 | #define CACHE_PAGE_SIZE (256 * 1024) |
38 | #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE) |
39 | |
40 | #define CACHE_OFFSET CACHE_PAGE_SIZE |
41 | #define FIFO_OFFSET 0 |
42 | |
43 | #define CTRL_PUT 0x10 |
44 | #define CTRL_GET 0x11 |
45 | #define CTRL_TOP 0x15 |
46 | |
47 | #define UPLOAD_SUBCH 1 |
48 | #define DOWNLOAD_SUBCH 2 |
49 | |
50 | #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c |
51 | #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 |
52 | |
53 | #define CACHE_PAGE_PRESENT 1 |
54 | #define CACHE_PAGE_DIRTY 2 |
55 | |
56 | struct ps3vram_tag { |
57 | unsigned int address; |
58 | unsigned int flags; |
59 | }; |
60 | |
61 | struct ps3vram_cache { |
62 | unsigned int page_count; |
63 | unsigned int page_size; |
64 | struct ps3vram_tag *tags; |
65 | unsigned int hit; |
66 | unsigned int miss; |
67 | }; |
68 | |
69 | struct ps3vram_priv { |
70 | struct gendisk *gendisk; |
71 | |
72 | u64 size; |
73 | |
74 | u64 memory_handle; |
75 | u64 context_handle; |
76 | u32 __iomem *ctrl; |
77 | void __iomem *reports; |
78 | u8 *xdr_buf; |
79 | |
80 | u32 *fifo_base; |
81 | u32 *fifo_ptr; |
82 | |
83 | struct ps3vram_cache cache; |
84 | |
85 | spinlock_t lock; /* protecting list of bios */ |
86 | struct bio_list list; |
87 | }; |
88 | |
89 | |
90 | static int ps3vram_major; |
91 | |
92 | #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */ |
93 | #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */ |
94 | #define DMA_NOTIFIER_SIZE 0x40 |
95 | #define NOTIFIER 7 /* notifier used for completion report */ |
96 | |
97 | static char *size = "256M" ; |
98 | module_param(size, charp, 0); |
99 | MODULE_PARM_DESC(size, "memory size" ); |
100 | |
101 | static u32 __iomem *ps3vram_get_notifier(void __iomem *reports, int notifier) |
102 | { |
103 | return reports + DMA_NOTIFIER_OFFSET_BASE + |
104 | DMA_NOTIFIER_SIZE * notifier; |
105 | } |
106 | |
107 | static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev) |
108 | { |
109 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
110 | u32 __iomem *notify = ps3vram_get_notifier(reports: priv->reports, NOTIFIER); |
111 | int i; |
112 | |
113 | for (i = 0; i < 4; i++) |
114 | iowrite32be(0xffffffff, notify + i); |
115 | } |
116 | |
117 | static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev, |
118 | unsigned int timeout_ms) |
119 | { |
120 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
121 | u32 __iomem *notify = ps3vram_get_notifier(reports: priv->reports, NOTIFIER); |
122 | unsigned long timeout; |
123 | |
124 | for (timeout = 20; timeout; timeout--) { |
125 | if (!ioread32be(notify + 3)) |
126 | return 0; |
127 | udelay(10); |
128 | } |
129 | |
130 | timeout = jiffies + msecs_to_jiffies(m: timeout_ms); |
131 | |
132 | do { |
133 | if (!ioread32be(notify + 3)) |
134 | return 0; |
135 | msleep(msecs: 1); |
136 | } while (time_before(jiffies, timeout)); |
137 | |
138 | return -ETIMEDOUT; |
139 | } |
140 | |
141 | static void ps3vram_init_ring(struct ps3_system_bus_device *dev) |
142 | { |
143 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
144 | |
145 | iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT); |
146 | iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_GET); |
147 | } |
148 | |
149 | static int ps3vram_wait_ring(struct ps3_system_bus_device *dev, |
150 | unsigned int timeout_ms) |
151 | { |
152 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
153 | unsigned long timeout = jiffies + msecs_to_jiffies(m: timeout_ms); |
154 | |
155 | do { |
156 | if (ioread32be(priv->ctrl + CTRL_PUT) == ioread32be(priv->ctrl + CTRL_GET)) |
157 | return 0; |
158 | msleep(msecs: 1); |
159 | } while (time_before(jiffies, timeout)); |
160 | |
161 | dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n" , |
162 | ioread32be(priv->ctrl + CTRL_PUT), ioread32be(priv->ctrl + CTRL_GET), |
163 | ioread32be(priv->ctrl + CTRL_TOP)); |
164 | |
165 | return -ETIMEDOUT; |
166 | } |
167 | |
168 | static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data) |
169 | { |
170 | *(priv->fifo_ptr)++ = data; |
171 | } |
172 | |
173 | static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag, |
174 | u32 size) |
175 | { |
176 | ps3vram_out_ring(priv, data: (size << 18) | (chan << 13) | tag); |
177 | } |
178 | |
179 | static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev) |
180 | { |
181 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
182 | int status; |
183 | |
184 | ps3vram_out_ring(priv, data: 0x20000000 | (FIFO_BASE + FIFO_OFFSET)); |
185 | |
186 | iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT); |
187 | |
188 | /* asking the HV for a blit will kick the FIFO */ |
189 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
190 | if (status) |
191 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n" , |
192 | __func__, status); |
193 | |
194 | priv->fifo_ptr = priv->fifo_base; |
195 | } |
196 | |
197 | static void ps3vram_fire_ring(struct ps3_system_bus_device *dev) |
198 | { |
199 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
200 | int status; |
201 | |
202 | mutex_lock(&ps3_gpu_mutex); |
203 | |
204 | iowrite32be(FIFO_BASE + FIFO_OFFSET + (priv->fifo_ptr - priv->fifo_base) |
205 | * sizeof(u32), priv->ctrl + CTRL_PUT); |
206 | |
207 | /* asking the HV for a blit will kick the FIFO */ |
208 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
209 | if (status) |
210 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n" , |
211 | __func__, status); |
212 | |
213 | if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) > |
214 | FIFO_SIZE - 1024) { |
215 | dev_dbg(&dev->core, "FIFO full, rewinding\n" ); |
216 | ps3vram_wait_ring(dev, timeout_ms: 200); |
217 | ps3vram_rewind_ring(dev); |
218 | } |
219 | |
220 | mutex_unlock(lock: &ps3_gpu_mutex); |
221 | } |
222 | |
223 | static void ps3vram_bind(struct ps3_system_bus_device *dev) |
224 | { |
225 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
226 | |
227 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, tag: 0, size: 1); |
228 | ps3vram_out_ring(priv, data: 0x31337303); |
229 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, tag: 0x180, size: 3); |
230 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); |
231 | ps3vram_out_ring(priv, data: 0xfeed0001); /* DMA system RAM instance */ |
232 | ps3vram_out_ring(priv, data: 0xfeed0000); /* DMA video RAM instance */ |
233 | |
234 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, tag: 0, size: 1); |
235 | ps3vram_out_ring(priv, data: 0x3137c0de); |
236 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, tag: 0x180, size: 3); |
237 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); |
238 | ps3vram_out_ring(priv, data: 0xfeed0000); /* DMA video RAM instance */ |
239 | ps3vram_out_ring(priv, data: 0xfeed0001); /* DMA system RAM instance */ |
240 | |
241 | ps3vram_fire_ring(dev); |
242 | } |
243 | |
244 | static int ps3vram_upload(struct ps3_system_bus_device *dev, |
245 | unsigned int src_offset, unsigned int dst_offset, |
246 | int len, int count) |
247 | { |
248 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
249 | |
250 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, |
251 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, size: 8); |
252 | ps3vram_out_ring(priv, XDR_IOIF + src_offset); |
253 | ps3vram_out_ring(priv, data: dst_offset); |
254 | ps3vram_out_ring(priv, data: len); |
255 | ps3vram_out_ring(priv, data: len); |
256 | ps3vram_out_ring(priv, data: len); |
257 | ps3vram_out_ring(priv, data: count); |
258 | ps3vram_out_ring(priv, data: (1 << 8) | 1); |
259 | ps3vram_out_ring(priv, data: 0); |
260 | |
261 | ps3vram_notifier_reset(dev); |
262 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, |
263 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, size: 1); |
264 | ps3vram_out_ring(priv, data: 0); |
265 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, tag: 0x100, size: 1); |
266 | ps3vram_out_ring(priv, data: 0); |
267 | ps3vram_fire_ring(dev); |
268 | if (ps3vram_notifier_wait(dev, timeout_ms: 200) < 0) { |
269 | dev_warn(&dev->core, "%s: Notifier timeout\n" , __func__); |
270 | return -1; |
271 | } |
272 | |
273 | return 0; |
274 | } |
275 | |
276 | static int ps3vram_download(struct ps3_system_bus_device *dev, |
277 | unsigned int src_offset, unsigned int dst_offset, |
278 | int len, int count) |
279 | { |
280 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
281 | |
282 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, |
283 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, size: 8); |
284 | ps3vram_out_ring(priv, data: src_offset); |
285 | ps3vram_out_ring(priv, XDR_IOIF + dst_offset); |
286 | ps3vram_out_ring(priv, data: len); |
287 | ps3vram_out_ring(priv, data: len); |
288 | ps3vram_out_ring(priv, data: len); |
289 | ps3vram_out_ring(priv, data: count); |
290 | ps3vram_out_ring(priv, data: (1 << 8) | 1); |
291 | ps3vram_out_ring(priv, data: 0); |
292 | |
293 | ps3vram_notifier_reset(dev); |
294 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, |
295 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, size: 1); |
296 | ps3vram_out_ring(priv, data: 0); |
297 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, tag: 0x100, size: 1); |
298 | ps3vram_out_ring(priv, data: 0); |
299 | ps3vram_fire_ring(dev); |
300 | if (ps3vram_notifier_wait(dev, timeout_ms: 200) < 0) { |
301 | dev_warn(&dev->core, "%s: Notifier timeout\n" , __func__); |
302 | return -1; |
303 | } |
304 | |
305 | return 0; |
306 | } |
307 | |
308 | static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry) |
309 | { |
310 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
311 | struct ps3vram_cache *cache = &priv->cache; |
312 | |
313 | if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY)) |
314 | return; |
315 | |
316 | dev_dbg(&dev->core, "Flushing %d: 0x%08x\n" , entry, |
317 | cache->tags[entry].address); |
318 | if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size, |
319 | dst_offset: cache->tags[entry].address, DMA_PAGE_SIZE, |
320 | count: cache->page_size / DMA_PAGE_SIZE) < 0) { |
321 | dev_err(&dev->core, |
322 | "Failed to upload from 0x%x to " "0x%x size 0x%x\n" , |
323 | entry * cache->page_size, cache->tags[entry].address, |
324 | cache->page_size); |
325 | } |
326 | cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY; |
327 | } |
328 | |
329 | static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry, |
330 | unsigned int address) |
331 | { |
332 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
333 | struct ps3vram_cache *cache = &priv->cache; |
334 | |
335 | dev_dbg(&dev->core, "Fetching %d: 0x%08x\n" , entry, address); |
336 | if (ps3vram_download(dev, src_offset: address, |
337 | CACHE_OFFSET + entry * cache->page_size, |
338 | DMA_PAGE_SIZE, |
339 | count: cache->page_size / DMA_PAGE_SIZE) < 0) { |
340 | dev_err(&dev->core, |
341 | "Failed to download from 0x%x to 0x%x size 0x%x\n" , |
342 | address, entry * cache->page_size, cache->page_size); |
343 | } |
344 | |
345 | cache->tags[entry].address = address; |
346 | cache->tags[entry].flags |= CACHE_PAGE_PRESENT; |
347 | } |
348 | |
349 | |
350 | static void ps3vram_cache_flush(struct ps3_system_bus_device *dev) |
351 | { |
352 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
353 | struct ps3vram_cache *cache = &priv->cache; |
354 | int i; |
355 | |
356 | dev_dbg(&dev->core, "FLUSH\n" ); |
357 | for (i = 0; i < cache->page_count; i++) { |
358 | ps3vram_cache_evict(dev, entry: i); |
359 | cache->tags[i].flags = 0; |
360 | } |
361 | } |
362 | |
363 | static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev, |
364 | loff_t address) |
365 | { |
366 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
367 | struct ps3vram_cache *cache = &priv->cache; |
368 | unsigned int base; |
369 | unsigned int offset; |
370 | int i; |
371 | static int counter; |
372 | |
373 | offset = (unsigned int) (address & (cache->page_size - 1)); |
374 | base = (unsigned int) (address - offset); |
375 | |
376 | /* fully associative check */ |
377 | for (i = 0; i < cache->page_count; i++) { |
378 | if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) && |
379 | cache->tags[i].address == base) { |
380 | cache->hit++; |
381 | dev_dbg(&dev->core, "Found entry %d: 0x%08x\n" , i, |
382 | cache->tags[i].address); |
383 | return i; |
384 | } |
385 | } |
386 | |
387 | /* choose a random entry */ |
388 | i = (jiffies + (counter++)) % cache->page_count; |
389 | dev_dbg(&dev->core, "Using entry %d\n" , i); |
390 | |
391 | ps3vram_cache_evict(dev, entry: i); |
392 | ps3vram_cache_load(dev, entry: i, address: base); |
393 | |
394 | cache->miss++; |
395 | return i; |
396 | } |
397 | |
398 | static int ps3vram_cache_init(struct ps3_system_bus_device *dev) |
399 | { |
400 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
401 | |
402 | priv->cache.page_count = CACHE_PAGE_COUNT; |
403 | priv->cache.page_size = CACHE_PAGE_SIZE; |
404 | priv->cache.tags = kcalloc(CACHE_PAGE_COUNT, |
405 | size: sizeof(struct ps3vram_tag), |
406 | GFP_KERNEL); |
407 | if (!priv->cache.tags) |
408 | return -ENOMEM; |
409 | |
410 | dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n" , |
411 | CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024); |
412 | |
413 | return 0; |
414 | } |
415 | |
416 | static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev) |
417 | { |
418 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
419 | |
420 | ps3vram_cache_flush(dev); |
421 | kfree(objp: priv->cache.tags); |
422 | } |
423 | |
424 | static blk_status_t ps3vram_read(struct ps3_system_bus_device *dev, loff_t from, |
425 | size_t len, size_t *retlen, u_char *buf) |
426 | { |
427 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
428 | unsigned int cached, count; |
429 | |
430 | dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n" , __func__, |
431 | (unsigned int)from, len); |
432 | |
433 | if (from >= priv->size) |
434 | return BLK_STS_IOERR; |
435 | |
436 | if (len > priv->size - from) |
437 | len = priv->size - from; |
438 | |
439 | /* Copy from vram to buf */ |
440 | count = len; |
441 | while (count) { |
442 | unsigned int offset, avail; |
443 | unsigned int entry; |
444 | |
445 | offset = (unsigned int) (from & (priv->cache.page_size - 1)); |
446 | avail = priv->cache.page_size - offset; |
447 | |
448 | entry = ps3vram_cache_match(dev, address: from); |
449 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; |
450 | |
451 | dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x " |
452 | "avail=%08x count=%08x\n" , __func__, |
453 | (unsigned int)from, cached, offset, avail, count); |
454 | |
455 | if (avail > count) |
456 | avail = count; |
457 | memcpy(buf, priv->xdr_buf + cached, avail); |
458 | |
459 | buf += avail; |
460 | count -= avail; |
461 | from += avail; |
462 | } |
463 | |
464 | *retlen = len; |
465 | return 0; |
466 | } |
467 | |
468 | static blk_status_t ps3vram_write(struct ps3_system_bus_device *dev, loff_t to, |
469 | size_t len, size_t *retlen, const u_char *buf) |
470 | { |
471 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
472 | unsigned int cached, count; |
473 | |
474 | if (to >= priv->size) |
475 | return BLK_STS_IOERR; |
476 | |
477 | if (len > priv->size - to) |
478 | len = priv->size - to; |
479 | |
480 | /* Copy from buf to vram */ |
481 | count = len; |
482 | while (count) { |
483 | unsigned int offset, avail; |
484 | unsigned int entry; |
485 | |
486 | offset = (unsigned int) (to & (priv->cache.page_size - 1)); |
487 | avail = priv->cache.page_size - offset; |
488 | |
489 | entry = ps3vram_cache_match(dev, address: to); |
490 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; |
491 | |
492 | dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x " |
493 | "avail=%08x count=%08x\n" , __func__, (unsigned int)to, |
494 | cached, offset, avail, count); |
495 | |
496 | if (avail > count) |
497 | avail = count; |
498 | memcpy(priv->xdr_buf + cached, buf, avail); |
499 | |
500 | priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY; |
501 | |
502 | buf += avail; |
503 | count -= avail; |
504 | to += avail; |
505 | } |
506 | |
507 | *retlen = len; |
508 | return 0; |
509 | } |
510 | |
511 | static int ps3vram_proc_show(struct seq_file *m, void *v) |
512 | { |
513 | struct ps3vram_priv *priv = m->private; |
514 | |
515 | seq_printf(m, fmt: "hit:%u\nmiss:%u\n" , priv->cache.hit, priv->cache.miss); |
516 | return 0; |
517 | } |
518 | |
519 | static void ps3vram_proc_init(struct ps3_system_bus_device *dev) |
520 | { |
521 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
522 | struct proc_dir_entry *pde; |
523 | |
524 | pde = proc_create_single_data(DEVICE_NAME, mode: 0444, NULL, |
525 | show: ps3vram_proc_show, data: priv); |
526 | if (!pde) |
527 | dev_warn(&dev->core, "failed to create /proc entry\n" ); |
528 | } |
529 | |
530 | static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev, |
531 | struct bio *bio) |
532 | { |
533 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
534 | int write = bio_data_dir(bio) == WRITE; |
535 | const char *op = write ? "write" : "read" ; |
536 | loff_t offset = bio->bi_iter.bi_sector << 9; |
537 | blk_status_t error = 0; |
538 | struct bio_vec bvec; |
539 | struct bvec_iter iter; |
540 | struct bio *next; |
541 | |
542 | bio_for_each_segment(bvec, bio, iter) { |
543 | /* PS3 is ppc64, so we don't handle highmem */ |
544 | char *ptr = bvec_virt(bvec: &bvec); |
545 | size_t len = bvec.bv_len, retlen; |
546 | |
547 | dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n" , op, |
548 | len, offset); |
549 | if (write) |
550 | error = ps3vram_write(dev, to: offset, len, retlen: &retlen, buf: ptr); |
551 | else |
552 | error = ps3vram_read(dev, from: offset, len, retlen: &retlen, buf: ptr); |
553 | |
554 | if (error) { |
555 | dev_err(&dev->core, "%s failed\n" , op); |
556 | goto out; |
557 | } |
558 | |
559 | if (retlen != len) { |
560 | dev_err(&dev->core, "Short %s\n" , op); |
561 | error = BLK_STS_IOERR; |
562 | goto out; |
563 | } |
564 | |
565 | offset += len; |
566 | } |
567 | |
568 | dev_dbg(&dev->core, "%s completed\n" , op); |
569 | |
570 | out: |
571 | spin_lock_irq(lock: &priv->lock); |
572 | bio_list_pop(bl: &priv->list); |
573 | next = bio_list_peek(bl: &priv->list); |
574 | spin_unlock_irq(lock: &priv->lock); |
575 | |
576 | bio->bi_status = error; |
577 | bio_endio(bio); |
578 | return next; |
579 | } |
580 | |
581 | static void ps3vram_submit_bio(struct bio *bio) |
582 | { |
583 | struct ps3_system_bus_device *dev = bio->bi_bdev->bd_disk->private_data; |
584 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
585 | int busy; |
586 | |
587 | dev_dbg(&dev->core, "%s\n" , __func__); |
588 | |
589 | spin_lock_irq(lock: &priv->lock); |
590 | busy = !bio_list_empty(bl: &priv->list); |
591 | bio_list_add(bl: &priv->list, bio); |
592 | spin_unlock_irq(lock: &priv->lock); |
593 | |
594 | if (busy) |
595 | return; |
596 | |
597 | do { |
598 | bio = ps3vram_do_bio(dev, bio); |
599 | } while (bio); |
600 | } |
601 | |
602 | static const struct block_device_operations ps3vram_fops = { |
603 | .owner = THIS_MODULE, |
604 | .submit_bio = ps3vram_submit_bio, |
605 | }; |
606 | |
607 | static int ps3vram_probe(struct ps3_system_bus_device *dev) |
608 | { |
609 | struct ps3vram_priv *priv; |
610 | int error, status; |
611 | struct gendisk *gendisk; |
612 | u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar, |
613 | reports_size, xdr_lpar; |
614 | char *rest; |
615 | |
616 | priv = kzalloc(size: sizeof(*priv), GFP_KERNEL); |
617 | if (!priv) { |
618 | error = -ENOMEM; |
619 | goto fail; |
620 | } |
621 | |
622 | spin_lock_init(&priv->lock); |
623 | bio_list_init(bl: &priv->list); |
624 | ps3_system_bus_set_drvdata(dev, priv); |
625 | |
626 | /* Allocate XDR buffer (1MiB aligned) */ |
627 | priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL, |
628 | order: get_order(XDR_BUF_SIZE)); |
629 | if (priv->xdr_buf == NULL) { |
630 | dev_err(&dev->core, "Could not allocate XDR buffer\n" ); |
631 | error = -ENOMEM; |
632 | goto fail_free_priv; |
633 | } |
634 | |
635 | /* Put FIFO at begginning of XDR buffer */ |
636 | priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET); |
637 | priv->fifo_ptr = priv->fifo_base; |
638 | |
639 | /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */ |
640 | if (ps3_open_hv_device(dev)) { |
641 | dev_err(&dev->core, "ps3_open_hv_device failed\n" ); |
642 | error = -EAGAIN; |
643 | goto out_free_xdr_buf; |
644 | } |
645 | |
646 | /* Request memory */ |
647 | status = -1; |
648 | ddr_size = ALIGN(memparse(size, &rest), 1024*1024); |
649 | if (!ddr_size) { |
650 | dev_err(&dev->core, "Specified size is too small\n" ); |
651 | error = -EINVAL; |
652 | goto out_close_gpu; |
653 | } |
654 | |
655 | while (ddr_size > 0) { |
656 | status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0, |
657 | &priv->memory_handle, |
658 | &ddr_lpar); |
659 | if (!status) |
660 | break; |
661 | ddr_size -= 1024*1024; |
662 | } |
663 | if (status) { |
664 | dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n" , |
665 | status); |
666 | error = -ENOMEM; |
667 | goto out_close_gpu; |
668 | } |
669 | |
670 | /* Request context */ |
671 | status = lv1_gpu_context_allocate(priv->memory_handle, 0, |
672 | &priv->context_handle, &ctrl_lpar, |
673 | &info_lpar, &reports_lpar, |
674 | &reports_size); |
675 | if (status) { |
676 | dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n" , |
677 | status); |
678 | error = -ENOMEM; |
679 | goto out_free_memory; |
680 | } |
681 | |
682 | /* Map XDR buffer to RSX */ |
683 | xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)); |
684 | status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
685 | xdr_lpar, XDR_BUF_SIZE, |
686 | CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | |
687 | CBE_IOPTE_M); |
688 | if (status) { |
689 | dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n" , |
690 | status); |
691 | error = -ENOMEM; |
692 | goto out_free_context; |
693 | } |
694 | |
695 | priv->ctrl = ioremap(ctrl_lpar, 64 * 1024); |
696 | if (!priv->ctrl) { |
697 | dev_err(&dev->core, "ioremap CTRL failed\n" ); |
698 | error = -ENOMEM; |
699 | goto out_unmap_context; |
700 | } |
701 | |
702 | priv->reports = ioremap(reports_lpar, reports_size); |
703 | if (!priv->reports) { |
704 | dev_err(&dev->core, "ioremap REPORTS failed\n" ); |
705 | error = -ENOMEM; |
706 | goto out_unmap_ctrl; |
707 | } |
708 | |
709 | mutex_lock(&ps3_gpu_mutex); |
710 | ps3vram_init_ring(dev); |
711 | mutex_unlock(lock: &ps3_gpu_mutex); |
712 | |
713 | priv->size = ddr_size; |
714 | |
715 | ps3vram_bind(dev); |
716 | |
717 | mutex_lock(&ps3_gpu_mutex); |
718 | error = ps3vram_wait_ring(dev, timeout_ms: 100); |
719 | mutex_unlock(lock: &ps3_gpu_mutex); |
720 | if (error < 0) { |
721 | dev_err(&dev->core, "Failed to initialize channels\n" ); |
722 | error = -ETIMEDOUT; |
723 | goto out_unmap_reports; |
724 | } |
725 | |
726 | error = ps3vram_cache_init(dev); |
727 | if (error < 0) { |
728 | goto out_unmap_reports; |
729 | } |
730 | |
731 | ps3vram_proc_init(dev); |
732 | |
733 | gendisk = blk_alloc_disk(NUMA_NO_NODE); |
734 | if (!gendisk) { |
735 | dev_err(&dev->core, "blk_alloc_disk failed\n" ); |
736 | error = -ENOMEM; |
737 | goto out_cache_cleanup; |
738 | } |
739 | |
740 | priv->gendisk = gendisk; |
741 | gendisk->major = ps3vram_major; |
742 | gendisk->minors = 1; |
743 | gendisk->flags |= GENHD_FL_NO_PART; |
744 | gendisk->fops = &ps3vram_fops; |
745 | gendisk->private_data = dev; |
746 | strscpy(p: gendisk->disk_name, DEVICE_NAME, size: sizeof(gendisk->disk_name)); |
747 | set_capacity(disk: gendisk, size: priv->size >> 9); |
748 | |
749 | dev_info(&dev->core, "%s: Using %llu MiB of GPU memory\n" , |
750 | gendisk->disk_name, get_capacity(gendisk) >> 11); |
751 | |
752 | error = device_add_disk(parent: &dev->core, disk: gendisk, NULL); |
753 | if (error) |
754 | goto out_cleanup_disk; |
755 | |
756 | return 0; |
757 | |
758 | out_cleanup_disk: |
759 | put_disk(disk: gendisk); |
760 | out_cache_cleanup: |
761 | remove_proc_entry(DEVICE_NAME, NULL); |
762 | ps3vram_cache_cleanup(dev); |
763 | out_unmap_reports: |
764 | iounmap(priv->reports); |
765 | out_unmap_ctrl: |
766 | iounmap(priv->ctrl); |
767 | out_unmap_context: |
768 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar, |
769 | XDR_BUF_SIZE, CBE_IOPTE_M); |
770 | out_free_context: |
771 | lv1_gpu_context_free(priv->context_handle); |
772 | out_free_memory: |
773 | lv1_gpu_memory_free(priv->memory_handle); |
774 | out_close_gpu: |
775 | ps3_close_hv_device(dev); |
776 | out_free_xdr_buf: |
777 | free_pages(addr: (unsigned long) priv->xdr_buf, order: get_order(XDR_BUF_SIZE)); |
778 | fail_free_priv: |
779 | kfree(objp: priv); |
780 | ps3_system_bus_set_drvdata(dev, NULL); |
781 | fail: |
782 | return error; |
783 | } |
784 | |
785 | static void ps3vram_remove(struct ps3_system_bus_device *dev) |
786 | { |
787 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
788 | |
789 | del_gendisk(gp: priv->gendisk); |
790 | put_disk(disk: priv->gendisk); |
791 | remove_proc_entry(DEVICE_NAME, NULL); |
792 | ps3vram_cache_cleanup(dev); |
793 | iounmap(priv->reports); |
794 | iounmap(priv->ctrl); |
795 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
796 | ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)), |
797 | XDR_BUF_SIZE, CBE_IOPTE_M); |
798 | lv1_gpu_context_free(priv->context_handle); |
799 | lv1_gpu_memory_free(priv->memory_handle); |
800 | ps3_close_hv_device(dev); |
801 | free_pages(addr: (unsigned long) priv->xdr_buf, order: get_order(XDR_BUF_SIZE)); |
802 | kfree(objp: priv); |
803 | ps3_system_bus_set_drvdata(dev, NULL); |
804 | } |
805 | |
806 | static struct ps3_system_bus_driver ps3vram = { |
807 | .match_id = PS3_MATCH_ID_GPU, |
808 | .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK, |
809 | .core.name = DEVICE_NAME, |
810 | .core.owner = THIS_MODULE, |
811 | .probe = ps3vram_probe, |
812 | .remove = ps3vram_remove, |
813 | .shutdown = ps3vram_remove, |
814 | }; |
815 | |
816 | |
817 | static int __init ps3vram_init(void) |
818 | { |
819 | int error; |
820 | |
821 | if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) |
822 | return -ENODEV; |
823 | |
824 | error = register_blkdev(0, DEVICE_NAME); |
825 | if (error <= 0) { |
826 | pr_err("%s: register_blkdev failed %d\n" , DEVICE_NAME, error); |
827 | return error; |
828 | } |
829 | ps3vram_major = error; |
830 | |
831 | pr_info("%s: registered block device major %d\n" , DEVICE_NAME, |
832 | ps3vram_major); |
833 | |
834 | error = ps3_system_bus_driver_register(&ps3vram); |
835 | if (error) |
836 | unregister_blkdev(major: ps3vram_major, DEVICE_NAME); |
837 | |
838 | return error; |
839 | } |
840 | |
841 | static void __exit ps3vram_exit(void) |
842 | { |
843 | ps3_system_bus_driver_unregister(&ps3vram); |
844 | unregister_blkdev(major: ps3vram_major, DEVICE_NAME); |
845 | } |
846 | |
847 | module_init(ps3vram_init); |
848 | module_exit(ps3vram_exit); |
849 | |
850 | MODULE_LICENSE("GPL" ); |
851 | MODULE_DESCRIPTION("PS3 Video RAM Storage Driver" ); |
852 | MODULE_AUTHOR("Sony Corporation" ); |
853 | MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK); |
854 | |