1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Setup routines for AGP 3.5 compliant bridges. |
4 | */ |
5 | |
6 | #include <linux/list.h> |
7 | #include <linux/pci.h> |
8 | #include <linux/agp_backend.h> |
9 | #include <linux/module.h> |
10 | #include <linux/slab.h> |
11 | |
12 | #include "agp.h" |
13 | |
14 | /* Generic AGP 3.5 enabling routines */ |
15 | |
16 | struct agp_3_5_dev { |
17 | struct list_head list; |
18 | u8 capndx; |
19 | u32 maxbw; |
20 | struct pci_dev *dev; |
21 | }; |
22 | |
23 | static void agp_3_5_dev_list_insert(struct list_head *head, struct list_head *new) |
24 | { |
25 | struct agp_3_5_dev *cur, *n = list_entry(new, struct agp_3_5_dev, list); |
26 | struct list_head *pos; |
27 | |
28 | list_for_each(pos, head) { |
29 | cur = list_entry(pos, struct agp_3_5_dev, list); |
30 | if (cur->maxbw > n->maxbw) |
31 | break; |
32 | } |
33 | list_add_tail(new, head: pos); |
34 | } |
35 | |
36 | static void agp_3_5_dev_list_sort(struct agp_3_5_dev *list, unsigned int ndevs) |
37 | { |
38 | struct agp_3_5_dev *cur; |
39 | struct pci_dev *dev; |
40 | struct list_head *pos, *tmp, *head = &list->list, *start = head->next; |
41 | u32 nistat; |
42 | |
43 | INIT_LIST_HEAD(list: head); |
44 | |
45 | for (pos=start; pos!=head; ) { |
46 | cur = list_entry(pos, struct agp_3_5_dev, list); |
47 | dev = cur->dev; |
48 | |
49 | pci_read_config_dword(dev, where: cur->capndx+AGPNISTAT, val: &nistat); |
50 | cur->maxbw = (nistat >> 16) & 0xff; |
51 | |
52 | tmp = pos; |
53 | pos = pos->next; |
54 | agp_3_5_dev_list_insert(head, new: tmp); |
55 | } |
56 | } |
57 | |
58 | /* |
59 | * Initialize all isochronous transfer parameters for an AGP 3.0 |
60 | * node (i.e. a host bridge in combination with the adapters |
61 | * lying behind it...) |
62 | */ |
63 | |
64 | static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge, |
65 | struct agp_3_5_dev *dev_list, unsigned int ndevs) |
66 | { |
67 | /* |
68 | * Convenience structure to make the calculations clearer |
69 | * here. The field names come straight from the AGP 3.0 spec. |
70 | */ |
71 | struct isoch_data { |
72 | u32 maxbw; |
73 | u32 n; |
74 | u32 y; |
75 | u32 l; |
76 | u32 rq; |
77 | struct agp_3_5_dev *dev; |
78 | }; |
79 | |
80 | struct pci_dev *td = bridge->dev, *dev; |
81 | struct list_head *head = &dev_list->list, *pos; |
82 | struct agp_3_5_dev *cur; |
83 | struct isoch_data *master, target; |
84 | unsigned int cdev = 0; |
85 | u32 mnistat, tnistat, tstatus, mcmd; |
86 | u16 tnicmd, mnicmd; |
87 | u32 tot_bw = 0, tot_n = 0, tot_rq = 0, y_max, rq_isoch, rq_async; |
88 | u32 step, rem, rem_isoch, rem_async; |
89 | int ret = 0; |
90 | |
91 | /* |
92 | * We'll work with an array of isoch_data's (one for each |
93 | * device in dev_list) throughout this function. |
94 | */ |
95 | master = kmalloc_array(n: ndevs, size: sizeof(*master), GFP_KERNEL); |
96 | if (master == NULL) { |
97 | ret = -ENOMEM; |
98 | goto get_out; |
99 | } |
100 | |
101 | /* |
102 | * Sort the device list by maxbw. We need to do this because the |
103 | * spec suggests that the devices with the smallest requirements |
104 | * have their resources allocated first, with all remaining resources |
105 | * falling to the device with the largest requirement. |
106 | * |
107 | * We don't exactly do this, we divide target resources by ndevs |
108 | * and split them amongst the AGP 3.0 devices. The remainder of such |
109 | * division operations are dropped on the last device, sort of like |
110 | * the spec mentions it should be done. |
111 | * |
112 | * We can't do this sort when we initially construct the dev_list |
113 | * because we don't know until this function whether isochronous |
114 | * transfers are enabled and consequently whether maxbw will mean |
115 | * anything. |
116 | */ |
117 | agp_3_5_dev_list_sort(list: dev_list, ndevs); |
118 | |
119 | pci_read_config_dword(dev: td, where: bridge->capndx+AGPNISTAT, val: &tnistat); |
120 | pci_read_config_dword(dev: td, where: bridge->capndx+AGPSTAT, val: &tstatus); |
121 | |
122 | /* Extract power-on defaults from the target */ |
123 | target.maxbw = (tnistat >> 16) & 0xff; |
124 | target.n = (tnistat >> 8) & 0xff; |
125 | target.y = (tnistat >> 6) & 0x3; |
126 | target.l = (tnistat >> 3) & 0x7; |
127 | target.rq = (tstatus >> 24) & 0xff; |
128 | |
129 | y_max = target.y; |
130 | |
131 | /* |
132 | * Extract power-on defaults for each device in dev_list. Along |
133 | * the way, calculate the total isochronous bandwidth required |
134 | * by these devices and the largest requested payload size. |
135 | */ |
136 | list_for_each(pos, head) { |
137 | cur = list_entry(pos, struct agp_3_5_dev, list); |
138 | dev = cur->dev; |
139 | |
140 | pci_read_config_dword(dev, where: cur->capndx+AGPNISTAT, val: &mnistat); |
141 | |
142 | master[cdev].maxbw = (mnistat >> 16) & 0xff; |
143 | master[cdev].n = (mnistat >> 8) & 0xff; |
144 | master[cdev].y = (mnistat >> 6) & 0x3; |
145 | master[cdev].dev = cur; |
146 | |
147 | tot_bw += master[cdev].maxbw; |
148 | y_max = max(y_max, master[cdev].y); |
149 | |
150 | cdev++; |
151 | } |
152 | |
153 | /* Check if this configuration has any chance of working */ |
154 | if (tot_bw > target.maxbw) { |
155 | dev_err(&td->dev, "isochronous bandwidth required " |
156 | "by AGP 3.0 devices exceeds that which is supported by " |
157 | "the AGP 3.0 bridge!\n" ); |
158 | ret = -ENODEV; |
159 | goto free_and_exit; |
160 | } |
161 | |
162 | target.y = y_max; |
163 | |
164 | /* |
165 | * Write the calculated payload size into the target's NICMD |
166 | * register. Doing this directly effects the ISOCH_N value |
167 | * in the target's NISTAT register, so we need to do this now |
168 | * to get an accurate value for ISOCH_N later. |
169 | */ |
170 | pci_read_config_word(dev: td, where: bridge->capndx+AGPNICMD, val: &tnicmd); |
171 | tnicmd &= ~(0x3 << 6); |
172 | tnicmd |= target.y << 6; |
173 | pci_write_config_word(dev: td, where: bridge->capndx+AGPNICMD, val: tnicmd); |
174 | |
175 | /* Reread the target's ISOCH_N */ |
176 | pci_read_config_dword(dev: td, where: bridge->capndx+AGPNISTAT, val: &tnistat); |
177 | target.n = (tnistat >> 8) & 0xff; |
178 | |
179 | /* Calculate the minimum ISOCH_N needed by each master */ |
180 | for (cdev=0; cdev<ndevs; cdev++) { |
181 | master[cdev].y = target.y; |
182 | master[cdev].n = master[cdev].maxbw / (master[cdev].y + 1); |
183 | |
184 | tot_n += master[cdev].n; |
185 | } |
186 | |
187 | /* Exit if the minimal ISOCH_N allocation among the masters is more |
188 | * than the target can handle. */ |
189 | if (tot_n > target.n) { |
190 | dev_err(&td->dev, "number of isochronous " |
191 | "transactions per period required by AGP 3.0 devices " |
192 | "exceeds that which is supported by the AGP 3.0 " |
193 | "bridge!\n" ); |
194 | ret = -ENODEV; |
195 | goto free_and_exit; |
196 | } |
197 | |
198 | /* Calculate left over ISOCH_N capability in the target. We'll give |
199 | * this to the hungriest device (as per the spec) */ |
200 | rem = target.n - tot_n; |
201 | |
202 | /* |
203 | * Calculate the minimum isochronous RQ depth needed by each master. |
204 | * Along the way, distribute the extra ISOCH_N capability calculated |
205 | * above. |
206 | */ |
207 | for (cdev=0; cdev<ndevs; cdev++) { |
208 | /* |
209 | * This is a little subtle. If ISOCH_Y > 64B, then ISOCH_Y |
210 | * byte isochronous writes will be broken into 64B pieces. |
211 | * This means we need to budget more RQ depth to account for |
212 | * these kind of writes (each isochronous write is actually |
213 | * many writes on the AGP bus). |
214 | */ |
215 | master[cdev].rq = master[cdev].n; |
216 | if (master[cdev].y > 0x1) |
217 | master[cdev].rq *= (1 << (master[cdev].y - 1)); |
218 | |
219 | tot_rq += master[cdev].rq; |
220 | } |
221 | master[ndevs-1].n += rem; |
222 | |
223 | /* Figure the number of isochronous and asynchronous RQ slots the |
224 | * target is providing. */ |
225 | rq_isoch = (target.y > 0x1) ? target.n * (1 << (target.y - 1)) : target.n; |
226 | rq_async = target.rq - rq_isoch; |
227 | |
228 | /* Exit if the minimal RQ needs of the masters exceeds what the target |
229 | * can provide. */ |
230 | if (tot_rq > rq_isoch) { |
231 | dev_err(&td->dev, "number of request queue slots " |
232 | "required by the isochronous bandwidth requested by " |
233 | "AGP 3.0 devices exceeds the number provided by the " |
234 | "AGP 3.0 bridge!\n" ); |
235 | ret = -ENODEV; |
236 | goto free_and_exit; |
237 | } |
238 | |
239 | /* Calculate asynchronous RQ capability in the target (per master) as |
240 | * well as the total number of leftover isochronous RQ slots. */ |
241 | step = rq_async / ndevs; |
242 | rem_async = step + (rq_async % ndevs); |
243 | rem_isoch = rq_isoch - tot_rq; |
244 | |
245 | /* Distribute the extra RQ slots calculated above and write our |
246 | * isochronous settings out to the actual devices. */ |
247 | for (cdev=0; cdev<ndevs; cdev++) { |
248 | cur = master[cdev].dev; |
249 | dev = cur->dev; |
250 | |
251 | master[cdev].rq += (cdev == ndevs - 1) |
252 | ? (rem_async + rem_isoch) : step; |
253 | |
254 | pci_read_config_word(dev, where: cur->capndx+AGPNICMD, val: &mnicmd); |
255 | pci_read_config_dword(dev, where: cur->capndx+AGPCMD, val: &mcmd); |
256 | |
257 | mnicmd &= ~(0xff << 8); |
258 | mnicmd &= ~(0x3 << 6); |
259 | mcmd &= ~(0xff << 24); |
260 | |
261 | mnicmd |= master[cdev].n << 8; |
262 | mnicmd |= master[cdev].y << 6; |
263 | mcmd |= master[cdev].rq << 24; |
264 | |
265 | pci_write_config_dword(dev, where: cur->capndx+AGPCMD, val: mcmd); |
266 | pci_write_config_word(dev, where: cur->capndx+AGPNICMD, val: mnicmd); |
267 | } |
268 | |
269 | free_and_exit: |
270 | kfree(objp: master); |
271 | |
272 | get_out: |
273 | return ret; |
274 | } |
275 | |
276 | /* |
277 | * This function basically allocates request queue slots among the |
278 | * AGP 3.0 systems in nonisochronous nodes. The algorithm is |
279 | * pretty stupid, divide the total number of RQ slots provided by the |
280 | * target by ndevs. Distribute this many slots to each AGP 3.0 device, |
281 | * giving any left over slots to the last device in dev_list. |
282 | */ |
283 | static void agp_3_5_nonisochronous_node_enable(struct agp_bridge_data *bridge, |
284 | struct agp_3_5_dev *dev_list, unsigned int ndevs) |
285 | { |
286 | struct agp_3_5_dev *cur; |
287 | struct list_head *head = &dev_list->list, *pos; |
288 | u32 tstatus, mcmd; |
289 | u32 trq, mrq, rem; |
290 | unsigned int cdev = 0; |
291 | |
292 | pci_read_config_dword(dev: bridge->dev, where: bridge->capndx+AGPSTAT, val: &tstatus); |
293 | |
294 | trq = (tstatus >> 24) & 0xff; |
295 | mrq = trq / ndevs; |
296 | |
297 | rem = mrq + (trq % ndevs); |
298 | |
299 | for (pos=head->next; cdev<ndevs; cdev++, pos=pos->next) { |
300 | cur = list_entry(pos, struct agp_3_5_dev, list); |
301 | |
302 | pci_read_config_dword(dev: cur->dev, where: cur->capndx+AGPCMD, val: &mcmd); |
303 | mcmd &= ~(0xff << 24); |
304 | mcmd |= ((cdev == ndevs - 1) ? rem : mrq) << 24; |
305 | pci_write_config_dword(dev: cur->dev, where: cur->capndx+AGPCMD, val: mcmd); |
306 | } |
307 | } |
308 | |
309 | /* |
310 | * Fully configure and enable an AGP 3.0 host bridge and all the devices |
311 | * lying behind it. |
312 | */ |
313 | int agp_3_5_enable(struct agp_bridge_data *bridge) |
314 | { |
315 | struct pci_dev *td = bridge->dev, *dev = NULL; |
316 | u8 mcapndx; |
317 | u32 isoch; |
318 | u32 tstatus, mstatus, ncapid; |
319 | u32 mmajor; |
320 | u16 mpstat; |
321 | struct agp_3_5_dev *dev_list, *cur; |
322 | struct list_head *head, *pos; |
323 | unsigned int ndevs = 0; |
324 | int ret = 0; |
325 | |
326 | /* Extract some power-on defaults from the target */ |
327 | pci_read_config_dword(dev: td, where: bridge->capndx+AGPSTAT, val: &tstatus); |
328 | isoch = (tstatus >> 17) & 0x1; |
329 | if (isoch == 0) /* isoch xfers not available, bail out. */ |
330 | return -ENODEV; |
331 | |
332 | /* |
333 | * Allocate a head for our AGP 3.5 device list |
334 | * (multiple AGP v3 devices are allowed behind a single bridge). |
335 | */ |
336 | if ((dev_list = kmalloc(size: sizeof(*dev_list), GFP_KERNEL)) == NULL) { |
337 | ret = -ENOMEM; |
338 | goto get_out; |
339 | } |
340 | head = &dev_list->list; |
341 | INIT_LIST_HEAD(list: head); |
342 | |
343 | /* Find all AGP devices, and add them to dev_list. */ |
344 | for_each_pci_dev(dev) { |
345 | mcapndx = pci_find_capability(dev, PCI_CAP_ID_AGP); |
346 | if (mcapndx == 0) |
347 | continue; |
348 | |
349 | switch ((dev->class >>8) & 0xff00) { |
350 | case 0x0600: /* Bridge */ |
351 | /* Skip bridges. We should call this function for each one. */ |
352 | continue; |
353 | |
354 | case 0x0001: /* Unclassified device */ |
355 | /* Don't know what this is, but log it for investigation. */ |
356 | if (mcapndx != 0) { |
357 | dev_info(&td->dev, "wacky, found unclassified AGP device %s [%04x/%04x]\n" , |
358 | pci_name(dev), |
359 | dev->vendor, dev->device); |
360 | } |
361 | continue; |
362 | |
363 | case 0x0300: /* Display controller */ |
364 | case 0x0400: /* Multimedia controller */ |
365 | if ((cur = kmalloc(size: sizeof(*cur), GFP_KERNEL)) == NULL) { |
366 | ret = -ENOMEM; |
367 | goto free_and_exit; |
368 | } |
369 | cur->dev = dev; |
370 | |
371 | pos = &cur->list; |
372 | list_add(new: pos, head); |
373 | ndevs++; |
374 | continue; |
375 | |
376 | default: |
377 | continue; |
378 | } |
379 | } |
380 | |
381 | /* |
382 | * Take an initial pass through the devices lying behind our host |
383 | * bridge. Make sure each one is actually an AGP 3.0 device, otherwise |
384 | * exit with an error message. Along the way store the AGP 3.0 |
385 | * cap_ptr for each device |
386 | */ |
387 | list_for_each(pos, head) { |
388 | cur = list_entry(pos, struct agp_3_5_dev, list); |
389 | dev = cur->dev; |
390 | |
391 | pci_read_config_word(dev, PCI_STATUS, val: &mpstat); |
392 | if ((mpstat & PCI_STATUS_CAP_LIST) == 0) |
393 | continue; |
394 | |
395 | pci_read_config_byte(dev, PCI_CAPABILITY_LIST, val: &mcapndx); |
396 | if (mcapndx != 0) { |
397 | do { |
398 | pci_read_config_dword(dev, where: mcapndx, val: &ncapid); |
399 | if ((ncapid & 0xff) != 2) |
400 | mcapndx = (ncapid >> 8) & 0xff; |
401 | } |
402 | while (((ncapid & 0xff) != 2) && (mcapndx != 0)); |
403 | } |
404 | |
405 | if (mcapndx == 0) { |
406 | dev_err(&td->dev, "woah! Non-AGP device %s on " |
407 | "secondary bus of AGP 3.5 bridge!\n" , |
408 | pci_name(dev)); |
409 | ret = -ENODEV; |
410 | goto free_and_exit; |
411 | } |
412 | |
413 | mmajor = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf; |
414 | if (mmajor < 3) { |
415 | dev_err(&td->dev, "woah! AGP 2.0 device %s on " |
416 | "secondary bus of AGP 3.5 bridge operating " |
417 | "with AGP 3.0 electricals!\n" , pci_name(dev)); |
418 | ret = -ENODEV; |
419 | goto free_and_exit; |
420 | } |
421 | |
422 | cur->capndx = mcapndx; |
423 | |
424 | pci_read_config_dword(dev, where: cur->capndx+AGPSTAT, val: &mstatus); |
425 | |
426 | if (((mstatus >> 3) & 0x1) == 0) { |
427 | dev_err(&td->dev, "woah! AGP 3.x device %s not " |
428 | "operating in AGP 3.x mode on secondary bus " |
429 | "of AGP 3.5 bridge operating with AGP 3.0 " |
430 | "electricals!\n" , pci_name(dev)); |
431 | ret = -ENODEV; |
432 | goto free_and_exit; |
433 | } |
434 | } |
435 | |
436 | /* |
437 | * Call functions to divide target resources amongst the AGP 3.0 |
438 | * masters. This process is dramatically different depending on |
439 | * whether isochronous transfers are supported. |
440 | */ |
441 | if (isoch) { |
442 | ret = agp_3_5_isochronous_node_enable(bridge, dev_list, ndevs); |
443 | if (ret) { |
444 | dev_info(&td->dev, "something bad happened setting " |
445 | "up isochronous xfers; falling back to " |
446 | "non-isochronous xfer mode\n" ); |
447 | } else { |
448 | goto free_and_exit; |
449 | } |
450 | } |
451 | agp_3_5_nonisochronous_node_enable(bridge, dev_list, ndevs); |
452 | |
453 | free_and_exit: |
454 | /* Be sure to free the dev_list */ |
455 | for (pos=head->next; pos!=head; ) { |
456 | cur = list_entry(pos, struct agp_3_5_dev, list); |
457 | |
458 | pos = pos->next; |
459 | kfree(objp: cur); |
460 | } |
461 | kfree(objp: dev_list); |
462 | |
463 | get_out: |
464 | return ret; |
465 | } |
466 | |