1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * HP Quicksilver AGP GART routines |
4 | * |
5 | * Copyright (c) 2006, Kyle McMartin <kyle@parisc-linux.org> |
6 | * |
7 | * Based on drivers/char/agpgart/hp-agp.c which is |
8 | * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P. |
9 | * Bjorn Helgaas <bjorn.helgaas@hp.com> |
10 | */ |
11 | |
12 | #include <linux/module.h> |
13 | #include <linux/pci.h> |
14 | #include <linux/init.h> |
15 | #include <linux/klist.h> |
16 | #include <linux/agp_backend.h> |
17 | #include <linux/log2.h> |
18 | #include <linux/slab.h> |
19 | |
20 | #include <asm/parisc-device.h> |
21 | #include <asm/ropes.h> |
22 | |
23 | #include "agp.h" |
24 | |
25 | #define DRVNAME "quicksilver" |
26 | #define DRVPFX DRVNAME ": " |
27 | |
28 | #define AGP8X_MODE_BIT 3 |
29 | #define AGP8X_MODE (1 << AGP8X_MODE_BIT) |
30 | |
31 | static unsigned long |
32 | parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, |
33 | int type); |
34 | |
35 | static struct _parisc_agp_info { |
36 | void __iomem *ioc_regs; |
37 | void __iomem *lba_regs; |
38 | |
39 | int lba_cap_offset; |
40 | |
41 | __le64 *gatt; |
42 | u64 gatt_entries; |
43 | |
44 | u64 gart_base; |
45 | u64 gart_size; |
46 | |
47 | int io_page_size; |
48 | int io_pages_per_kpage; |
49 | } parisc_agp_info; |
50 | |
51 | static struct gatt_mask parisc_agp_masks[] = |
52 | { |
53 | { |
54 | .mask = SBA_PDIR_VALID_BIT, |
55 | .type = 0 |
56 | } |
57 | }; |
58 | |
59 | static struct aper_size_info_fixed parisc_agp_sizes[] = |
60 | { |
61 | {0, 0, 0}, /* filled in by parisc_agp_fetch_size() */ |
62 | }; |
63 | |
64 | static int |
65 | parisc_agp_fetch_size(void) |
66 | { |
67 | int size; |
68 | |
69 | size = parisc_agp_info.gart_size / MB(1); |
70 | parisc_agp_sizes[0].size = size; |
71 | agp_bridge->current_size = (void *) &parisc_agp_sizes[0]; |
72 | |
73 | return size; |
74 | } |
75 | |
76 | static int |
77 | parisc_agp_configure(void) |
78 | { |
79 | struct _parisc_agp_info *info = &parisc_agp_info; |
80 | |
81 | agp_bridge->gart_bus_addr = info->gart_base; |
82 | agp_bridge->capndx = info->lba_cap_offset; |
83 | agp_bridge->mode = readl(addr: info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS); |
84 | |
85 | return 0; |
86 | } |
87 | |
88 | static void |
89 | parisc_agp_tlbflush(struct agp_memory *mem) |
90 | { |
91 | struct _parisc_agp_info *info = &parisc_agp_info; |
92 | |
93 | /* force fdc ops to be visible to IOMMU */ |
94 | asm_io_sync(); |
95 | |
96 | writeq(val: info->gart_base | ilog2(info->gart_size), addr: info->ioc_regs+IOC_PCOM); |
97 | readq(addr: info->ioc_regs+IOC_PCOM); /* flush */ |
98 | } |
99 | |
100 | static int |
101 | parisc_agp_create_gatt_table(struct agp_bridge_data *bridge) |
102 | { |
103 | struct _parisc_agp_info *info = &parisc_agp_info; |
104 | int i; |
105 | |
106 | for (i = 0; i < info->gatt_entries; i++) { |
107 | info->gatt[i] = cpu_to_le64(agp_bridge->scratch_page); |
108 | } |
109 | |
110 | return 0; |
111 | } |
112 | |
113 | static int |
114 | parisc_agp_free_gatt_table(struct agp_bridge_data *bridge) |
115 | { |
116 | struct _parisc_agp_info *info = &parisc_agp_info; |
117 | |
118 | info->gatt[0] = SBA_AGPGART_COOKIE; |
119 | |
120 | return 0; |
121 | } |
122 | |
123 | static int |
124 | parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type) |
125 | { |
126 | struct _parisc_agp_info *info = &parisc_agp_info; |
127 | int i, k; |
128 | off_t j, io_pg_start; |
129 | int io_pg_count; |
130 | |
131 | if (type != mem->type || |
132 | agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) { |
133 | return -EINVAL; |
134 | } |
135 | |
136 | io_pg_start = info->io_pages_per_kpage * pg_start; |
137 | io_pg_count = info->io_pages_per_kpage * mem->page_count; |
138 | if ((io_pg_start + io_pg_count) > info->gatt_entries) { |
139 | return -EINVAL; |
140 | } |
141 | |
142 | j = io_pg_start; |
143 | while (j < (io_pg_start + io_pg_count)) { |
144 | if (info->gatt[j]) |
145 | return -EBUSY; |
146 | j++; |
147 | } |
148 | |
149 | if (!mem->is_flushed) { |
150 | global_cache_flush(); |
151 | mem->is_flushed = true; |
152 | } |
153 | |
154 | for (i = 0, j = io_pg_start; i < mem->page_count; i++) { |
155 | unsigned long paddr; |
156 | |
157 | paddr = page_to_phys(mem->pages[i]); |
158 | for (k = 0; |
159 | k < info->io_pages_per_kpage; |
160 | k++, j++, paddr += info->io_page_size) { |
161 | info->gatt[j] = cpu_to_le64( |
162 | parisc_agp_mask_memory(agp_bridge, |
163 | paddr, type)); |
164 | asm_io_fdc(&info->gatt[j]); |
165 | } |
166 | } |
167 | |
168 | agp_bridge->driver->tlb_flush(mem); |
169 | |
170 | return 0; |
171 | } |
172 | |
173 | static int |
174 | parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type) |
175 | { |
176 | struct _parisc_agp_info *info = &parisc_agp_info; |
177 | int i, io_pg_start, io_pg_count; |
178 | |
179 | if (type != mem->type || |
180 | agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) { |
181 | return -EINVAL; |
182 | } |
183 | |
184 | io_pg_start = info->io_pages_per_kpage * pg_start; |
185 | io_pg_count = info->io_pages_per_kpage * mem->page_count; |
186 | for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) { |
187 | info->gatt[i] = cpu_to_le64(agp_bridge->scratch_page); |
188 | } |
189 | |
190 | agp_bridge->driver->tlb_flush(mem); |
191 | return 0; |
192 | } |
193 | |
194 | static unsigned long |
195 | parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, |
196 | int type) |
197 | { |
198 | unsigned ci; /* coherent index */ |
199 | dma_addr_t pa; |
200 | |
201 | pa = addr & IOVP_MASK; |
202 | asm("lci 0(%1), %0" : "=r" (ci) : "r" (phys_to_virt(address: pa))); |
203 | |
204 | pa |= (ci >> PAGE_SHIFT) & 0xff;/* move CI (8 bits) into lowest byte */ |
205 | pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ |
206 | |
207 | /* return native (big-endian) PDIR entry */ |
208 | return pa; |
209 | } |
210 | |
211 | static void |
212 | parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
213 | { |
214 | struct _parisc_agp_info *info = &parisc_agp_info; |
215 | u32 command; |
216 | |
217 | command = readl(addr: info->lba_regs + info->lba_cap_offset + PCI_AGP_STATUS); |
218 | |
219 | command = agp_collect_device_status(bridge, mode, command); |
220 | command |= 0x00000100; |
221 | |
222 | writel(val: command, addr: info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND); |
223 | |
224 | agp_device_command(command, agp_v3: (mode & AGP8X_MODE) != 0); |
225 | } |
226 | |
227 | static const struct agp_bridge_driver parisc_agp_driver = { |
228 | .owner = THIS_MODULE, |
229 | .size_type = FIXED_APER_SIZE, |
230 | .configure = parisc_agp_configure, |
231 | .fetch_size = parisc_agp_fetch_size, |
232 | .tlb_flush = parisc_agp_tlbflush, |
233 | .mask_memory = parisc_agp_mask_memory, |
234 | .masks = parisc_agp_masks, |
235 | .agp_enable = parisc_agp_enable, |
236 | .cache_flush = global_cache_flush, |
237 | .create_gatt_table = parisc_agp_create_gatt_table, |
238 | .free_gatt_table = parisc_agp_free_gatt_table, |
239 | .insert_memory = parisc_agp_insert_memory, |
240 | .remove_memory = parisc_agp_remove_memory, |
241 | .alloc_by_type = agp_generic_alloc_by_type, |
242 | .free_by_type = agp_generic_free_by_type, |
243 | .agp_alloc_page = agp_generic_alloc_page, |
244 | .agp_alloc_pages = agp_generic_alloc_pages, |
245 | .agp_destroy_page = agp_generic_destroy_page, |
246 | .agp_destroy_pages = agp_generic_destroy_pages, |
247 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
248 | .cant_use_aperture = true, |
249 | }; |
250 | |
251 | static int __init |
252 | agp_ioc_init(void __iomem *ioc_regs) |
253 | { |
254 | struct _parisc_agp_info *info = &parisc_agp_info; |
255 | u64 iova_base, io_tlb_ps; |
256 | __le64 *io_pdir; |
257 | int io_tlb_shift; |
258 | |
259 | printk(KERN_INFO DRVPFX "IO PDIR shared with sba_iommu\n" ); |
260 | |
261 | info->ioc_regs = ioc_regs; |
262 | |
263 | io_tlb_ps = readq(addr: info->ioc_regs+IOC_TCNFG); |
264 | switch (io_tlb_ps) { |
265 | case 0: io_tlb_shift = 12; break; |
266 | case 1: io_tlb_shift = 13; break; |
267 | case 2: io_tlb_shift = 14; break; |
268 | case 3: io_tlb_shift = 16; break; |
269 | default: |
270 | printk(KERN_ERR DRVPFX "Invalid IOTLB page size " |
271 | "configuration 0x%llx\n" , io_tlb_ps); |
272 | info->gatt = NULL; |
273 | info->gatt_entries = 0; |
274 | return -ENODEV; |
275 | } |
276 | info->io_page_size = 1 << io_tlb_shift; |
277 | info->io_pages_per_kpage = PAGE_SIZE / info->io_page_size; |
278 | |
279 | iova_base = readq(addr: info->ioc_regs+IOC_IBASE) & ~0x1; |
280 | info->gart_base = iova_base + PLUTO_IOVA_SIZE - PLUTO_GART_SIZE; |
281 | |
282 | info->gart_size = PLUTO_GART_SIZE; |
283 | info->gatt_entries = info->gart_size / info->io_page_size; |
284 | |
285 | io_pdir = phys_to_virt(readq(addr: info->ioc_regs+IOC_PDIR_BASE)); |
286 | info->gatt = &io_pdir[(PLUTO_IOVA_SIZE/2) >> PAGE_SHIFT]; |
287 | |
288 | if (info->gatt[0] != SBA_AGPGART_COOKIE) { |
289 | info->gatt = NULL; |
290 | info->gatt_entries = 0; |
291 | printk(KERN_ERR DRVPFX "No reserved IO PDIR entry found; " |
292 | "GART disabled\n" ); |
293 | return -ENODEV; |
294 | } |
295 | |
296 | return 0; |
297 | } |
298 | |
299 | static int __init |
300 | lba_find_capability(int cap) |
301 | { |
302 | struct _parisc_agp_info *info = &parisc_agp_info; |
303 | u16 status; |
304 | u8 pos, id; |
305 | int ttl = 48; |
306 | |
307 | status = readw(addr: info->lba_regs + PCI_STATUS); |
308 | if (!(status & PCI_STATUS_CAP_LIST)) |
309 | return 0; |
310 | pos = readb(addr: info->lba_regs + PCI_CAPABILITY_LIST); |
311 | while (ttl-- && pos >= 0x40) { |
312 | pos &= ~3; |
313 | id = readb(addr: info->lba_regs + pos + PCI_CAP_LIST_ID); |
314 | if (id == 0xff) |
315 | break; |
316 | if (id == cap) |
317 | return pos; |
318 | pos = readb(addr: info->lba_regs + pos + PCI_CAP_LIST_NEXT); |
319 | } |
320 | return 0; |
321 | } |
322 | |
323 | static int __init |
324 | agp_lba_init(void __iomem *lba_hpa) |
325 | { |
326 | struct _parisc_agp_info *info = &parisc_agp_info; |
327 | int cap; |
328 | |
329 | info->lba_regs = lba_hpa; |
330 | info->lba_cap_offset = lba_find_capability(PCI_CAP_ID_AGP); |
331 | |
332 | cap = readl(addr: lba_hpa + info->lba_cap_offset) & 0xff; |
333 | if (cap != PCI_CAP_ID_AGP) { |
334 | printk(KERN_ERR DRVPFX "Invalid capability ID 0x%02x at 0x%x\n" , |
335 | cap, info->lba_cap_offset); |
336 | return -ENODEV; |
337 | } |
338 | |
339 | return 0; |
340 | } |
341 | |
342 | static int __init |
343 | parisc_agp_setup(void __iomem *ioc_hpa, void __iomem *lba_hpa) |
344 | { |
345 | struct pci_dev *fake_bridge_dev = NULL; |
346 | struct agp_bridge_data *bridge; |
347 | int error = 0; |
348 | |
349 | fake_bridge_dev = pci_alloc_dev(NULL); |
350 | if (!fake_bridge_dev) { |
351 | error = -ENOMEM; |
352 | goto fail; |
353 | } |
354 | |
355 | error = agp_ioc_init(ioc_regs: ioc_hpa); |
356 | if (error) |
357 | goto fail; |
358 | |
359 | error = agp_lba_init(lba_hpa); |
360 | if (error) |
361 | goto fail; |
362 | |
363 | bridge = agp_alloc_bridge(); |
364 | if (!bridge) { |
365 | error = -ENOMEM; |
366 | goto fail; |
367 | } |
368 | bridge->driver = &parisc_agp_driver; |
369 | |
370 | fake_bridge_dev->vendor = PCI_VENDOR_ID_HP; |
371 | fake_bridge_dev->device = PCI_DEVICE_ID_HP_PCIX_LBA; |
372 | bridge->dev = fake_bridge_dev; |
373 | |
374 | error = agp_add_bridge(bridge); |
375 | if (error) |
376 | goto fail; |
377 | return 0; |
378 | |
379 | fail: |
380 | kfree(objp: fake_bridge_dev); |
381 | return error; |
382 | } |
383 | |
384 | static int __init |
385 | find_quicksilver(struct device *dev, void *data) |
386 | { |
387 | struct parisc_device **lba = data; |
388 | struct parisc_device *padev = to_parisc_device(dev); |
389 | |
390 | if (IS_QUICKSILVER(padev)) |
391 | *lba = padev; |
392 | |
393 | return 0; |
394 | } |
395 | |
396 | static int __init |
397 | parisc_agp_init(void) |
398 | { |
399 | int err = -1; |
400 | struct parisc_device *sba = NULL, *lba = NULL; |
401 | struct lba_device *lbadev = NULL; |
402 | |
403 | if (!sba_list) |
404 | goto out; |
405 | |
406 | /* Find our parent Pluto */ |
407 | sba = sba_list->dev; |
408 | if (!IS_PLUTO(sba)) { |
409 | printk(KERN_INFO DRVPFX "No Pluto found, so no AGPGART for you.\n" ); |
410 | goto out; |
411 | } |
412 | |
413 | /* Now search our Pluto for our precious AGP device... */ |
414 | device_for_each_child(dev: &sba->dev, data: &lba, fn: find_quicksilver); |
415 | |
416 | if (!lba) { |
417 | printk(KERN_INFO DRVPFX "No AGP devices found.\n" ); |
418 | goto out; |
419 | } |
420 | |
421 | lbadev = parisc_get_drvdata(lba); |
422 | |
423 | /* w00t, let's go find our cookies... */ |
424 | parisc_agp_setup(sba_list->ioc[0].ioc_hpa, lbadev->hba.base_addr); |
425 | |
426 | return 0; |
427 | |
428 | out: |
429 | return err; |
430 | } |
431 | |
432 | module_init(parisc_agp_init); |
433 | |
434 | MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>" ); |
435 | MODULE_LICENSE("GPL" ); |
436 | |