1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Actions Semi Owl S500 SoC clock driver |
4 | * |
5 | * Copyright (c) 2014 Actions Semi Inc. |
6 | * Author: David Liu <liuwei@actions-semi.com> |
7 | * |
8 | * Copyright (c) 2018 Linaro Ltd. |
9 | * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
10 | * |
11 | * Copyright (c) 2018 LSI-TEC - Caninos Loucos |
12 | * Author: Edgar Bernardi Righi <edgar.righi@lsitec.org.br> |
13 | */ |
14 | |
15 | #include <linux/clk-provider.h> |
16 | #include <linux/platform_device.h> |
17 | |
18 | #include "owl-common.h" |
19 | #include "owl-composite.h" |
20 | #include "owl-divider.h" |
21 | #include "owl-factor.h" |
22 | #include "owl-fixed-factor.h" |
23 | #include "owl-gate.h" |
24 | #include "owl-mux.h" |
25 | #include "owl-pll.h" |
26 | #include "owl-reset.h" |
27 | |
28 | #include <dt-bindings/clock/actions,s500-cmu.h> |
29 | #include <dt-bindings/reset/actions,s500-reset.h> |
30 | |
31 | #define CMU_COREPLL (0x0000) |
32 | #define CMU_DEVPLL (0x0004) |
33 | #define CMU_DDRPLL (0x0008) |
34 | #define CMU_NANDPLL (0x000C) |
35 | #define CMU_DISPLAYPLL (0x0010) |
36 | #define CMU_AUDIOPLL (0x0014) |
37 | #define CMU_TVOUTPLL (0x0018) |
38 | #define CMU_BUSCLK (0x001C) |
39 | #define CMU_SENSORCLK (0x0020) |
40 | #define CMU_LCDCLK (0x0024) |
41 | #define CMU_DSICLK (0x0028) |
42 | #define CMU_CSICLK (0x002C) |
43 | #define CMU_DECLK (0x0030) |
44 | #define CMU_BISPCLK (0x0034) |
45 | #define CMU_BUSCLK1 (0x0038) |
46 | #define CMU_VDECLK (0x0040) |
47 | #define CMU_VCECLK (0x0044) |
48 | #define CMU_NANDCCLK (0x004C) |
49 | #define CMU_SD0CLK (0x0050) |
50 | #define CMU_SD1CLK (0x0054) |
51 | #define CMU_SD2CLK (0x0058) |
52 | #define CMU_UART0CLK (0x005C) |
53 | #define CMU_UART1CLK (0x0060) |
54 | #define CMU_UART2CLK (0x0064) |
55 | #define CMU_PWM4CLK (0x0068) |
56 | #define CMU_PWM5CLK (0x006C) |
57 | #define CMU_PWM0CLK (0x0070) |
58 | #define CMU_PWM1CLK (0x0074) |
59 | #define CMU_PWM2CLK (0x0078) |
60 | #define CMU_PWM3CLK (0x007C) |
61 | #define CMU_USBPLL (0x0080) |
62 | #define CMU_ETHERNETPLL (0x0084) |
63 | #define CMU_CVBSPLL (0x0088) |
64 | #define CMU_LENSCLK (0x008C) |
65 | #define CMU_GPU3DCLK (0x0090) |
66 | #define CMU_CORECTL (0x009C) |
67 | #define CMU_DEVCLKEN0 (0x00A0) |
68 | #define CMU_DEVCLKEN1 (0x00A4) |
69 | #define CMU_DEVRST0 (0x00A8) |
70 | #define CMU_DEVRST1 (0x00AC) |
71 | #define CMU_UART3CLK (0x00B0) |
72 | #define CMU_UART4CLK (0x00B4) |
73 | #define CMU_UART5CLK (0x00B8) |
74 | #define CMU_UART6CLK (0x00BC) |
75 | #define CMU_SSCLK (0x00C0) |
76 | #define CMU_DIGITALDEBUG (0x00D0) |
77 | #define CMU_ANALOGDEBUG (0x00D4) |
78 | #define CMU_COREPLLDEBUG (0x00D8) |
79 | #define CMU_DEVPLLDEBUG (0x00DC) |
80 | #define CMU_DDRPLLDEBUG (0x00E0) |
81 | #define CMU_NANDPLLDEBUG (0x00E4) |
82 | #define CMU_DISPLAYPLLDEBUG (0x00E8) |
83 | #define CMU_TVOUTPLLDEBUG (0x00EC) |
84 | #define CMU_DEEPCOLORPLLDEBUG (0x00F4) |
85 | #define CMU_AUDIOPLL_ETHPLLDEBUG (0x00F8) |
86 | #define CMU_CVBSPLLDEBUG (0x00FC) |
87 | |
88 | #define OWL_S500_COREPLL_DELAY (150) |
89 | #define OWL_S500_DDRPLL_DELAY (63) |
90 | #define OWL_S500_DEVPLL_DELAY (28) |
91 | #define OWL_S500_NANDPLL_DELAY (44) |
92 | #define OWL_S500_DISPLAYPLL_DELAY (57) |
93 | #define OWL_S500_ETHERNETPLL_DELAY (25) |
94 | #define OWL_S500_AUDIOPLL_DELAY (100) |
95 | |
96 | static const struct clk_pll_table clk_audio_pll_table[] = { |
97 | { 0, 45158400 }, { 1, 49152000 }, |
98 | { /* sentinel */ } |
99 | }; |
100 | |
101 | /* pll clocks */ |
102 | static OWL_PLL_NO_PARENT_DELAY(ethernet_pll_clk, "ethernet_pll_clk" , CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, OWL_S500_ETHERNETPLL_DELAY, NULL, CLK_IGNORE_UNUSED); |
103 | static OWL_PLL_NO_PARENT_DELAY(core_pll_clk, "core_pll_clk" , CMU_COREPLL, 12000000, 9, 0, 8, 4, 134, OWL_S500_COREPLL_DELAY, NULL, CLK_IGNORE_UNUSED); |
104 | static OWL_PLL_NO_PARENT_DELAY(ddr_pll_clk, "ddr_pll_clk" , CMU_DDRPLL, 12000000, 8, 0, 8, 1, 67, OWL_S500_DDRPLL_DELAY, NULL, CLK_IGNORE_UNUSED); |
105 | static OWL_PLL_NO_PARENT_DELAY(nand_pll_clk, "nand_pll_clk" , CMU_NANDPLL, 6000000, 8, 0, 7, 2, 86, OWL_S500_NANDPLL_DELAY, NULL, CLK_IGNORE_UNUSED); |
106 | static OWL_PLL_NO_PARENT_DELAY(display_pll_clk, "display_pll_clk" , CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 126, OWL_S500_DISPLAYPLL_DELAY, NULL, CLK_IGNORE_UNUSED); |
107 | static OWL_PLL_NO_PARENT_DELAY(dev_pll_clk, "dev_pll_clk" , CMU_DEVPLL, 6000000, 8, 0, 7, 8, 126, OWL_S500_DEVPLL_DELAY, NULL, CLK_IGNORE_UNUSED); |
108 | static OWL_PLL_NO_PARENT_DELAY(audio_pll_clk, "audio_pll_clk" , CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, OWL_S500_AUDIOPLL_DELAY, clk_audio_pll_table, CLK_IGNORE_UNUSED); |
109 | |
110 | static const char * const dev_clk_mux_p[] = { "hosc" , "dev_pll_clk" }; |
111 | static const char * const bisp_clk_mux_p[] = { "display_pll_clk" , "dev_clk" }; |
112 | static const char * const sensor_clk_mux_p[] = { "hosc" , "bisp_clk" }; |
113 | static const char * const sd_clk_mux_p[] = { "dev_clk" , "nand_pll_clk" }; |
114 | static const char * const pwm_clk_mux_p[] = { "losc" , "hosc" }; |
115 | static const char * const ahbprediv_clk_mux_p[] = { "dev_clk" , "display_pll_clk" , "nand_pll_clk" , "ddr_pll_clk" }; |
116 | static const char * const nic_clk_mux_p[] = { "dev_clk" , "display_pll_clk" , "nand_pll_clk" , "ddr_pll_clk" }; |
117 | static const char * const uart_clk_mux_p[] = { "hosc" , "dev_pll_clk" }; |
118 | static const char * const de_clk_mux_p[] = { "display_pll_clk" , "dev_clk" }; |
119 | static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" }; |
120 | static const char * const hde_clk_mux_p[] = { "dev_clk" , "display_pll_clk" , "nand_pll_clk" , "ddr_pll_clk" }; |
121 | static const char * const nand_clk_mux_p[] = { "nand_pll_clk" , "display_pll_clk" , "dev_clk" , "ddr_pll_clk" }; |
122 | |
123 | static struct clk_factor_table sd_factor_table[] = { |
124 | /* bit0 ~ 4 */ |
125 | { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 }, |
126 | { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 }, |
127 | { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 }, |
128 | { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 }, |
129 | { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 }, |
130 | { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 }, |
131 | { 24, 1, 25 }, |
132 | |
133 | /* bit8: /128 */ |
134 | { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 }, |
135 | { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 }, |
136 | { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 }, |
137 | { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 }, |
138 | { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 }, |
139 | { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 }, |
140 | { 280, 1, 25 * 128 }, |
141 | { /* sentinel */ } |
142 | }; |
143 | |
144 | static struct clk_factor_table de_factor_table[] = { |
145 | { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, |
146 | { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, |
147 | { 8, 1, 12 }, |
148 | { /* sentinel */ } |
149 | }; |
150 | |
151 | static struct clk_factor_table hde_factor_table[] = { |
152 | { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, |
153 | { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, |
154 | { /* sentinel */ } |
155 | }; |
156 | |
157 | static struct clk_div_table rmii_ref_div_table[] = { |
158 | { 0, 4 }, { 1, 10 }, |
159 | { /* sentinel */ } |
160 | }; |
161 | |
162 | static struct clk_div_table std12rate_div_table[] = { |
163 | { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, |
164 | { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, |
165 | { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, |
166 | { /* sentinel */ } |
167 | }; |
168 | |
169 | static struct clk_div_table i2s_div_table[] = { |
170 | { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, |
171 | { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 }, |
172 | { 8, 24 }, |
173 | { /* sentinel */ } |
174 | }; |
175 | |
176 | static struct clk_div_table nand_div_table[] = { |
177 | { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 }, |
178 | { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 }, |
179 | { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 }, |
180 | { /* sentinel */ } |
181 | }; |
182 | |
183 | /* mux clock */ |
184 | static OWL_MUX(dev_clk, "dev_clk" , dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); |
185 | |
186 | /* gate clocks */ |
187 | static OWL_GATE(gpio_clk, "gpio_clk" , "apb_clk" , CMU_DEVCLKEN0, 18, 0, 0); |
188 | static OWL_GATE(dmac_clk, "dmac_clk" , "h_clk" , CMU_DEVCLKEN0, 1, 0, 0); |
189 | static OWL_GATE(spi0_clk, "spi0_clk" , "ahb_clk" , CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED); |
190 | static OWL_GATE(spi1_clk, "spi1_clk" , "ahb_clk" , CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED); |
191 | static OWL_GATE(spi2_clk, "spi2_clk" , "ahb_clk" , CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED); |
192 | static OWL_GATE(spi3_clk, "spi3_clk" , "ahb_clk" , CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED); |
193 | static OWL_GATE(timer_clk, "timer_clk" , "hosc" , CMU_DEVCLKEN1, 27, 0, 0); |
194 | static OWL_GATE(hdmi_clk, "hdmi_clk" , "hosc" , CMU_DEVCLKEN1, 3, 0, 0); |
195 | |
196 | /* divider clocks */ |
197 | static OWL_DIVIDER(h_clk, "h_clk" , "ahbprediv_clk" , CMU_BUSCLK1, 2, 2, NULL, 0, 0); |
198 | static OWL_DIVIDER(apb_clk, "apb_clk" , "nic_clk" , CMU_BUSCLK1, 14, 2, NULL, 0, 0); |
199 | static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk" , "ethernet_pll_clk" , CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); |
200 | |
201 | /* factor clocks */ |
202 | static OWL_FACTOR(de1_clk, "de_clk1" , "de_clk" , CMU_DECLK, 0, 4, de_factor_table, 0, 0); |
203 | static OWL_FACTOR(de2_clk, "de_clk2" , "de_clk" , CMU_DECLK, 4, 4, de_factor_table, 0, 0); |
204 | |
205 | /* composite clocks */ |
206 | static OWL_COMP_DIV(nic_clk, "nic_clk" , nic_clk_mux_p, |
207 | OWL_MUX_HW(CMU_BUSCLK1, 4, 3), |
208 | { 0 }, |
209 | OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL), |
210 | 0); |
211 | |
212 | static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk" , ahbprediv_clk_mux_p, |
213 | OWL_MUX_HW(CMU_BUSCLK1, 8, 3), |
214 | { 0 }, |
215 | OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL), |
216 | CLK_SET_RATE_PARENT); |
217 | |
218 | static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk" , "h_clk" , |
219 | { 0 }, |
220 | 1, 1, 0); |
221 | |
222 | static OWL_COMP_FACTOR(vce_clk, "vce_clk" , hde_clk_mux_p, |
223 | OWL_MUX_HW(CMU_VCECLK, 4, 2), |
224 | OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), |
225 | OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table), |
226 | 0); |
227 | |
228 | static OWL_COMP_FACTOR(vde_clk, "vde_clk" , hde_clk_mux_p, |
229 | OWL_MUX_HW(CMU_VDECLK, 4, 2), |
230 | OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0), |
231 | OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table), |
232 | 0); |
233 | |
234 | static OWL_COMP_DIV(bisp_clk, "bisp_clk" , bisp_clk_mux_p, |
235 | OWL_MUX_HW(CMU_BISPCLK, 4, 1), |
236 | OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), |
237 | OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table), |
238 | 0); |
239 | |
240 | static OWL_COMP_DIV(sensor0_clk, "sensor0_clk" , sensor_clk_mux_p, |
241 | OWL_MUX_HW(CMU_SENSORCLK, 4, 1), |
242 | OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), |
243 | OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table), |
244 | 0); |
245 | |
246 | static OWL_COMP_DIV(sensor1_clk, "sensor1_clk" , sensor_clk_mux_p, |
247 | OWL_MUX_HW(CMU_SENSORCLK, 4, 1), |
248 | OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), |
249 | OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table), |
250 | 0); |
251 | |
252 | static OWL_COMP_FACTOR(sd0_clk, "sd0_clk" , sd_clk_mux_p, |
253 | OWL_MUX_HW(CMU_SD0CLK, 9, 1), |
254 | OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0), |
255 | OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table), |
256 | 0); |
257 | |
258 | static OWL_COMP_FACTOR(sd1_clk, "sd1_clk" , sd_clk_mux_p, |
259 | OWL_MUX_HW(CMU_SD1CLK, 9, 1), |
260 | OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0), |
261 | OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table), |
262 | 0); |
263 | |
264 | static OWL_COMP_FACTOR(sd2_clk, "sd2_clk" , sd_clk_mux_p, |
265 | OWL_MUX_HW(CMU_SD2CLK, 9, 1), |
266 | OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0), |
267 | OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table), |
268 | 0); |
269 | |
270 | static OWL_COMP_DIV(pwm0_clk, "pwm0_clk" , pwm_clk_mux_p, |
271 | OWL_MUX_HW(CMU_PWM0CLK, 12, 1), |
272 | OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0), |
273 | OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL), |
274 | 0); |
275 | |
276 | static OWL_COMP_DIV(pwm1_clk, "pwm1_clk" , pwm_clk_mux_p, |
277 | OWL_MUX_HW(CMU_PWM1CLK, 12, 1), |
278 | OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0), |
279 | OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL), |
280 | 0); |
281 | |
282 | static OWL_COMP_DIV(pwm2_clk, "pwm2_clk" , pwm_clk_mux_p, |
283 | OWL_MUX_HW(CMU_PWM2CLK, 12, 1), |
284 | OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0), |
285 | OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL), |
286 | 0); |
287 | |
288 | static OWL_COMP_DIV(pwm3_clk, "pwm3_clk" , pwm_clk_mux_p, |
289 | OWL_MUX_HW(CMU_PWM3CLK, 12, 1), |
290 | OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0), |
291 | OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL), |
292 | 0); |
293 | |
294 | static OWL_COMP_DIV(pwm4_clk, "pwm4_clk" , pwm_clk_mux_p, |
295 | OWL_MUX_HW(CMU_PWM4CLK, 12, 1), |
296 | OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0), |
297 | OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL), |
298 | 0); |
299 | |
300 | static OWL_COMP_DIV(pwm5_clk, "pwm5_clk" , pwm_clk_mux_p, |
301 | OWL_MUX_HW(CMU_PWM5CLK, 12, 1), |
302 | OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0), |
303 | OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL), |
304 | 0); |
305 | |
306 | static OWL_COMP_PASS(de_clk, "de_clk" , de_clk_mux_p, |
307 | OWL_MUX_HW(CMU_DECLK, 12, 1), |
308 | OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0), |
309 | 0); |
310 | |
311 | static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk" , "ethernet_pll_clk" , |
312 | OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0), |
313 | 1, 5, 0); |
314 | |
315 | static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk" , "ethernet_pll_clk" , |
316 | OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0), |
317 | 1, 5, 0); |
318 | |
319 | static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk" , "ethernet_pll_clk" , |
320 | OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0), |
321 | 1, 5, 0); |
322 | |
323 | static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk" , "ethernet_pll_clk" , |
324 | OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), |
325 | 1, 5, 0); |
326 | |
327 | static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk" , "ethernet_pll_clk" , |
328 | OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0), |
329 | 1, 20, 0); |
330 | |
331 | static OWL_COMP_DIV(uart0_clk, "uart0_clk" , uart_clk_mux_p, |
332 | OWL_MUX_HW(CMU_UART0CLK, 16, 1), |
333 | OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), |
334 | OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), |
335 | CLK_IGNORE_UNUSED); |
336 | |
337 | static OWL_COMP_DIV(uart1_clk, "uart1_clk" , uart_clk_mux_p, |
338 | OWL_MUX_HW(CMU_UART1CLK, 16, 1), |
339 | OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0), |
340 | OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), |
341 | CLK_IGNORE_UNUSED); |
342 | |
343 | static OWL_COMP_DIV(uart2_clk, "uart2_clk" , uart_clk_mux_p, |
344 | OWL_MUX_HW(CMU_UART2CLK, 16, 1), |
345 | OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), |
346 | OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), |
347 | CLK_IGNORE_UNUSED); |
348 | |
349 | static OWL_COMP_DIV(uart3_clk, "uart3_clk" , uart_clk_mux_p, |
350 | OWL_MUX_HW(CMU_UART3CLK, 16, 1), |
351 | OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), |
352 | OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), |
353 | CLK_IGNORE_UNUSED); |
354 | |
355 | static OWL_COMP_DIV(uart4_clk, "uart4_clk" , uart_clk_mux_p, |
356 | OWL_MUX_HW(CMU_UART4CLK, 16, 1), |
357 | OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), |
358 | OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), |
359 | CLK_IGNORE_UNUSED); |
360 | |
361 | static OWL_COMP_DIV(uart5_clk, "uart5_clk" , uart_clk_mux_p, |
362 | OWL_MUX_HW(CMU_UART5CLK, 16, 1), |
363 | OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), |
364 | OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), |
365 | CLK_IGNORE_UNUSED); |
366 | |
367 | static OWL_COMP_DIV(uart6_clk, "uart6_clk" , uart_clk_mux_p, |
368 | OWL_MUX_HW(CMU_UART6CLK, 16, 1), |
369 | OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), |
370 | OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), |
371 | CLK_IGNORE_UNUSED); |
372 | |
373 | static OWL_COMP_DIV(i2srx_clk, "i2srx_clk" , i2s_clk_mux_p, |
374 | OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), |
375 | OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0), |
376 | OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table), |
377 | 0); |
378 | |
379 | static OWL_COMP_DIV(i2stx_clk, "i2stx_clk" , i2s_clk_mux_p, |
380 | OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), |
381 | OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0), |
382 | OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table), |
383 | 0); |
384 | |
385 | static OWL_COMP_DIV(hdmia_clk, "hdmia_clk" , i2s_clk_mux_p, |
386 | OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), |
387 | OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0), |
388 | OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table), |
389 | 0); |
390 | |
391 | static OWL_COMP_DIV(spdif_clk, "spdif_clk" , i2s_clk_mux_p, |
392 | OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), |
393 | OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0), |
394 | OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table), |
395 | 0); |
396 | |
397 | static OWL_COMP_DIV(nand_clk, "nand_clk" , nand_clk_mux_p, |
398 | OWL_MUX_HW(CMU_NANDCCLK, 8, 2), |
399 | OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0), |
400 | OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table), |
401 | CLK_SET_RATE_PARENT); |
402 | |
403 | static OWL_COMP_DIV(ecc_clk, "ecc_clk" , nand_clk_mux_p, |
404 | OWL_MUX_HW(CMU_NANDCCLK, 8, 2), |
405 | OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0), |
406 | OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table), |
407 | CLK_SET_RATE_PARENT); |
408 | |
409 | static struct owl_clk_common *s500_clks[] = { |
410 | ðernet_pll_clk.common, |
411 | &core_pll_clk.common, |
412 | &ddr_pll_clk.common, |
413 | &dev_pll_clk.common, |
414 | &nand_pll_clk.common, |
415 | &audio_pll_clk.common, |
416 | &display_pll_clk.common, |
417 | &dev_clk.common, |
418 | &timer_clk.common, |
419 | &i2c0_clk.common, |
420 | &i2c1_clk.common, |
421 | &i2c2_clk.common, |
422 | &i2c3_clk.common, |
423 | &uart0_clk.common, |
424 | &uart1_clk.common, |
425 | &uart2_clk.common, |
426 | &uart3_clk.common, |
427 | &uart4_clk.common, |
428 | &uart5_clk.common, |
429 | &uart6_clk.common, |
430 | &pwm0_clk.common, |
431 | &pwm1_clk.common, |
432 | &pwm2_clk.common, |
433 | &pwm3_clk.common, |
434 | &pwm4_clk.common, |
435 | &pwm5_clk.common, |
436 | &sensor0_clk.common, |
437 | &sensor1_clk.common, |
438 | &sd0_clk.common, |
439 | &sd1_clk.common, |
440 | &sd2_clk.common, |
441 | &bisp_clk.common, |
442 | &ahb_clk.common, |
443 | &ahbprediv_clk.common, |
444 | &h_clk.common, |
445 | &spi0_clk.common, |
446 | &spi1_clk.common, |
447 | &spi2_clk.common, |
448 | &spi3_clk.common, |
449 | &rmii_ref_clk.common, |
450 | &de_clk.common, |
451 | &de1_clk.common, |
452 | &de2_clk.common, |
453 | &i2srx_clk.common, |
454 | &i2stx_clk.common, |
455 | &hdmia_clk.common, |
456 | &hdmi_clk.common, |
457 | &vce_clk.common, |
458 | &vde_clk.common, |
459 | &spdif_clk.common, |
460 | &nand_clk.common, |
461 | &ecc_clk.common, |
462 | &apb_clk.common, |
463 | &dmac_clk.common, |
464 | &gpio_clk.common, |
465 | &nic_clk.common, |
466 | ðernet_clk.common, |
467 | }; |
468 | |
469 | static struct clk_hw_onecell_data s500_hw_clks = { |
470 | .hws = { |
471 | [CLK_ETHERNET_PLL] = ðernet_pll_clk.common.hw, |
472 | [CLK_CORE_PLL] = &core_pll_clk.common.hw, |
473 | [CLK_DDR_PLL] = &ddr_pll_clk.common.hw, |
474 | [CLK_NAND_PLL] = &nand_pll_clk.common.hw, |
475 | [CLK_DISPLAY_PLL] = &display_pll_clk.common.hw, |
476 | [CLK_DEV_PLL] = &dev_pll_clk.common.hw, |
477 | [CLK_AUDIO_PLL] = &audio_pll_clk.common.hw, |
478 | [CLK_TIMER] = &timer_clk.common.hw, |
479 | [CLK_DEV] = &dev_clk.common.hw, |
480 | [CLK_DE] = &de_clk.common.hw, |
481 | [CLK_DE1] = &de1_clk.common.hw, |
482 | [CLK_DE2] = &de2_clk.common.hw, |
483 | [CLK_I2C0] = &i2c0_clk.common.hw, |
484 | [CLK_I2C1] = &i2c1_clk.common.hw, |
485 | [CLK_I2C2] = &i2c2_clk.common.hw, |
486 | [CLK_I2C3] = &i2c3_clk.common.hw, |
487 | [CLK_I2SRX] = &i2srx_clk.common.hw, |
488 | [CLK_I2STX] = &i2stx_clk.common.hw, |
489 | [CLK_UART0] = &uart0_clk.common.hw, |
490 | [CLK_UART1] = &uart1_clk.common.hw, |
491 | [CLK_UART2] = &uart2_clk.common.hw, |
492 | [CLK_UART3] = &uart3_clk.common.hw, |
493 | [CLK_UART4] = &uart4_clk.common.hw, |
494 | [CLK_UART5] = &uart5_clk.common.hw, |
495 | [CLK_UART6] = &uart6_clk.common.hw, |
496 | [CLK_PWM0] = &pwm0_clk.common.hw, |
497 | [CLK_PWM1] = &pwm1_clk.common.hw, |
498 | [CLK_PWM2] = &pwm2_clk.common.hw, |
499 | [CLK_PWM3] = &pwm3_clk.common.hw, |
500 | [CLK_PWM4] = &pwm4_clk.common.hw, |
501 | [CLK_PWM5] = &pwm5_clk.common.hw, |
502 | [CLK_SENSOR0] = &sensor0_clk.common.hw, |
503 | [CLK_SENSOR1] = &sensor1_clk.common.hw, |
504 | [CLK_SD0] = &sd0_clk.common.hw, |
505 | [CLK_SD1] = &sd1_clk.common.hw, |
506 | [CLK_SD2] = &sd2_clk.common.hw, |
507 | [CLK_BISP] = &bisp_clk.common.hw, |
508 | [CLK_SPI0] = &spi0_clk.common.hw, |
509 | [CLK_SPI1] = &spi1_clk.common.hw, |
510 | [CLK_SPI2] = &spi2_clk.common.hw, |
511 | [CLK_SPI3] = &spi3_clk.common.hw, |
512 | [CLK_AHB] = &ahb_clk.common.hw, |
513 | [CLK_H] = &h_clk.common.hw, |
514 | [CLK_AHBPREDIV] = &ahbprediv_clk.common.hw, |
515 | [CLK_RMII_REF] = &rmii_ref_clk.common.hw, |
516 | [CLK_HDMI_AUDIO] = &hdmia_clk.common.hw, |
517 | [CLK_HDMI] = &hdmi_clk.common.hw, |
518 | [CLK_VDE] = &vde_clk.common.hw, |
519 | [CLK_VCE] = &vce_clk.common.hw, |
520 | [CLK_SPDIF] = &spdif_clk.common.hw, |
521 | [CLK_NAND] = &nand_clk.common.hw, |
522 | [CLK_ECC] = &ecc_clk.common.hw, |
523 | [CLK_APB] = &apb_clk.common.hw, |
524 | [CLK_DMAC] = &dmac_clk.common.hw, |
525 | [CLK_GPIO] = &gpio_clk.common.hw, |
526 | [CLK_NIC] = &nic_clk.common.hw, |
527 | [CLK_ETHERNET] = ðernet_clk.common.hw, |
528 | }, |
529 | .num = CLK_NR_CLKS, |
530 | }; |
531 | |
532 | static const struct owl_reset_map s500_resets[] = { |
533 | [RESET_DMAC] = { CMU_DEVRST0, BIT(0) }, |
534 | [RESET_NORIF] = { CMU_DEVRST0, BIT(1) }, |
535 | [RESET_DDR] = { CMU_DEVRST0, BIT(2) }, |
536 | [RESET_NANDC] = { CMU_DEVRST0, BIT(3) }, |
537 | [RESET_SD0] = { CMU_DEVRST0, BIT(4) }, |
538 | [RESET_SD1] = { CMU_DEVRST0, BIT(5) }, |
539 | [RESET_PCM1] = { CMU_DEVRST0, BIT(6) }, |
540 | [RESET_DE] = { CMU_DEVRST0, BIT(7) }, |
541 | [RESET_LCD] = { CMU_DEVRST0, BIT(8) }, |
542 | [RESET_SD2] = { CMU_DEVRST0, BIT(9) }, |
543 | [RESET_DSI] = { CMU_DEVRST0, BIT(10) }, |
544 | [RESET_CSI] = { CMU_DEVRST0, BIT(11) }, |
545 | [RESET_BISP] = { CMU_DEVRST0, BIT(12) }, |
546 | [RESET_KEY] = { CMU_DEVRST0, BIT(14) }, |
547 | [RESET_GPIO] = { CMU_DEVRST0, BIT(15) }, |
548 | [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) }, |
549 | [RESET_PCM0] = { CMU_DEVRST0, BIT(18) }, |
550 | [RESET_VDE] = { CMU_DEVRST0, BIT(19) }, |
551 | [RESET_VCE] = { CMU_DEVRST0, BIT(20) }, |
552 | [RESET_GPU3D] = { CMU_DEVRST0, BIT(22) }, |
553 | [RESET_NIC301] = { CMU_DEVRST0, BIT(23) }, |
554 | [RESET_LENS] = { CMU_DEVRST0, BIT(26) }, |
555 | [RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) }, |
556 | [RESET_USB2_0] = { CMU_DEVRST1, BIT(0) }, |
557 | [RESET_TVOUT] = { CMU_DEVRST1, BIT(1) }, |
558 | [RESET_HDMI] = { CMU_DEVRST1, BIT(2) }, |
559 | [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) }, |
560 | [RESET_UART6] = { CMU_DEVRST1, BIT(4) }, |
561 | [RESET_UART0] = { CMU_DEVRST1, BIT(5) }, |
562 | [RESET_UART1] = { CMU_DEVRST1, BIT(6) }, |
563 | [RESET_UART2] = { CMU_DEVRST1, BIT(7) }, |
564 | [RESET_SPI0] = { CMU_DEVRST1, BIT(8) }, |
565 | [RESET_SPI1] = { CMU_DEVRST1, BIT(9) }, |
566 | [RESET_SPI2] = { CMU_DEVRST1, BIT(10) }, |
567 | [RESET_SPI3] = { CMU_DEVRST1, BIT(11) }, |
568 | [RESET_I2C0] = { CMU_DEVRST1, BIT(12) }, |
569 | [RESET_I2C1] = { CMU_DEVRST1, BIT(13) }, |
570 | [RESET_USB3] = { CMU_DEVRST1, BIT(14) }, |
571 | [RESET_UART3] = { CMU_DEVRST1, BIT(15) }, |
572 | [RESET_UART4] = { CMU_DEVRST1, BIT(16) }, |
573 | [RESET_UART5] = { CMU_DEVRST1, BIT(17) }, |
574 | [RESET_I2C2] = { CMU_DEVRST1, BIT(18) }, |
575 | [RESET_I2C3] = { CMU_DEVRST1, BIT(19) }, |
576 | [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) }, |
577 | [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) }, |
578 | [RESET_USB2_1] = { CMU_DEVRST1, BIT(22) }, |
579 | [RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) }, |
580 | [RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) }, |
581 | [RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) }, |
582 | [RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) }, |
583 | [RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) }, |
584 | [RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) }, |
585 | [RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) }, |
586 | [RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) }, |
587 | }; |
588 | |
589 | static struct owl_clk_desc s500_clk_desc = { |
590 | .clks = s500_clks, |
591 | .num_clks = ARRAY_SIZE(s500_clks), |
592 | |
593 | .hw_clks = &s500_hw_clks, |
594 | |
595 | .resets = s500_resets, |
596 | .num_resets = ARRAY_SIZE(s500_resets), |
597 | }; |
598 | |
599 | static int s500_clk_probe(struct platform_device *pdev) |
600 | { |
601 | struct owl_clk_desc *desc; |
602 | struct owl_reset *reset; |
603 | int ret; |
604 | |
605 | desc = &s500_clk_desc; |
606 | owl_clk_regmap_init(pdev, desc); |
607 | |
608 | reset = devm_kzalloc(dev: &pdev->dev, size: sizeof(*reset), GFP_KERNEL); |
609 | if (!reset) |
610 | return -ENOMEM; |
611 | |
612 | reset->rcdev.of_node = pdev->dev.of_node; |
613 | reset->rcdev.ops = &owl_reset_ops; |
614 | reset->rcdev.nr_resets = desc->num_resets; |
615 | reset->reset_map = desc->resets; |
616 | reset->regmap = desc->regmap; |
617 | |
618 | ret = devm_reset_controller_register(dev: &pdev->dev, rcdev: &reset->rcdev); |
619 | if (ret) |
620 | dev_err(&pdev->dev, "Failed to register reset controller\n" ); |
621 | |
622 | return owl_clk_probe(dev: &pdev->dev, hw_clks: desc->hw_clks); |
623 | } |
624 | |
625 | static const struct of_device_id s500_clk_of_match[] = { |
626 | { .compatible = "actions,s500-cmu" , }, |
627 | { /* sentinel */ } |
628 | }; |
629 | |
630 | static struct platform_driver s500_clk_driver = { |
631 | .probe = s500_clk_probe, |
632 | .driver = { |
633 | .name = "s500-cmu" , |
634 | .of_match_table = s500_clk_of_match, |
635 | }, |
636 | }; |
637 | |
638 | static int __init s500_clk_init(void) |
639 | { |
640 | return platform_driver_register(&s500_clk_driver); |
641 | } |
642 | core_initcall(s500_clk_init); |
643 | |