1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2014 Oleksij Rempel <linux@rempel-privat.de>. |
4 | */ |
5 | |
6 | #include <linux/clk.h> |
7 | #include <linux/clkdev.h> |
8 | #include <linux/err.h> |
9 | #include <linux/io.h> |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/spinlock.h> |
12 | #include <linux/of.h> |
13 | #include <linux/of_address.h> |
14 | #include <dt-bindings/clock/alphascale,asm9260.h> |
15 | |
16 | #define HW_AHBCLKCTRL0 0x0020 |
17 | #define HW_AHBCLKCTRL1 0x0030 |
18 | #define HW_SYSPLLCTRL 0x0100 |
19 | #define HW_MAINCLKSEL 0x0120 |
20 | #define HW_MAINCLKUEN 0x0124 |
21 | #define HW_UARTCLKSEL 0x0128 |
22 | #define HW_UARTCLKUEN 0x012c |
23 | #define HW_I2S0CLKSEL 0x0130 |
24 | #define HW_I2S0CLKUEN 0x0134 |
25 | #define HW_I2S1CLKSEL 0x0138 |
26 | #define HW_I2S1CLKUEN 0x013c |
27 | #define HW_WDTCLKSEL 0x0160 |
28 | #define HW_WDTCLKUEN 0x0164 |
29 | #define HW_CLKOUTCLKSEL 0x0170 |
30 | #define HW_CLKOUTCLKUEN 0x0174 |
31 | #define HW_CPUCLKDIV 0x017c |
32 | #define HW_SYSAHBCLKDIV 0x0180 |
33 | #define HW_I2S0MCLKDIV 0x0190 |
34 | #define HW_I2S0SCLKDIV 0x0194 |
35 | #define HW_I2S1MCLKDIV 0x0188 |
36 | #define HW_I2S1SCLKDIV 0x018c |
37 | #define HW_UART0CLKDIV 0x0198 |
38 | #define HW_UART1CLKDIV 0x019c |
39 | #define HW_UART2CLKDIV 0x01a0 |
40 | #define HW_UART3CLKDIV 0x01a4 |
41 | #define HW_UART4CLKDIV 0x01a8 |
42 | #define HW_UART5CLKDIV 0x01ac |
43 | #define HW_UART6CLKDIV 0x01b0 |
44 | #define HW_UART7CLKDIV 0x01b4 |
45 | #define HW_UART8CLKDIV 0x01b8 |
46 | #define HW_UART9CLKDIV 0x01bc |
47 | #define HW_SPI0CLKDIV 0x01c0 |
48 | #define HW_SPI1CLKDIV 0x01c4 |
49 | #define HW_QUADSPICLKDIV 0x01c8 |
50 | #define HW_SSP0CLKDIV 0x01d0 |
51 | #define HW_NANDCLKDIV 0x01d4 |
52 | #define HW_TRACECLKDIV 0x01e0 |
53 | #define HW_CAMMCLKDIV 0x01e8 |
54 | #define HW_WDTCLKDIV 0x01ec |
55 | #define HW_CLKOUTCLKDIV 0x01f4 |
56 | #define HW_MACCLKDIV 0x01f8 |
57 | #define HW_LCDCLKDIV 0x01fc |
58 | #define HW_ADCANACLKDIV 0x0200 |
59 | |
60 | static struct clk_hw_onecell_data *clk_data; |
61 | static DEFINE_SPINLOCK(asm9260_clk_lock); |
62 | |
63 | struct asm9260_div_clk { |
64 | unsigned int idx; |
65 | const char *name; |
66 | const char *parent_name; |
67 | u32 reg; |
68 | }; |
69 | |
70 | struct asm9260_gate_data { |
71 | unsigned int idx; |
72 | const char *name; |
73 | const char *parent_name; |
74 | u32 reg; |
75 | u8 bit_idx; |
76 | unsigned long flags; |
77 | }; |
78 | |
79 | struct asm9260_mux_clock { |
80 | u8 mask; |
81 | u32 *table; |
82 | const char *name; |
83 | const struct clk_parent_data *parent_data; |
84 | u8 num_parents; |
85 | unsigned long offset; |
86 | unsigned long flags; |
87 | }; |
88 | |
89 | static void __iomem *base; |
90 | |
91 | static const struct asm9260_div_clk asm9260_div_clks[] __initconst = { |
92 | { CLKID_SYS_CPU, .name: "cpu_div" , .parent_name: "main_gate" , HW_CPUCLKDIV }, |
93 | { CLKID_SYS_AHB, "ahb_div" , "cpu_div" , HW_SYSAHBCLKDIV }, |
94 | |
95 | /* i2s has two deviders: one for only external mclk and internal |
96 | * devider for all clks. */ |
97 | { CLKID_SYS_I2S0M, "i2s0m_div" , "i2s0_mclk" , HW_I2S0MCLKDIV }, |
98 | { CLKID_SYS_I2S1M, "i2s1m_div" , "i2s1_mclk" , HW_I2S1MCLKDIV }, |
99 | { CLKID_SYS_I2S0S, "i2s0s_div" , "i2s0_gate" , HW_I2S0SCLKDIV }, |
100 | { CLKID_SYS_I2S1S, "i2s1s_div" , "i2s0_gate" , HW_I2S1SCLKDIV }, |
101 | |
102 | { CLKID_SYS_UART0, "uart0_div" , "uart_gate" , HW_UART0CLKDIV }, |
103 | { CLKID_SYS_UART1, "uart1_div" , "uart_gate" , HW_UART1CLKDIV }, |
104 | { CLKID_SYS_UART2, "uart2_div" , "uart_gate" , HW_UART2CLKDIV }, |
105 | { CLKID_SYS_UART3, "uart3_div" , "uart_gate" , HW_UART3CLKDIV }, |
106 | { CLKID_SYS_UART4, "uart4_div" , "uart_gate" , HW_UART4CLKDIV }, |
107 | { CLKID_SYS_UART5, "uart5_div" , "uart_gate" , HW_UART5CLKDIV }, |
108 | { CLKID_SYS_UART6, "uart6_div" , "uart_gate" , HW_UART6CLKDIV }, |
109 | { CLKID_SYS_UART7, "uart7_div" , "uart_gate" , HW_UART7CLKDIV }, |
110 | { CLKID_SYS_UART8, "uart8_div" , "uart_gate" , HW_UART8CLKDIV }, |
111 | { CLKID_SYS_UART9, "uart9_div" , "uart_gate" , HW_UART9CLKDIV }, |
112 | |
113 | { CLKID_SYS_SPI0, "spi0_div" , "main_gate" , HW_SPI0CLKDIV }, |
114 | { CLKID_SYS_SPI1, "spi1_div" , "main_gate" , HW_SPI1CLKDIV }, |
115 | { CLKID_SYS_QUADSPI, "quadspi_div" , "main_gate" , HW_QUADSPICLKDIV }, |
116 | { CLKID_SYS_SSP0, "ssp0_div" , "main_gate" , HW_SSP0CLKDIV }, |
117 | { CLKID_SYS_NAND, "nand_div" , "main_gate" , HW_NANDCLKDIV }, |
118 | { CLKID_SYS_TRACE, "trace_div" , "main_gate" , HW_TRACECLKDIV }, |
119 | { CLKID_SYS_CAMM, "camm_div" , "main_gate" , HW_CAMMCLKDIV }, |
120 | { CLKID_SYS_MAC, "mac_div" , "main_gate" , HW_MACCLKDIV }, |
121 | { CLKID_SYS_LCD, "lcd_div" , "main_gate" , HW_LCDCLKDIV }, |
122 | { CLKID_SYS_ADCANA, "adcana_div" , "main_gate" , HW_ADCANACLKDIV }, |
123 | |
124 | { CLKID_SYS_WDT, "wdt_div" , "wdt_gate" , HW_WDTCLKDIV }, |
125 | { CLKID_SYS_CLKOUT, "clkout_div" , "clkout_gate" , HW_CLKOUTCLKDIV }, |
126 | }; |
127 | |
128 | static const struct asm9260_gate_data asm9260_mux_gates[] __initconst = { |
129 | { 0, "main_gate" , "main_mux" , HW_MAINCLKUEN, 0 }, |
130 | { 0, "uart_gate" , "uart_mux" , HW_UARTCLKUEN, 0 }, |
131 | { 0, "i2s0_gate" , "i2s0_mux" , HW_I2S0CLKUEN, 0 }, |
132 | { 0, "i2s1_gate" , "i2s1_mux" , HW_I2S1CLKUEN, 0 }, |
133 | { 0, "wdt_gate" , "wdt_mux" , HW_WDTCLKUEN, 0 }, |
134 | { 0, "clkout_gate" , "clkout_mux" , HW_CLKOUTCLKUEN, 0 }, |
135 | }; |
136 | static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = { |
137 | /* ahb gates */ |
138 | { CLKID_AHB_ROM, "rom" , "ahb_div" , |
139 | HW_AHBCLKCTRL0, 1, CLK_IGNORE_UNUSED}, |
140 | { CLKID_AHB_RAM, "ram" , "ahb_div" , |
141 | HW_AHBCLKCTRL0, 2, CLK_IGNORE_UNUSED}, |
142 | { CLKID_AHB_GPIO, "gpio" , "ahb_div" , |
143 | HW_AHBCLKCTRL0, 4 }, |
144 | { CLKID_AHB_MAC, "mac" , "ahb_div" , |
145 | HW_AHBCLKCTRL0, 5 }, |
146 | { CLKID_AHB_EMI, "emi" , "ahb_div" , |
147 | HW_AHBCLKCTRL0, 6, CLK_IGNORE_UNUSED}, |
148 | { CLKID_AHB_USB0, "usb0" , "ahb_div" , |
149 | HW_AHBCLKCTRL0, 7 }, |
150 | { CLKID_AHB_USB1, "usb1" , "ahb_div" , |
151 | HW_AHBCLKCTRL0, 8 }, |
152 | { CLKID_AHB_DMA0, "dma0" , "ahb_div" , |
153 | HW_AHBCLKCTRL0, 9 }, |
154 | { CLKID_AHB_DMA1, "dma1" , "ahb_div" , |
155 | HW_AHBCLKCTRL0, 10 }, |
156 | { CLKID_AHB_UART0, "uart0" , "ahb_div" , |
157 | HW_AHBCLKCTRL0, 11 }, |
158 | { CLKID_AHB_UART1, "uart1" , "ahb_div" , |
159 | HW_AHBCLKCTRL0, 12 }, |
160 | { CLKID_AHB_UART2, "uart2" , "ahb_div" , |
161 | HW_AHBCLKCTRL0, 13 }, |
162 | { CLKID_AHB_UART3, "uart3" , "ahb_div" , |
163 | HW_AHBCLKCTRL0, 14 }, |
164 | { CLKID_AHB_UART4, "uart4" , "ahb_div" , |
165 | HW_AHBCLKCTRL0, 15 }, |
166 | { CLKID_AHB_UART5, "uart5" , "ahb_div" , |
167 | HW_AHBCLKCTRL0, 16 }, |
168 | { CLKID_AHB_UART6, "uart6" , "ahb_div" , |
169 | HW_AHBCLKCTRL0, 17 }, |
170 | { CLKID_AHB_UART7, "uart7" , "ahb_div" , |
171 | HW_AHBCLKCTRL0, 18 }, |
172 | { CLKID_AHB_UART8, "uart8" , "ahb_div" , |
173 | HW_AHBCLKCTRL0, 19 }, |
174 | { CLKID_AHB_UART9, "uart9" , "ahb_div" , |
175 | HW_AHBCLKCTRL0, 20 }, |
176 | { CLKID_AHB_I2S0, "i2s0" , "ahb_div" , |
177 | HW_AHBCLKCTRL0, 21 }, |
178 | { CLKID_AHB_I2C0, "i2c0" , "ahb_div" , |
179 | HW_AHBCLKCTRL0, 22 }, |
180 | { CLKID_AHB_I2C1, "i2c1" , "ahb_div" , |
181 | HW_AHBCLKCTRL0, 23 }, |
182 | { CLKID_AHB_SSP0, "ssp0" , "ahb_div" , |
183 | HW_AHBCLKCTRL0, 24 }, |
184 | { CLKID_AHB_IOCONFIG, "ioconf" , "ahb_div" , |
185 | HW_AHBCLKCTRL0, 25 }, |
186 | { CLKID_AHB_WDT, "wdt" , "ahb_div" , |
187 | HW_AHBCLKCTRL0, 26 }, |
188 | { CLKID_AHB_CAN0, "can0" , "ahb_div" , |
189 | HW_AHBCLKCTRL0, 27 }, |
190 | { CLKID_AHB_CAN1, "can1" , "ahb_div" , |
191 | HW_AHBCLKCTRL0, 28 }, |
192 | { CLKID_AHB_MPWM, "mpwm" , "ahb_div" , |
193 | HW_AHBCLKCTRL0, 29 }, |
194 | { CLKID_AHB_SPI0, "spi0" , "ahb_div" , |
195 | HW_AHBCLKCTRL0, 30 }, |
196 | { CLKID_AHB_SPI1, "spi1" , "ahb_div" , |
197 | HW_AHBCLKCTRL0, 31 }, |
198 | |
199 | { CLKID_AHB_QEI, "qei" , "ahb_div" , |
200 | HW_AHBCLKCTRL1, 0 }, |
201 | { CLKID_AHB_QUADSPI0, "quadspi0" , "ahb_div" , |
202 | HW_AHBCLKCTRL1, 1 }, |
203 | { CLKID_AHB_CAMIF, "capmif" , "ahb_div" , |
204 | HW_AHBCLKCTRL1, 2 }, |
205 | { CLKID_AHB_LCDIF, "lcdif" , "ahb_div" , |
206 | HW_AHBCLKCTRL1, 3 }, |
207 | { CLKID_AHB_TIMER0, "timer0" , "ahb_div" , |
208 | HW_AHBCLKCTRL1, 4 }, |
209 | { CLKID_AHB_TIMER1, "timer1" , "ahb_div" , |
210 | HW_AHBCLKCTRL1, 5 }, |
211 | { CLKID_AHB_TIMER2, "timer2" , "ahb_div" , |
212 | HW_AHBCLKCTRL1, 6 }, |
213 | { CLKID_AHB_TIMER3, "timer3" , "ahb_div" , |
214 | HW_AHBCLKCTRL1, 7 }, |
215 | { CLKID_AHB_IRQ, "irq" , "ahb_div" , |
216 | HW_AHBCLKCTRL1, 8, CLK_IGNORE_UNUSED}, |
217 | { CLKID_AHB_RTC, "rtc" , "ahb_div" , |
218 | HW_AHBCLKCTRL1, 9 }, |
219 | { CLKID_AHB_NAND, "nand" , "ahb_div" , |
220 | HW_AHBCLKCTRL1, 10 }, |
221 | { CLKID_AHB_ADC0, "adc0" , "ahb_div" , |
222 | HW_AHBCLKCTRL1, 11 }, |
223 | { CLKID_AHB_LED, "led" , "ahb_div" , |
224 | HW_AHBCLKCTRL1, 12 }, |
225 | { CLKID_AHB_DAC0, "dac0" , "ahb_div" , |
226 | HW_AHBCLKCTRL1, 13 }, |
227 | { CLKID_AHB_LCD, "lcd" , "ahb_div" , |
228 | HW_AHBCLKCTRL1, 14 }, |
229 | { CLKID_AHB_I2S1, "i2s1" , "ahb_div" , |
230 | HW_AHBCLKCTRL1, 15 }, |
231 | { CLKID_AHB_MAC1, "mac1" , "ahb_div" , |
232 | HW_AHBCLKCTRL1, 16 }, |
233 | }; |
234 | |
235 | static struct clk_parent_data __initdata main_mux_p[] = { { .index = 0, }, { .name = "pll" } }; |
236 | static struct clk_parent_data __initdata i2s0_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s0m_div" } }; |
237 | static struct clk_parent_data __initdata i2s1_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s1m_div" } }; |
238 | static struct clk_parent_data __initdata clkout_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "rtc" } }; |
239 | static u32 three_mux_table[] = {0, 1, 3}; |
240 | |
241 | static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = { |
242 | { 1, three_mux_table, "main_mux" , main_mux_p, |
243 | ARRAY_SIZE(main_mux_p), HW_MAINCLKSEL, }, |
244 | { 1, three_mux_table, "uart_mux" , main_mux_p, |
245 | ARRAY_SIZE(main_mux_p), HW_UARTCLKSEL, }, |
246 | { 1, three_mux_table, "wdt_mux" , main_mux_p, |
247 | ARRAY_SIZE(main_mux_p), HW_WDTCLKSEL, }, |
248 | { 3, three_mux_table, "i2s0_mux" , i2s0_mux_p, |
249 | ARRAY_SIZE(i2s0_mux_p), HW_I2S0CLKSEL, }, |
250 | { 3, three_mux_table, "i2s1_mux" , i2s1_mux_p, |
251 | ARRAY_SIZE(i2s1_mux_p), HW_I2S1CLKSEL, }, |
252 | { 3, three_mux_table, "clkout_mux" , clkout_mux_p, |
253 | ARRAY_SIZE(clkout_mux_p), HW_CLKOUTCLKSEL, }, |
254 | }; |
255 | |
256 | static void __init asm9260_acc_init(struct device_node *np) |
257 | { |
258 | struct clk_hw *pll_hw; |
259 | struct clk_hw **hws; |
260 | const char *pll_clk = "pll" ; |
261 | struct clk_parent_data pll_parent_data = { .index = 0 }; |
262 | u32 rate; |
263 | int n; |
264 | |
265 | clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL); |
266 | if (!clk_data) |
267 | return; |
268 | clk_data->num = MAX_CLKS; |
269 | hws = clk_data->hws; |
270 | |
271 | base = of_io_request_and_map(device: np, index: 0, name: np->name); |
272 | if (IS_ERR(ptr: base)) |
273 | panic(fmt: "%pOFn: unable to map resource" , np); |
274 | |
275 | /* register pll */ |
276 | rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000; |
277 | |
278 | pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data, |
279 | 0, rate); |
280 | if (IS_ERR(ptr: pll_hw)) |
281 | panic(fmt: "%pOFn: can't register REFCLK. Check DT!" , np); |
282 | |
283 | for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) { |
284 | const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n]; |
285 | |
286 | clk_hw_register_mux_table_parent_data(NULL, mc->name, mc->parent_data, |
287 | mc->num_parents, mc->flags, base + mc->offset, |
288 | 0, mc->mask, 0, mc->table, &asm9260_clk_lock); |
289 | } |
290 | |
291 | /* clock mux gate cells */ |
292 | for (n = 0; n < ARRAY_SIZE(asm9260_mux_gates); n++) { |
293 | const struct asm9260_gate_data *gd = &asm9260_mux_gates[n]; |
294 | |
295 | clk_hw_register_gate(NULL, gd->name, |
296 | gd->parent_name, gd->flags | CLK_SET_RATE_PARENT, |
297 | base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock); |
298 | } |
299 | |
300 | /* clock div cells */ |
301 | for (n = 0; n < ARRAY_SIZE(asm9260_div_clks); n++) { |
302 | const struct asm9260_div_clk *dc = &asm9260_div_clks[n]; |
303 | |
304 | hws[dc->idx] = clk_hw_register_divider(NULL, dc->name, |
305 | dc->parent_name, CLK_SET_RATE_PARENT, |
306 | base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED, |
307 | &asm9260_clk_lock); |
308 | } |
309 | |
310 | /* clock ahb gate cells */ |
311 | for (n = 0; n < ARRAY_SIZE(asm9260_ahb_gates); n++) { |
312 | const struct asm9260_gate_data *gd = &asm9260_ahb_gates[n]; |
313 | |
314 | hws[gd->idx] = clk_hw_register_gate(NULL, gd->name, |
315 | gd->parent_name, gd->flags, base + gd->reg, |
316 | gd->bit_idx, 0, &asm9260_clk_lock); |
317 | } |
318 | |
319 | /* check for errors on leaf clocks */ |
320 | for (n = 0; n < MAX_CLKS; n++) { |
321 | if (!IS_ERR(ptr: hws[n])) |
322 | continue; |
323 | |
324 | pr_err("%pOF: Unable to register leaf clock %d\n" , |
325 | np, n); |
326 | goto fail; |
327 | } |
328 | |
329 | /* register clk-provider */ |
330 | of_clk_add_hw_provider(np, get: of_clk_hw_onecell_get, data: clk_data); |
331 | return; |
332 | fail: |
333 | iounmap(addr: base); |
334 | } |
335 | CLK_OF_DECLARE(asm9260_acc, "alphascale,asm9260-clock-controller" , |
336 | asm9260_acc_init); |
337 | |