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1/*
2 * Cirrus Logic CLPS711X CLK driver
3 *
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/clkdev.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
16#include <linux/of_address.h>
17#include <linux/slab.h>
18#include <linux/mfd/syscon/clps711x.h>
19
20#include <dt-bindings/clock/clps711x-clock.h>
21
22#define CLPS711X_SYSCON1 (0x0100)
23#define CLPS711X_SYSCON2 (0x1100)
24#define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET)
25#define CLPS711X_PLLR (0xa5a8)
26
27#define CLPS711X_EXT_FREQ (13000000)
28#define CLPS711X_OSC_FREQ (3686400)
29
30static const struct clk_div_table spi_div_table[] = {
31 { .val = 0, .div = 32, },
32 { .val = 1, .div = 8, },
33 { .val = 2, .div = 2, },
34 { .val = 3, .div = 1, },
35};
36
37static const struct clk_div_table timer_div_table[] = {
38 { .val = 0, .div = 256, },
39 { .val = 1, .div = 1, },
40};
41
42struct clps711x_clk {
43 spinlock_t lock;
44 struct clk_hw_onecell_data clk_data;
45};
46
47static void __init clps711x_clk_init_dt(struct device_node *np)
48{
49 u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0;
50 struct clps711x_clk *clps711x_clk;
51 void __iomem *base;
52
53 WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
54
55 base = of_iomap(np, 0);
56 BUG_ON(!base);
57
58 clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
59 CLPS711X_CLK_MAX),
60 GFP_KERNEL);
61 BUG_ON(!clps711x_clk);
62
63 spin_lock_init(&clps711x_clk->lock);
64
65 /* Read PLL multiplier value and sanity check */
66 tmp = readl(base + CLPS711X_PLLR) >> 24;
67 if (((tmp >= 10) && (tmp <= 50)) || !fref)
68 f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
69 else
70 f_pll = fref;
71
72 tmp = readl(base + CLPS711X_SYSFLG2);
73 if (tmp & SYSFLG2_CKMODE) {
74 f_cpu = CLPS711X_EXT_FREQ;
75 f_bus = CLPS711X_EXT_FREQ;
76 f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
77 f_pll = 0;
78 f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
79 } else {
80 f_cpu = f_pll;
81 if (f_cpu > 36864000)
82 f_bus = DIV_ROUND_UP(f_cpu, 2);
83 else
84 f_bus = 36864000 / 2;
85 f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
86 f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
87 }
88
89 if (tmp & SYSFLG2_CKMODE) {
90 if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
91 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
92 else
93 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
94 } else
95 f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);
96
97 tmp = readl(base + CLPS711X_SYSCON1);
98 /* Timer1 in free running mode.
99 * Counter will wrap around to 0xffff when it underflows
100 * and will continue to count down.
101 */
102 tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
103 /* Timer2 in prescale mode.
104 * Value writen is automatically re-loaded when
105 * the counter underflows.
106 */
107 tmp |= SYSCON1_TC2M | SYSCON1_TC2S;
108 writel(tmp, base + CLPS711X_SYSCON1);
109
110 clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
111 clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
112 clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
113 clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu);
114 clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
115 clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus);
116 clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
117 clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll);
118 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
119 clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim);
120 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
121 clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0,
122 base + CLPS711X_SYSCON1, 5, 1, 0,
123 timer_div_table, &clps711x_clk->lock);
124 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
125 clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0,
126 base + CLPS711X_SYSCON1, 7, 1, 0,
127 timer_div_table, &clps711x_clk->lock);
128 clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
129 clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm);
130 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] =
131 clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi);
132 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] =
133 clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
134 base + CLPS711X_SYSCON1, 16, 2, 0,
135 spi_div_table, &clps711x_clk->lock);
136 clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] =
137 clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
138 clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
139 clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
140 for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++)
141 if (IS_ERR(clps711x_clk->clk_data.hws[tmp]))
142 pr_err("clk %i: register failed with %ld\n",
143 tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp]));
144
145 clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
146 of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
147 &clps711x_clk->clk_data);
148}
149CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);
150

Warning: That file was not part of the compilation database. It may have many parsing errors.