1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Cirrus Logic CLPS711X CLK driver |
4 | * |
5 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> |
6 | */ |
7 | |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/clkdev.h> |
10 | #include <linux/io.h> |
11 | #include <linux/ioport.h> |
12 | #include <linux/of_address.h> |
13 | #include <linux/slab.h> |
14 | #include <linux/mfd/syscon/clps711x.h> |
15 | |
16 | #include <dt-bindings/clock/clps711x-clock.h> |
17 | |
18 | #define CLPS711X_SYSCON1 (0x0100) |
19 | #define CLPS711X_SYSCON2 (0x1100) |
20 | #define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET) |
21 | #define CLPS711X_PLLR (0xa5a8) |
22 | |
23 | #define CLPS711X_EXT_FREQ (13000000) |
24 | #define CLPS711X_OSC_FREQ (3686400) |
25 | |
26 | static const struct clk_div_table spi_div_table[] = { |
27 | { .val = 0, .div = 32, }, |
28 | { .val = 1, .div = 8, }, |
29 | { .val = 2, .div = 2, }, |
30 | { .val = 3, .div = 1, }, |
31 | { /* sentinel */ } |
32 | }; |
33 | |
34 | static const struct clk_div_table timer_div_table[] = { |
35 | { .val = 0, .div = 256, }, |
36 | { .val = 1, .div = 1, }, |
37 | { /* sentinel */ } |
38 | }; |
39 | |
40 | struct clps711x_clk { |
41 | spinlock_t lock; |
42 | struct clk_hw_onecell_data clk_data; |
43 | }; |
44 | |
45 | static void __init clps711x_clk_init_dt(struct device_node *np) |
46 | { |
47 | u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0; |
48 | struct clps711x_clk *clps711x_clk; |
49 | void __iomem *base; |
50 | |
51 | WARN_ON(of_property_read_u32(np, "startup-frequency" , &fref)); |
52 | |
53 | base = of_iomap(node: np, index: 0); |
54 | BUG_ON(!base); |
55 | |
56 | clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws, |
57 | CLPS711X_CLK_MAX), |
58 | GFP_KERNEL); |
59 | BUG_ON(!clps711x_clk); |
60 | |
61 | spin_lock_init(&clps711x_clk->lock); |
62 | |
63 | /* Read PLL multiplier value and sanity check */ |
64 | tmp = readl(addr: base + CLPS711X_PLLR) >> 24; |
65 | if (((tmp >= 10) && (tmp <= 50)) || !fref) |
66 | f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2); |
67 | else |
68 | f_pll = fref; |
69 | |
70 | tmp = readl(addr: base + CLPS711X_SYSFLG2); |
71 | if (tmp & SYSFLG2_CKMODE) { |
72 | f_cpu = CLPS711X_EXT_FREQ; |
73 | f_bus = CLPS711X_EXT_FREQ; |
74 | f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96); |
75 | f_pll = 0; |
76 | f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128); |
77 | } else { |
78 | f_cpu = f_pll; |
79 | if (f_cpu > 36864000) |
80 | f_bus = DIV_ROUND_UP(f_cpu, 2); |
81 | else |
82 | f_bus = 36864000 / 2; |
83 | f_spi = DIV_ROUND_CLOSEST(f_cpu, 576); |
84 | f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768); |
85 | } |
86 | |
87 | if (tmp & SYSFLG2_CKMODE) { |
88 | if (readl(addr: base + CLPS711X_SYSCON2) & SYSCON2_OSTB) |
89 | f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26); |
90 | else |
91 | f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24); |
92 | } else |
93 | f_tim = DIV_ROUND_CLOSEST(f_cpu, 144); |
94 | |
95 | tmp = readl(addr: base + CLPS711X_SYSCON1); |
96 | /* Timer1 in free running mode. |
97 | * Counter will wrap around to 0xffff when it underflows |
98 | * and will continue to count down. |
99 | */ |
100 | tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S); |
101 | /* Timer2 in prescale mode. |
102 | * Value writen is automatically re-loaded when |
103 | * the counter underflows. |
104 | */ |
105 | tmp |= SYSCON1_TC2M | SYSCON1_TC2S; |
106 | writel(val: tmp, addr: base + CLPS711X_SYSCON1); |
107 | |
108 | clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] = |
109 | clk_hw_register_fixed_rate(NULL, "dummy" , NULL, 0, 0); |
110 | clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] = |
111 | clk_hw_register_fixed_rate(NULL, "cpu" , NULL, 0, f_cpu); |
112 | clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] = |
113 | clk_hw_register_fixed_rate(NULL, "bus" , NULL, 0, f_bus); |
114 | clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] = |
115 | clk_hw_register_fixed_rate(NULL, "pll" , NULL, 0, f_pll); |
116 | clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] = |
117 | clk_hw_register_fixed_rate(NULL, "timer_ref" , NULL, 0, f_tim); |
118 | clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] = |
119 | clk_hw_register_divider_table(NULL, "timer1" , "timer_ref" , 0, |
120 | base + CLPS711X_SYSCON1, 5, 1, 0, |
121 | timer_div_table, &clps711x_clk->lock); |
122 | clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] = |
123 | clk_hw_register_divider_table(NULL, "timer2" , "timer_ref" , 0, |
124 | base + CLPS711X_SYSCON1, 7, 1, 0, |
125 | timer_div_table, &clps711x_clk->lock); |
126 | clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] = |
127 | clk_hw_register_fixed_rate(NULL, "pwm" , NULL, 0, f_pwm); |
128 | clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] = |
129 | clk_hw_register_fixed_rate(NULL, "spi_ref" , NULL, 0, f_spi); |
130 | clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] = |
131 | clk_hw_register_divider_table(NULL, "spi" , "spi_ref" , 0, |
132 | base + CLPS711X_SYSCON1, 16, 2, 0, |
133 | spi_div_table, &clps711x_clk->lock); |
134 | clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] = |
135 | clk_hw_register_fixed_factor(NULL, name: "uart" , parent_name: "bus" , flags: 0, mult: 1, div: 10); |
136 | clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] = |
137 | clk_hw_register_fixed_rate(NULL, "tick" , NULL, 0, 64); |
138 | for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++) |
139 | if (IS_ERR(ptr: clps711x_clk->clk_data.hws[tmp])) |
140 | pr_err("clk %i: register failed with %ld\n" , |
141 | tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp])); |
142 | |
143 | clps711x_clk->clk_data.num = CLPS711X_CLK_MAX; |
144 | of_clk_add_hw_provider(np, get: of_clk_hw_onecell_get, |
145 | data: &clps711x_clk->clk_data); |
146 | } |
147 | CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk" , clps711x_clk_init_dt); |
148 | |