1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 *
6 * Gated clock implementation
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/module.h>
11#include <linux/slab.h>
12#include <linux/io.h>
13#include <linux/err.h>
14#include <linux/string.h>
15
16/**
17 * DOC: basic gatable clock which can gate and ungate it's ouput
18 *
19 * Traits of this clock:
20 * prepare - clk_(un)prepare only ensures parent is (un)prepared
21 * enable - clk_enable and clk_disable are functional & control gating
22 * rate - inherits rate from parent. No clk_set_rate support
23 * parent - fixed parent. No clk_set_parent support
24 */
25
26/*
27 * It works on following logic:
28 *
29 * For enabling clock, enable = 1
30 * set2dis = 1 -> clear bit -> set = 0
31 * set2dis = 0 -> set bit -> set = 1
32 *
33 * For disabling clock, enable = 0
34 * set2dis = 1 -> set bit -> set = 1
35 * set2dis = 0 -> clear bit -> set = 0
36 *
37 * So, result is always: enable xor set2dis.
38 */
39static void clk_gate_endisable(struct clk_hw *hw, int enable)
40{
41 struct clk_gate *gate = to_clk_gate(hw);
42 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
43 unsigned long uninitialized_var(flags);
44 u32 reg;
45
46 set ^= enable;
47
48 if (gate->lock)
49 spin_lock_irqsave(gate->lock, flags);
50 else
51 __acquire(gate->lock);
52
53 if (gate->flags & CLK_GATE_HIWORD_MASK) {
54 reg = BIT(gate->bit_idx + 16);
55 if (set)
56 reg |= BIT(gate->bit_idx);
57 } else {
58 reg = clk_readl(gate->reg);
59
60 if (set)
61 reg |= BIT(gate->bit_idx);
62 else
63 reg &= ~BIT(gate->bit_idx);
64 }
65
66 clk_writel(reg, gate->reg);
67
68 if (gate->lock)
69 spin_unlock_irqrestore(gate->lock, flags);
70 else
71 __release(gate->lock);
72}
73
74static int clk_gate_enable(struct clk_hw *hw)
75{
76 clk_gate_endisable(hw, 1);
77
78 return 0;
79}
80
81static void clk_gate_disable(struct clk_hw *hw)
82{
83 clk_gate_endisable(hw, 0);
84}
85
86int clk_gate_is_enabled(struct clk_hw *hw)
87{
88 u32 reg;
89 struct clk_gate *gate = to_clk_gate(hw);
90
91 reg = clk_readl(gate->reg);
92
93 /* if a set bit disables this clk, flip it before masking */
94 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
95 reg ^= BIT(gate->bit_idx);
96
97 reg &= BIT(gate->bit_idx);
98
99 return reg ? 1 : 0;
100}
101EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
102
103const struct clk_ops clk_gate_ops = {
104 .enable = clk_gate_enable,
105 .disable = clk_gate_disable,
106 .is_enabled = clk_gate_is_enabled,
107};
108EXPORT_SYMBOL_GPL(clk_gate_ops);
109
110/**
111 * clk_hw_register_gate - register a gate clock with the clock framework
112 * @dev: device that is registering this clock
113 * @name: name of this clock
114 * @parent_name: name of this clock's parent
115 * @flags: framework-specific flags for this clock
116 * @reg: register address to control gating of this clock
117 * @bit_idx: which bit in the register controls gating of this clock
118 * @clk_gate_flags: gate-specific flags for this clock
119 * @lock: shared register lock for this clock
120 */
121struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
122 const char *parent_name, unsigned long flags,
123 void __iomem *reg, u8 bit_idx,
124 u8 clk_gate_flags, spinlock_t *lock)
125{
126 struct clk_gate *gate;
127 struct clk_hw *hw;
128 struct clk_init_data init;
129 int ret;
130
131 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
132 if (bit_idx > 15) {
133 pr_err("gate bit exceeds LOWORD field\n");
134 return ERR_PTR(-EINVAL);
135 }
136 }
137
138 /* allocate the gate */
139 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
140 if (!gate)
141 return ERR_PTR(-ENOMEM);
142
143 init.name = name;
144 init.ops = &clk_gate_ops;
145 init.flags = flags | CLK_IS_BASIC;
146 init.parent_names = parent_name ? &parent_name : NULL;
147 init.num_parents = parent_name ? 1 : 0;
148
149 /* struct clk_gate assignments */
150 gate->reg = reg;
151 gate->bit_idx = bit_idx;
152 gate->flags = clk_gate_flags;
153 gate->lock = lock;
154 gate->hw.init = &init;
155
156 hw = &gate->hw;
157 ret = clk_hw_register(dev, hw);
158 if (ret) {
159 kfree(gate);
160 hw = ERR_PTR(ret);
161 }
162
163 return hw;
164}
165EXPORT_SYMBOL_GPL(clk_hw_register_gate);
166
167struct clk *clk_register_gate(struct device *dev, const char *name,
168 const char *parent_name, unsigned long flags,
169 void __iomem *reg, u8 bit_idx,
170 u8 clk_gate_flags, spinlock_t *lock)
171{
172 struct clk_hw *hw;
173
174 hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,
175 bit_idx, clk_gate_flags, lock);
176 if (IS_ERR(hw))
177 return ERR_CAST(hw);
178 return hw->clk;
179}
180EXPORT_SYMBOL_GPL(clk_register_gate);
181
182void clk_unregister_gate(struct clk *clk)
183{
184 struct clk_gate *gate;
185 struct clk_hw *hw;
186
187 hw = __clk_get_hw(clk);
188 if (!hw)
189 return;
190
191 gate = to_clk_gate(hw);
192
193 clk_unregister(clk);
194 kfree(gate);
195}
196EXPORT_SYMBOL_GPL(clk_unregister_gate);
197
198void clk_hw_unregister_gate(struct clk_hw *hw)
199{
200 struct clk_gate *gate;
201
202 gate = to_clk_gate(hw);
203
204 clk_hw_unregister(hw);
205 kfree(gate);
206}
207EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);
208