1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de> |
4 | */ |
5 | |
6 | #include <linux/module.h> |
7 | #include <linux/clk.h> |
8 | #include <linux/clkdev.h> |
9 | #include <linux/io.h> |
10 | #include <linux/err.h> |
11 | #include <linux/of.h> |
12 | #include <linux/of_address.h> |
13 | #include <soc/imx/revision.h> |
14 | #include <asm/irq.h> |
15 | |
16 | #include "clk.h" |
17 | |
18 | #define MX31_CCM_BASE_ADDR 0x53f80000 |
19 | #define MX31_GPT1_BASE_ADDR 0x53f90000 |
20 | #define MX31_INT_GPT (NR_IRQS_LEGACY + 29) |
21 | |
22 | #define MXC_CCM_CCMR 0x00 |
23 | #define MXC_CCM_PDR0 0x04 |
24 | #define MXC_CCM_PDR1 0x08 |
25 | #define MXC_CCM_MPCTL 0x10 |
26 | #define MXC_CCM_UPCTL 0x14 |
27 | #define MXC_CCM_SRPCTL 0x18 |
28 | #define MXC_CCM_CGR0 0x20 |
29 | #define MXC_CCM_CGR1 0x24 |
30 | #define MXC_CCM_CGR2 0x28 |
31 | #define MXC_CCM_PMCR0 0x5c |
32 | |
33 | static const char *mcu_main_sel[] = { "spll" , "mpll" , }; |
34 | static const char *per_sel[] = { "per_div" , "ipg" , }; |
35 | static const char *csi_sel[] = { "upll" , "spll" , }; |
36 | static const char *fir_sel[] = { "mcu_main" , "upll" , "spll" }; |
37 | |
38 | enum mx31_clks { |
39 | dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, |
40 | per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre, |
41 | fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate, |
42 | iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate, |
43 | uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate, |
44 | mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate, |
45 | sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate, |
46 | uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate, |
47 | gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max |
48 | }; |
49 | |
50 | static struct clk *clk[clk_max]; |
51 | static struct clk_onecell_data clk_data; |
52 | |
53 | static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref) |
54 | { |
55 | clk[dummy] = imx_clk_fixed("dummy" , 0); |
56 | clk[ckih] = imx_clk_fixed("ckih" , fref); |
57 | clk[ckil] = imx_clk_fixed("ckil" , 32768); |
58 | clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll" , "ckih" , base + MXC_CCM_MPCTL); |
59 | clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll" , "ckih" , base + MXC_CCM_SRPCTL); |
60 | clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll" , "ckih" , base + MXC_CCM_UPCTL); |
61 | clk[mcu_main] = imx_clk_mux("mcu_main" , base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); |
62 | clk[hsp] = imx_clk_divider("hsp" , "mcu_main" , base + MXC_CCM_PDR0, 11, 3); |
63 | clk[ahb] = imx_clk_divider("ahb" , "mcu_main" , base + MXC_CCM_PDR0, 3, 3); |
64 | clk[nfc] = imx_clk_divider("nfc" , "ahb" , base + MXC_CCM_PDR0, 8, 3); |
65 | clk[ipg] = imx_clk_divider("ipg" , "ahb" , base + MXC_CCM_PDR0, 6, 2); |
66 | clk[per_div] = imx_clk_divider("per_div" , "upll" , base + MXC_CCM_PDR0, 16, 5); |
67 | clk[per] = imx_clk_mux("per" , base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel)); |
68 | clk[csi] = imx_clk_mux("csi_sel" , base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel)); |
69 | clk[fir] = imx_clk_mux("fir_sel" , base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel)); |
70 | clk[csi_div] = imx_clk_divider("csi_div" , "csi_sel" , base + MXC_CCM_PDR0, 23, 9); |
71 | clk[usb_div_pre] = imx_clk_divider("usb_div_pre" , "upll" , base + MXC_CCM_PDR1, 30, 2); |
72 | clk[usb_div_post] = imx_clk_divider("usb_div_post" , "usb_div_pre" , base + MXC_CCM_PDR1, 27, 3); |
73 | clk[fir_div_pre] = imx_clk_divider("fir_div_pre" , "fir_sel" , base + MXC_CCM_PDR1, 24, 3); |
74 | clk[fir_div_post] = imx_clk_divider("fir_div_post" , "fir_div_pre" , base + MXC_CCM_PDR1, 23, 6); |
75 | clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate" , "per" , base + MXC_CCM_CGR0, 0); |
76 | clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate" , "per" , base + MXC_CCM_CGR0, 2); |
77 | clk[gpt_gate] = imx_clk_gate2("gpt_gate" , "per" , base + MXC_CCM_CGR0, 4); |
78 | clk[epit1_gate] = imx_clk_gate2("epit1_gate" , "per" , base + MXC_CCM_CGR0, 6); |
79 | clk[epit2_gate] = imx_clk_gate2("epit2_gate" , "per" , base + MXC_CCM_CGR0, 8); |
80 | clk[iim_gate] = imx_clk_gate2("iim_gate" , "ipg" , base + MXC_CCM_CGR0, 10); |
81 | clk[ata_gate] = imx_clk_gate2("ata_gate" , "ipg" , base + MXC_CCM_CGR0, 12); |
82 | clk[sdma_gate] = imx_clk_gate2("sdma_gate" , "ahb" , base + MXC_CCM_CGR0, 14); |
83 | clk[cspi3_gate] = imx_clk_gate2("cspi3_gate" , "ipg" , base + MXC_CCM_CGR0, 16); |
84 | clk[rng_gate] = imx_clk_gate2("rng_gate" , "ipg" , base + MXC_CCM_CGR0, 18); |
85 | clk[uart1_gate] = imx_clk_gate2("uart1_gate" , "per" , base + MXC_CCM_CGR0, 20); |
86 | clk[uart2_gate] = imx_clk_gate2("uart2_gate" , "per" , base + MXC_CCM_CGR0, 22); |
87 | clk[ssi1_gate] = imx_clk_gate2("ssi1_gate" , "spll" , base + MXC_CCM_CGR0, 24); |
88 | clk[i2c1_gate] = imx_clk_gate2("i2c1_gate" , "per" , base + MXC_CCM_CGR0, 26); |
89 | clk[i2c2_gate] = imx_clk_gate2("i2c2_gate" , "per" , base + MXC_CCM_CGR0, 28); |
90 | clk[i2c3_gate] = imx_clk_gate2("i2c3_gate" , "per" , base + MXC_CCM_CGR0, 30); |
91 | clk[hantro_gate] = imx_clk_gate2("hantro_gate" , "per" , base + MXC_CCM_CGR1, 0); |
92 | clk[mstick1_gate] = imx_clk_gate2("mstick1_gate" , "per" , base + MXC_CCM_CGR1, 2); |
93 | clk[mstick2_gate] = imx_clk_gate2("mstick2_gate" , "per" , base + MXC_CCM_CGR1, 4); |
94 | clk[csi_gate] = imx_clk_gate2("csi_gate" , "csi_div" , base + MXC_CCM_CGR1, 6); |
95 | clk[rtc_gate] = imx_clk_gate2("rtc_gate" , "ipg" , base + MXC_CCM_CGR1, 8); |
96 | clk[wdog_gate] = imx_clk_gate2("wdog_gate" , "ipg" , base + MXC_CCM_CGR1, 10); |
97 | clk[pwm_gate] = imx_clk_gate2("pwm_gate" , "per" , base + MXC_CCM_CGR1, 12); |
98 | clk[sim_gate] = imx_clk_gate2("sim_gate" , "per" , base + MXC_CCM_CGR1, 14); |
99 | clk[ect_gate] = imx_clk_gate2("ect_gate" , "per" , base + MXC_CCM_CGR1, 16); |
100 | clk[usb_gate] = imx_clk_gate2("usb_gate" , "ahb" , base + MXC_CCM_CGR1, 18); |
101 | clk[kpp_gate] = imx_clk_gate2("kpp_gate" , "ipg" , base + MXC_CCM_CGR1, 20); |
102 | clk[ipu_gate] = imx_clk_gate2("ipu_gate" , "hsp" , base + MXC_CCM_CGR1, 22); |
103 | clk[uart3_gate] = imx_clk_gate2("uart3_gate" , "per" , base + MXC_CCM_CGR1, 24); |
104 | clk[uart4_gate] = imx_clk_gate2("uart4_gate" , "per" , base + MXC_CCM_CGR1, 26); |
105 | clk[uart5_gate] = imx_clk_gate2("uart5_gate" , "per" , base + MXC_CCM_CGR1, 28); |
106 | clk[owire_gate] = imx_clk_gate2("owire_gate" , "per" , base + MXC_CCM_CGR1, 30); |
107 | clk[ssi2_gate] = imx_clk_gate2("ssi2_gate" , "spll" , base + MXC_CCM_CGR2, 0); |
108 | clk[cspi1_gate] = imx_clk_gate2("cspi1_gate" , "ipg" , base + MXC_CCM_CGR2, 2); |
109 | clk[cspi2_gate] = imx_clk_gate2("cspi2_gate" , "ipg" , base + MXC_CCM_CGR2, 4); |
110 | clk[gacc_gate] = imx_clk_gate2("gacc_gate" , "per" , base + MXC_CCM_CGR2, 6); |
111 | clk[emi_gate] = imx_clk_gate2("emi_gate" , "ahb" , base + MXC_CCM_CGR2, 8); |
112 | clk[rtic_gate] = imx_clk_gate2("rtic_gate" , "ahb" , base + MXC_CCM_CGR2, 10); |
113 | clk[firi_gate] = imx_clk_gate2("firi_gate" , "upll" , base+MXC_CCM_CGR2, 12); |
114 | |
115 | imx_check_clocks(clks: clk, ARRAY_SIZE(clk)); |
116 | |
117 | clk_set_parent(clk: clk[csi], parent: clk[upll]); |
118 | clk_prepare_enable(clk: clk[emi_gate]); |
119 | clk_prepare_enable(clk: clk[iim_gate]); |
120 | mx31_revision(); |
121 | clk_disable_unprepare(clk: clk[iim_gate]); |
122 | } |
123 | |
124 | static void __init mx31_clocks_init_dt(struct device_node *np) |
125 | { |
126 | struct device_node *osc_np; |
127 | u32 fref = 26000000; /* default */ |
128 | void __iomem *ccm; |
129 | |
130 | for_each_compatible_node(osc_np, NULL, "fixed-clock" ) { |
131 | if (!of_device_is_compatible(device: osc_np, "fsl,imx-osc26m" )) |
132 | continue; |
133 | |
134 | if (!of_property_read_u32(np: osc_np, propname: "clock-frequency" , out_value: &fref)) { |
135 | of_node_put(node: osc_np); |
136 | break; |
137 | } |
138 | } |
139 | |
140 | ccm = of_iomap(node: np, index: 0); |
141 | if (!ccm) |
142 | panic(fmt: "%s: failed to map registers\n" , __func__); |
143 | |
144 | _mx31_clocks_init(base: ccm, fref); |
145 | |
146 | clk_data.clks = clk; |
147 | clk_data.clk_num = ARRAY_SIZE(clk); |
148 | of_clk_add_provider(np, clk_src_get: of_clk_src_onecell_get, data: &clk_data); |
149 | } |
150 | |
151 | CLK_OF_DECLARE(imx31_ccm, "fsl,imx31-ccm" , mx31_clocks_init_dt); |
152 | |