1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
4 | * Copyright 2011 Linaro Ltd. |
5 | */ |
6 | |
7 | #include <linux/init.h> |
8 | #include <linux/types.h> |
9 | #include <linux/bits.h> |
10 | #include <linux/clk.h> |
11 | #include <linux/clkdev.h> |
12 | #include <linux/clk-provider.h> |
13 | #include <linux/err.h> |
14 | #include <linux/io.h> |
15 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> |
16 | #include <linux/of.h> |
17 | #include <linux/of_address.h> |
18 | #include <linux/of_irq.h> |
19 | #include <soc/imx/revision.h> |
20 | #include <dt-bindings/clock/imx6qdl-clock.h> |
21 | |
22 | #include "clk.h" |
23 | |
24 | static const char *step_sels[] = { "osc" , "pll2_pfd2_396m" , }; |
25 | static const char *pll1_sw_sels[] = { "pll1_sys" , "step" , }; |
26 | static const char *periph_pre_sels[] = { "pll2_bus" , "pll2_pfd2_396m" , "pll2_pfd0_352m" , "pll2_198m" , }; |
27 | static const char *periph_clk2_sels[] = { "pll3_usb_otg" , "osc" , "osc" , "dummy" , }; |
28 | static const char *periph2_clk2_sels[] = { "pll3_usb_otg" , "pll2_bus" , }; |
29 | static const char *periph_sels[] = { "periph_pre" , "periph_clk2" , }; |
30 | static const char *periph2_sels[] = { "periph2_pre" , "periph2_clk2" , }; |
31 | static const char *axi_sels[] = { "periph" , "pll2_pfd2_396m" , "periph" , "pll3_pfd1_540m" , }; |
32 | static const char *audio_sels[] = { "pll4_audio_div" , "pll3_pfd2_508m" , "pll3_pfd3_454m" , "pll3_usb_otg" , }; |
33 | static const char *gpu_axi_sels[] = { "axi" , "ahb" , }; |
34 | static const char *pre_axi_sels[] = { "axi" , "ahb" , }; |
35 | static const char *gpu2d_core_sels[] = { "axi" , "pll3_usb_otg" , "pll2_pfd0_352m" , "pll2_pfd2_396m" , }; |
36 | static const char *gpu2d_core_sels_2[] = { "mmdc_ch0_axi" , "pll3_usb_otg" , "pll2_pfd1_594m" , "pll3_pfd0_720m" ,}; |
37 | static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi" , "pll3_usb_otg" , "pll2_pfd1_594m" , "pll2_pfd2_396m" , }; |
38 | static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi" , "pll3_usb_otg" , "pll2_pfd1_594m" , "pll3_pfd0_720m" , }; |
39 | static const char *ipu_sels[] = { "mmdc_ch0_axi" , "pll2_pfd2_396m" , "pll3_120m" , "pll3_pfd1_540m" , }; |
40 | static const char *ldb_di_sels[] = { "pll5_video_div" , "pll2_pfd0_352m" , "pll2_pfd2_396m" , "mmdc_ch1_axi" , "pll3_usb_otg" , }; |
41 | static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi" , "pll3_usb_otg" , "pll5_video_div" , "pll2_pfd0_352m" , "pll2_pfd2_396m" , "pll3_pfd1_540m" , }; |
42 | static const char *ipu1_di0_sels[] = { "ipu1_di0_pre" , "dummy" , "dummy" , "ldb_di0" , "ldb_di1" , }; |
43 | static const char *ipu1_di1_sels[] = { "ipu1_di1_pre" , "dummy" , "dummy" , "ldb_di0" , "ldb_di1" , }; |
44 | static const char *ipu2_di0_sels[] = { "ipu2_di0_pre" , "dummy" , "dummy" , "ldb_di0" , "ldb_di1" , }; |
45 | static const char *ipu2_di1_sels[] = { "ipu2_di1_pre" , "dummy" , "dummy" , "ldb_di0" , "ldb_di1" , }; |
46 | static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre" , "dummy" , "dummy" , "ldb_di0_podf" , "ldb_di1_podf" , }; |
47 | static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre" , "dummy" , "dummy" , "ldb_di0_podf" , "ldb_di1_podf" , }; |
48 | static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre" , "dummy" , "dummy" , "ldb_di0_podf" , "ldb_di1_podf" , }; |
49 | static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre" , "dummy" , "dummy" , "ldb_di0_podf" , "ldb_di1_podf" , }; |
50 | static const char *hsi_tx_sels[] = { "pll3_120m" , "pll2_pfd2_396m" , }; |
51 | static const char *pcie_axi_sels[] = { "axi" , "ahb" , }; |
52 | static const char *ssi_sels[] = { "pll3_pfd2_508m" , "pll3_pfd3_454m" , "pll4_audio_div" , }; |
53 | static const char *usdhc_sels[] = { "pll2_pfd2_396m" , "pll2_pfd0_352m" , }; |
54 | static const char *enfc_sels[] = { "pll2_pfd0_352m" , "pll2_bus" , "pll3_usb_otg" , "pll2_pfd2_396m" , }; |
55 | static const char *enfc_sels_2[] = {"pll2_pfd0_352m" , "pll2_bus" , "pll3_usb_otg" , "pll2_pfd2_396m" , "pll3_pfd3_454m" , "dummy" , }; |
56 | static const char *eim_sels[] = { "pll2_pfd2_396m" , "pll3_usb_otg" , "axi" , "pll2_pfd0_352m" , }; |
57 | static const char *eim_slow_sels[] = { "axi" , "pll3_usb_otg" , "pll2_pfd2_396m" , "pll2_pfd0_352m" , }; |
58 | static const char *vdo_axi_sels[] = { "axi" , "ahb" , }; |
59 | static const char *vpu_axi_sels[] = { "axi" , "pll2_pfd2_396m" , "pll2_pfd0_352m" , }; |
60 | static const char *uart_sels[] = { "pll3_80m" , "osc" , }; |
61 | static const char *ipg_per_sels[] = { "ipg" , "osc" , }; |
62 | static const char *ecspi_sels[] = { "pll3_60m" , "osc" , }; |
63 | static const char *can_sels[] = { "pll3_60m" , "osc" , "pll3_80m" , }; |
64 | static const char *cko1_sels[] = { "pll3_usb_otg" , "pll2_bus" , "pll1_sys" , "pll5_video_div" , |
65 | "video_27m" , "axi" , "enfc" , "ipu1_di0" , "ipu1_di1" , "ipu2_di0" , |
66 | "ipu2_di1" , "ahb" , "ipg" , "ipg_per" , "ckil" , "pll4_audio_div" , }; |
67 | static const char *cko2_sels[] = { |
68 | "mmdc_ch0_axi" , "mmdc_ch1_axi" , "usdhc4" , "usdhc1" , |
69 | "gpu2d_axi" , "dummy" , "ecspi_root" , "gpu3d_axi" , |
70 | "usdhc3" , "dummy" , "arm" , "ipu1" , |
71 | "ipu2" , "vdo_axi" , "osc" , "gpu2d_core" , |
72 | "gpu3d_core" , "usdhc2" , "ssi1" , "ssi2" , |
73 | "ssi3" , "gpu3d_shader" , "vpu_axi" , "can_root" , |
74 | "ldb_di0" , "ldb_di1" , "esai_extal" , "eim_slow" , |
75 | "uart_serial" , "spdif" , "asrc" , "hsi_tx" , |
76 | }; |
77 | static const char *cko_sels[] = { "cko1" , "cko2" , }; |
78 | static const char *lvds_sels[] = { |
79 | "dummy" , "dummy" , "dummy" , "dummy" , "dummy" , "dummy" , |
80 | "pll4_audio" , "pll5_video" , "pll8_mlb" , "enet_ref" , |
81 | "pcie_ref_125m" , "sata_ref_100m" , "usbphy1" , "usbphy2" , |
82 | "dummy" , "dummy" , "dummy" , "dummy" , "osc" , |
83 | }; |
84 | static const char *pll_bypass_src_sels[] = { "osc" , "lvds1_in" , "lvds2_in" , "dummy" , }; |
85 | static const char *pll1_bypass_sels[] = { "pll1" , "pll1_bypass_src" , }; |
86 | static const char *pll2_bypass_sels[] = { "pll2" , "pll2_bypass_src" , }; |
87 | static const char *pll3_bypass_sels[] = { "pll3" , "pll3_bypass_src" , }; |
88 | static const char *pll4_bypass_sels[] = { "pll4" , "pll4_bypass_src" , }; |
89 | static const char *pll5_bypass_sels[] = { "pll5" , "pll5_bypass_src" , }; |
90 | static const char *pll6_bypass_sels[] = { "pll6" , "pll6_bypass_src" , }; |
91 | static const char *pll7_bypass_sels[] = { "pll7" , "pll7_bypass_src" , }; |
92 | |
93 | static struct clk_hw **hws; |
94 | static struct clk_hw_onecell_data *clk_hw_data; |
95 | |
96 | static struct clk_div_table clk_enet_ref_table[] = { |
97 | { .val = 0, .div = 20, }, |
98 | { .val = 1, .div = 10, }, |
99 | { .val = 2, .div = 5, }, |
100 | { .val = 3, .div = 4, }, |
101 | { /* sentinel */ } |
102 | }; |
103 | |
104 | static struct clk_div_table post_div_table[] = { |
105 | { .val = 2, .div = 1, }, |
106 | { .val = 1, .div = 2, }, |
107 | { .val = 0, .div = 4, }, |
108 | { /* sentinel */ } |
109 | }; |
110 | |
111 | static struct clk_div_table video_div_table[] = { |
112 | { .val = 0, .div = 1, }, |
113 | { .val = 1, .div = 2, }, |
114 | { .val = 2, .div = 1, }, |
115 | { .val = 3, .div = 4, }, |
116 | { /* sentinel */ } |
117 | }; |
118 | |
119 | static const char * enet_ref_sels[] = { "enet_ref" , "enet_ref_pad" , }; |
120 | static const u32 enet_ref_sels_table[] = { IMX6Q_GPR1_ENET_CLK_SEL_ANATOP, IMX6Q_GPR1_ENET_CLK_SEL_PAD }; |
121 | static const u32 enet_ref_sels_table_mask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP; |
122 | |
123 | static unsigned int share_count_esai; |
124 | static unsigned int share_count_asrc; |
125 | static unsigned int share_count_ssi1; |
126 | static unsigned int share_count_ssi2; |
127 | static unsigned int share_count_ssi3; |
128 | static unsigned int share_count_mipi_core_cfg; |
129 | static unsigned int share_count_spdif; |
130 | static unsigned int share_count_prg0; |
131 | static unsigned int share_count_prg1; |
132 | |
133 | static inline int clk_on_imx6q(void) |
134 | { |
135 | return of_machine_is_compatible(compat: "fsl,imx6q" ); |
136 | } |
137 | |
138 | static inline int clk_on_imx6qp(void) |
139 | { |
140 | return of_machine_is_compatible(compat: "fsl,imx6qp" ); |
141 | } |
142 | |
143 | static inline int clk_on_imx6dl(void) |
144 | { |
145 | return of_machine_is_compatible(compat: "fsl,imx6dl" ); |
146 | } |
147 | |
148 | static int ldb_di_sel_by_clock_id(int clock_id) |
149 | { |
150 | switch (clock_id) { |
151 | case IMX6QDL_CLK_PLL5_VIDEO_DIV: |
152 | if (clk_on_imx6q() && |
153 | imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) |
154 | return -ENOENT; |
155 | return 0; |
156 | case IMX6QDL_CLK_PLL2_PFD0_352M: |
157 | return 1; |
158 | case IMX6QDL_CLK_PLL2_PFD2_396M: |
159 | return 2; |
160 | case IMX6QDL_CLK_MMDC_CH1_AXI: |
161 | return 3; |
162 | case IMX6QDL_CLK_PLL3_USB_OTG: |
163 | return 4; |
164 | default: |
165 | return -ENOENT; |
166 | } |
167 | } |
168 | |
169 | static void of_assigned_ldb_sels(struct device_node *node, |
170 | unsigned int *ldb_di0_sel, |
171 | unsigned int *ldb_di1_sel) |
172 | { |
173 | struct of_phandle_args clkspec; |
174 | int index, rc, num_parents; |
175 | int parent, child, sel; |
176 | |
177 | num_parents = of_count_phandle_with_args(np: node, list_name: "assigned-clock-parents" , |
178 | cells_name: "#clock-cells" ); |
179 | for (index = 0; index < num_parents; index++) { |
180 | rc = of_parse_phandle_with_args(np: node, list_name: "assigned-clock-parents" , |
181 | cells_name: "#clock-cells" , index, out_args: &clkspec); |
182 | if (rc < 0) { |
183 | /* skip empty (null) phandles */ |
184 | if (rc == -ENOENT) |
185 | continue; |
186 | else |
187 | return; |
188 | } |
189 | if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { |
190 | pr_err("ccm: parent clock %d not in ccm\n" , index); |
191 | return; |
192 | } |
193 | parent = clkspec.args[0]; |
194 | |
195 | rc = of_parse_phandle_with_args(np: node, list_name: "assigned-clocks" , |
196 | cells_name: "#clock-cells" , index, out_args: &clkspec); |
197 | if (rc < 0) |
198 | return; |
199 | if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { |
200 | pr_err("ccm: child clock %d not in ccm\n" , index); |
201 | return; |
202 | } |
203 | child = clkspec.args[0]; |
204 | |
205 | if (child != IMX6QDL_CLK_LDB_DI0_SEL && |
206 | child != IMX6QDL_CLK_LDB_DI1_SEL) |
207 | continue; |
208 | |
209 | sel = ldb_di_sel_by_clock_id(clock_id: parent); |
210 | if (sel < 0) { |
211 | pr_err("ccm: invalid ldb_di%d parent clock: %d\n" , |
212 | child == IMX6QDL_CLK_LDB_DI1_SEL, parent); |
213 | continue; |
214 | } |
215 | |
216 | if (child == IMX6QDL_CLK_LDB_DI0_SEL) |
217 | *ldb_di0_sel = sel; |
218 | if (child == IMX6QDL_CLK_LDB_DI1_SEL) |
219 | *ldb_di1_sel = sel; |
220 | } |
221 | } |
222 | |
223 | static bool pll6_bypassed(struct device_node *node) |
224 | { |
225 | int index, ret, num_clocks; |
226 | struct of_phandle_args clkspec; |
227 | |
228 | num_clocks = of_count_phandle_with_args(np: node, list_name: "assigned-clocks" , |
229 | cells_name: "#clock-cells" ); |
230 | if (num_clocks < 0) |
231 | return false; |
232 | |
233 | for (index = 0; index < num_clocks; index++) { |
234 | ret = of_parse_phandle_with_args(np: node, list_name: "assigned-clocks" , |
235 | cells_name: "#clock-cells" , index, |
236 | out_args: &clkspec); |
237 | if (ret < 0) |
238 | return false; |
239 | |
240 | if (clkspec.np == node && |
241 | clkspec.args[0] == IMX6QDL_PLL6_BYPASS) |
242 | break; |
243 | } |
244 | |
245 | /* PLL6 bypass is not part of the assigned clock list */ |
246 | if (index == num_clocks) |
247 | return false; |
248 | |
249 | ret = of_parse_phandle_with_args(np: node, list_name: "assigned-clock-parents" , |
250 | cells_name: "#clock-cells" , index, out_args: &clkspec); |
251 | |
252 | if (clkspec.args[0] != IMX6QDL_CLK_PLL6) |
253 | return true; |
254 | |
255 | return false; |
256 | } |
257 | |
258 | #define CCM_CCSR 0x0c |
259 | #define CCM_CS2CDR 0x2c |
260 | |
261 | #define CCSR_PLL3_SW_CLK_SEL BIT(0) |
262 | |
263 | #define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9 |
264 | #define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12 |
265 | |
266 | /* |
267 | * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk |
268 | * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the |
269 | * bypass clock source, since there is no CG bit for mmdc_ch1. |
270 | */ |
271 | static void mmdc_ch1_disable(void __iomem *ccm_base) |
272 | { |
273 | unsigned int reg; |
274 | |
275 | clk_set_parent(clk: hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, |
276 | parent: hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); |
277 | |
278 | /* Disable pll3_sw_clk by selecting the bypass clock source */ |
279 | reg = readl_relaxed(ccm_base + CCM_CCSR); |
280 | reg |= CCSR_PLL3_SW_CLK_SEL; |
281 | writel_relaxed(reg, ccm_base + CCM_CCSR); |
282 | } |
283 | |
284 | static void mmdc_ch1_reenable(void __iomem *ccm_base) |
285 | { |
286 | unsigned int reg; |
287 | |
288 | /* Enable pll3_sw_clk by disabling the bypass */ |
289 | reg = readl_relaxed(ccm_base + CCM_CCSR); |
290 | reg &= ~CCSR_PLL3_SW_CLK_SEL; |
291 | writel_relaxed(reg, ccm_base + CCM_CCSR); |
292 | } |
293 | |
294 | /* |
295 | * We have to follow a strict procedure when changing the LDB clock source, |
296 | * otherwise we risk introducing a glitch that can lock up the LDB divider. |
297 | * Things to keep in mind: |
298 | * |
299 | * 1. The current and new parent clock inputs to the mux must be disabled. |
300 | * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which |
301 | * has no CG bit. |
302 | * 3. pll2_pfd2_396m can not be gated if it is used as memory clock. |
303 | * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four |
304 | * options are in one mux and the PLL3 option along with three unused |
305 | * inputs is in a second mux. There is a third mux with two inputs used |
306 | * to decide between the first and second 4-port mux: |
307 | * |
308 | * pll5_video_div 0 --|\ |
309 | * pll2_pfd0_352m 1 --| |_ |
310 | * pll2_pfd2_396m 2 --| | `-|\ |
311 | * mmdc_ch1_axi 3 --|/ | | |
312 | * | |-- |
313 | * pll3_usb_otg 4 --|\ | | |
314 | * 5 --| |_,-|/ |
315 | * 6 --| | |
316 | * 7 --|/ |
317 | * |
318 | * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time. |
319 | * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below |
320 | * switches the parent to the bottom mux first and then manipulates the top |
321 | * mux to ensure that no glitch will enter the divider. |
322 | */ |
323 | static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) |
324 | { |
325 | unsigned int reg; |
326 | unsigned int sel[2][4]; |
327 | int i; |
328 | |
329 | reg = readl_relaxed(ccm_base + CCM_CS2CDR); |
330 | sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7; |
331 | sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7; |
332 | |
333 | sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0]; |
334 | sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0]; |
335 | |
336 | of_assigned_ldb_sels(node: np, ldb_di0_sel: &sel[0][3], ldb_di1_sel: &sel[1][3]); |
337 | |
338 | for (i = 0; i < 2; i++) { |
339 | /* Print a notice if a glitch might have been introduced already */ |
340 | if (sel[i][0] != 3) { |
341 | pr_notice("ccm: possible glitch: ldb_di%d_sel already changed from reset value: %d\n" , |
342 | i, sel[i][0]); |
343 | } |
344 | |
345 | if (sel[i][0] == sel[i][3]) |
346 | continue; |
347 | |
348 | /* Only switch to or from pll2_pfd2_396m if it is disabled */ |
349 | if ((sel[i][0] == 2 || sel[i][3] == 2) && |
350 | (clk_get_parent(clk: hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == |
351 | hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) { |
352 | pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n" , |
353 | i); |
354 | sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0]; |
355 | continue; |
356 | } |
357 | |
358 | /* First switch to the bottom mux */ |
359 | sel[i][1] = sel[i][0] | 4; |
360 | |
361 | /* Then configure the top mux before switching back to it */ |
362 | sel[i][2] = sel[i][3] | 4; |
363 | |
364 | pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n" , i, |
365 | sel[i][0], sel[i][1], sel[i][2], sel[i][3]); |
366 | } |
367 | |
368 | if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3]) |
369 | return; |
370 | |
371 | mmdc_ch1_disable(ccm_base); |
372 | |
373 | for (i = 1; i < 4; i++) { |
374 | reg = readl_relaxed(ccm_base + CCM_CS2CDR); |
375 | reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | |
376 | (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); |
377 | reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | |
378 | (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); |
379 | writel_relaxed(reg, ccm_base + CCM_CS2CDR); |
380 | } |
381 | |
382 | mmdc_ch1_reenable(ccm_base); |
383 | } |
384 | |
385 | #define CCM_ANALOG_PLL_VIDEO 0xa0 |
386 | #define CCM_ANALOG_PFD_480 0xf0 |
387 | #define CCM_ANALOG_PFD_528 0x100 |
388 | |
389 | #define PLL_ENABLE BIT(13) |
390 | |
391 | #define PFD0_CLKGATE BIT(7) |
392 | #define PFD1_CLKGATE BIT(15) |
393 | #define PFD2_CLKGATE BIT(23) |
394 | #define PFD3_CLKGATE BIT(31) |
395 | |
396 | static void disable_anatop_clocks(void __iomem *anatop_base) |
397 | { |
398 | unsigned int reg; |
399 | |
400 | /* Make sure PLL2 PFDs 0-2 are gated */ |
401 | reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); |
402 | /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */ |
403 | if (clk_get_parent(clk: hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == |
404 | hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk) |
405 | reg |= PFD0_CLKGATE | PFD1_CLKGATE; |
406 | else |
407 | reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE; |
408 | writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); |
409 | |
410 | /* Make sure PLL3 PFDs 0-3 are gated */ |
411 | reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); |
412 | reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE; |
413 | writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); |
414 | |
415 | /* Make sure PLL5 is disabled */ |
416 | reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); |
417 | reg &= ~PLL_ENABLE; |
418 | writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); |
419 | } |
420 | |
421 | static struct clk_hw * __init imx6q_obtain_fixed_clk_hw(struct device_node *np, |
422 | const char *name, |
423 | unsigned long rate) |
424 | { |
425 | struct clk *clk = of_clk_get_by_name(np, name); |
426 | struct clk_hw *hw; |
427 | |
428 | if (IS_ERR(ptr: clk)) |
429 | hw = imx_obtain_fixed_clock_hw(name, rate); |
430 | else |
431 | hw = __clk_get_hw(clk); |
432 | |
433 | return hw; |
434 | } |
435 | |
436 | static void __init imx6q_clocks_init(struct device_node *ccm_node) |
437 | { |
438 | struct device_node *np; |
439 | void __iomem *anatop_base, *base; |
440 | int ret; |
441 | |
442 | clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, |
443 | IMX6QDL_CLK_END), GFP_KERNEL); |
444 | if (WARN_ON(!clk_hw_data)) |
445 | return; |
446 | |
447 | clk_hw_data->num = IMX6QDL_CLK_END; |
448 | hws = clk_hw_data->hws; |
449 | |
450 | hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed(name: "dummy" , rate: 0); |
451 | |
452 | hws[IMX6QDL_CLK_CKIL] = imx6q_obtain_fixed_clk_hw(np: ccm_node, name: "ckil" , rate: 0); |
453 | hws[IMX6QDL_CLK_CKIH] = imx6q_obtain_fixed_clk_hw(np: ccm_node, name: "ckih1" , rate: 0); |
454 | hws[IMX6QDL_CLK_OSC] = imx6q_obtain_fixed_clk_hw(np: ccm_node, name: "osc" , rate: 0); |
455 | |
456 | /* Clock source from external clock via CLK1/2 PADs */ |
457 | hws[IMX6QDL_CLK_ANACLK1] = imx6q_obtain_fixed_clk_hw(np: ccm_node, name: "anaclk1" , rate: 0); |
458 | hws[IMX6QDL_CLK_ANACLK2] = imx6q_obtain_fixed_clk_hw(np: ccm_node, name: "anaclk2" , rate: 0); |
459 | |
460 | np = of_find_compatible_node(NULL, NULL, compat: "fsl,imx6q-anatop" ); |
461 | anatop_base = base = of_iomap(node: np, index: 0); |
462 | WARN_ON(!base); |
463 | of_node_put(node: np); |
464 | |
465 | /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ |
466 | if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { |
467 | post_div_table[1].div = 1; |
468 | post_div_table[2].div = 1; |
469 | video_div_table[1].div = 1; |
470 | video_div_table[3].div = 1; |
471 | } |
472 | |
473 | hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src" , base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
474 | hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src" , base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
475 | hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src" , base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
476 | hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src" , base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
477 | hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src" , base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
478 | hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src" , base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
479 | hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src" , base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
480 | |
481 | /* type name parent_name base div_mask */ |
482 | hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(type: IMX_PLLV3_SYS, name: "pll1" , parent_name: "osc" , base: base + 0x00, div_mask: 0x7f); |
483 | hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(type: IMX_PLLV3_GENERIC, name: "pll2" , parent_name: "osc" , base: base + 0x30, div_mask: 0x1); |
484 | hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(type: IMX_PLLV3_USB, name: "pll3" , parent_name: "osc" , base: base + 0x10, div_mask: 0x3); |
485 | hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(type: IMX_PLLV3_AV, name: "pll4" , parent_name: "osc" , base: base + 0x70, div_mask: 0x7f); |
486 | hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(type: IMX_PLLV3_AV, name: "pll5" , parent_name: "osc" , base: base + 0xa0, div_mask: 0x7f); |
487 | hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(type: IMX_PLLV3_ENET, name: "pll6" , parent_name: "osc" , base: base + 0xe0, div_mask: 0x3); |
488 | hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(type: IMX_PLLV3_USB, name: "pll7" , parent_name: "osc" , base: base + 0x20, div_mask: 0x3); |
489 | |
490 | hws[IMX6QDL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass" , base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); |
491 | hws[IMX6QDL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass" , base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); |
492 | hws[IMX6QDL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass" , base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); |
493 | hws[IMX6QDL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass" , base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); |
494 | hws[IMX6QDL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass" , base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); |
495 | hws[IMX6QDL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass" , base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); |
496 | hws[IMX6QDL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass" , base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); |
497 | |
498 | /* Do not bypass PLLs initially */ |
499 | clk_set_parent(clk: hws[IMX6QDL_PLL1_BYPASS]->clk, parent: hws[IMX6QDL_CLK_PLL1]->clk); |
500 | clk_set_parent(clk: hws[IMX6QDL_PLL2_BYPASS]->clk, parent: hws[IMX6QDL_CLK_PLL2]->clk); |
501 | clk_set_parent(clk: hws[IMX6QDL_PLL3_BYPASS]->clk, parent: hws[IMX6QDL_CLK_PLL3]->clk); |
502 | clk_set_parent(clk: hws[IMX6QDL_PLL4_BYPASS]->clk, parent: hws[IMX6QDL_CLK_PLL4]->clk); |
503 | clk_set_parent(clk: hws[IMX6QDL_PLL5_BYPASS]->clk, parent: hws[IMX6QDL_CLK_PLL5]->clk); |
504 | clk_set_parent(clk: hws[IMX6QDL_PLL6_BYPASS]->clk, parent: hws[IMX6QDL_CLK_PLL6]->clk); |
505 | clk_set_parent(clk: hws[IMX6QDL_PLL7_BYPASS]->clk, parent: hws[IMX6QDL_CLK_PLL7]->clk); |
506 | |
507 | hws[IMX6QDL_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys" , "pll1_bypass" , base + 0x00, 13); |
508 | hws[IMX6QDL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus" , "pll2_bypass" , base + 0x30, 13); |
509 | hws[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg" , "pll3_bypass" , base + 0x10, 13); |
510 | hws[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio" , "pll4_bypass" , base + 0x70, 13); |
511 | hws[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video" , "pll5_bypass" , base + 0xa0, 13); |
512 | hws[IMX6QDL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet" , "pll6_bypass" , base + 0xe0, 13); |
513 | hws[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host" , "pll7_bypass" , base + 0x20, 13); |
514 | |
515 | /* |
516 | * Bit 20 is the reserved and read-only bit, we do this only for: |
517 | * - Do nothing for usbphy clk_enable/disable |
518 | * - Keep refcount when do usbphy clk_enable/disable, in that case, |
519 | * the clk framework may need to enable/disable usbphy's parent |
520 | */ |
521 | hws[IMX6QDL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1" , "pll3_usb_otg" , base + 0x10, 20); |
522 | hws[IMX6QDL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2" , "pll7_usb_host" , base + 0x20, 20); |
523 | |
524 | /* |
525 | * usbphy*_gate needs to be on after system boots up, and software |
526 | * never needs to control it anymore. |
527 | */ |
528 | hws[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate" , "dummy" , base + 0x10, 6); |
529 | hws[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate" , "dummy" , base + 0x20, 6); |
530 | |
531 | /* |
532 | * The ENET PLL is special in that is has multiple outputs with |
533 | * different post-dividers that are all affected by the single bypass |
534 | * bit, so a single mux bit affects 3 independent branches of the clock |
535 | * tree. There is no good way to model this in the clock framework and |
536 | * dynamically changing the bypass bit, will yield unexpected results. |
537 | * So we treat any configuration that bypasses the ENET PLL as |
538 | * essentially static with the divider ratios reflecting the bypass |
539 | * status. |
540 | * |
541 | */ |
542 | if (!pll6_bypassed(node: ccm_node)) { |
543 | hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor(name: "sata_ref" , parent: "pll6_enet" , mult: 1, div: 5); |
544 | hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor(name: "pcie_ref" , parent: "pll6_enet" , mult: 1, div: 4); |
545 | hws[IMX6QDL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref" , "pll6_enet" , 0, |
546 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, |
547 | &imx_ccm_lock); |
548 | } else { |
549 | hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor(name: "sata_ref" , parent: "pll6_enet" , mult: 1, div: 1); |
550 | hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor(name: "pcie_ref" , parent: "pll6_enet" , mult: 1, div: 1); |
551 | hws[IMX6QDL_CLK_ENET_REF] = imx_clk_hw_fixed_factor(name: "enet_ref" , parent: "pll6_enet" , mult: 1, div: 1); |
552 | } |
553 | |
554 | hws[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_hw_gate("sata_ref_100m" , "sata_ref" , base + 0xe0, 20); |
555 | hws[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m" , "pcie_ref" , base + 0xe0, 19); |
556 | |
557 | hws[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel" , base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); |
558 | hws[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel" , base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); |
559 | |
560 | /* |
561 | * lvds1_gate and lvds2_gate are pseudo-gates. Both can be |
562 | * independently configured as clock inputs or outputs. We treat |
563 | * the "output_enable" bit as a gate, even though it's really just |
564 | * enabling clock output. Initially the gate bits are cleared, as |
565 | * otherwise the exclusive configuration gets locked in the setup done |
566 | * by software running before the clock driver, with no way to change |
567 | * it. |
568 | */ |
569 | writel(readl(addr: base + 0x160) & ~0x3c00, addr: base + 0x160); |
570 | hws[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_hw_gate_exclusive(name: "lvds1_gate" , parent: "lvds1_sel" , reg: base + 0x160, shift: 10, BIT(12)); |
571 | hws[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_hw_gate_exclusive(name: "lvds2_gate" , parent: "lvds2_sel" , reg: base + 0x160, shift: 11, BIT(13)); |
572 | |
573 | hws[IMX6QDL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive(name: "lvds1_in" , parent: "anaclk1" , reg: base + 0x160, shift: 12, BIT(10)); |
574 | hws[IMX6QDL_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive(name: "lvds2_in" , parent: "anaclk2" , reg: base + 0x160, shift: 13, BIT(11)); |
575 | |
576 | /* name parent_name reg idx */ |
577 | hws[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd(name: "pll2_pfd0_352m" , parent_name: "pll2_bus" , reg: base + 0x100, idx: 0); |
578 | hws[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd(name: "pll2_pfd1_594m" , parent_name: "pll2_bus" , reg: base + 0x100, idx: 1); |
579 | hws[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd(name: "pll2_pfd2_396m" , parent_name: "pll2_bus" , reg: base + 0x100, idx: 2); |
580 | hws[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_hw_pfd(name: "pll3_pfd0_720m" , parent_name: "pll3_usb_otg" , reg: base + 0xf0, idx: 0); |
581 | hws[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_hw_pfd(name: "pll3_pfd1_540m" , parent_name: "pll3_usb_otg" , reg: base + 0xf0, idx: 1); |
582 | hws[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_hw_pfd(name: "pll3_pfd2_508m" , parent_name: "pll3_usb_otg" , reg: base + 0xf0, idx: 2); |
583 | hws[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_hw_pfd(name: "pll3_pfd3_454m" , parent_name: "pll3_usb_otg" , reg: base + 0xf0, idx: 3); |
584 | |
585 | /* name parent_name mult div */ |
586 | hws[IMX6QDL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor(name: "pll2_198m" , parent: "pll2_pfd2_396m" , mult: 1, div: 2); |
587 | hws[IMX6QDL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor(name: "pll3_120m" , parent: "pll3_usb_otg" , mult: 1, div: 4); |
588 | hws[IMX6QDL_CLK_PLL3_80M] = imx_clk_hw_fixed_factor(name: "pll3_80m" , parent: "pll3_usb_otg" , mult: 1, div: 6); |
589 | hws[IMX6QDL_CLK_PLL3_60M] = imx_clk_hw_fixed_factor(name: "pll3_60m" , parent: "pll3_usb_otg" , mult: 1, div: 8); |
590 | hws[IMX6QDL_CLK_TWD] = imx_clk_hw_fixed_factor(name: "twd" , parent: "arm" , mult: 1, div: 2); |
591 | hws[IMX6QDL_CLK_GPT_3M] = imx_clk_hw_fixed_factor(name: "gpt_3m" , parent: "osc" , mult: 1, div: 8); |
592 | hws[IMX6QDL_CLK_VIDEO_27M] = imx_clk_hw_fixed_factor(name: "video_27m" , parent: "pll3_pfd1_540m" , mult: 1, div: 20); |
593 | if (clk_on_imx6dl() || clk_on_imx6qp()) { |
594 | hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_fixed_factor(name: "gpu2d_axi" , parent: "mmdc_ch0_axi_podf" , mult: 1, div: 1); |
595 | hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_fixed_factor(name: "gpu3d_axi" , parent: "mmdc_ch0_axi_podf" , mult: 1, div: 1); |
596 | } |
597 | |
598 | hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div" , "pll4_audio" , CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); |
599 | if (clk_on_imx6q() || clk_on_imx6qp()) |
600 | hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = imx_clk_hw_fixed_factor(name: "pll4_audio_div" , parent: "pll4_post_div" , mult: 1, div: 1); |
601 | else |
602 | hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div" , "pll4_post_div" , CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); |
603 | hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div" , "pll5_video" , CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); |
604 | hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div" , "pll5_post_div" , CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); |
605 | |
606 | np = ccm_node; |
607 | base = of_iomap(node: np, index: 0); |
608 | WARN_ON(!base); |
609 | |
610 | /* name reg shift width parent_names num_parents */ |
611 | hws[IMX6QDL_CLK_STEP] = imx_clk_hw_mux("step" , base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); |
612 | hws[IMX6QDL_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw" , base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); |
613 | hws[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre" , base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); |
614 | hws[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre" , base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); |
615 | hws[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel" , base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); |
616 | hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel" , base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); |
617 | hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel" , base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); |
618 | hws[IMX6QDL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel" , base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); |
619 | hws[IMX6QDL_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel" , base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); |
620 | hws[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel" , base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); |
621 | if (clk_on_imx6q()) { |
622 | hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_mux("gpu2d_axi" , base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); |
623 | hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_mux("gpu3d_axi" , base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); |
624 | } |
625 | if (clk_on_imx6qp()) { |
626 | hws[IMX6QDL_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel" , base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); |
627 | hws[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel" , base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); |
628 | hws[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_hw_mux("ipg_per_sel" , base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels)); |
629 | hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel" , base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); |
630 | hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel" , base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2)); |
631 | } else if (clk_on_imx6dl()) { |
632 | hws[IMX6QDL_CLK_MLB_SEL] = imx_clk_hw_mux("mlb_sel" , base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); |
633 | } else { |
634 | hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel" , base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); |
635 | } |
636 | hws[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_hw_mux("gpu3d_core_sel" , base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); |
637 | if (clk_on_imx6dl()) |
638 | hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel" , base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); |
639 | else |
640 | hws[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_hw_mux("gpu3d_shader_sel" , base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); |
641 | hws[IMX6QDL_CLK_IPU1_SEL] = imx_clk_hw_mux("ipu1_sel" , base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); |
642 | hws[IMX6QDL_CLK_IPU2_SEL] = imx_clk_hw_mux("ipu2_sel" , base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); |
643 | |
644 | disable_anatop_clocks(anatop_base); |
645 | |
646 | imx_mmdc_mask_handshake(ccm_base: base, chn: 1); |
647 | |
648 | if (clk_on_imx6qp()) { |
649 | hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_flags("ldb_di0_sel" , base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); |
650 | hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_flags("ldb_di1_sel" , base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); |
651 | } else { |
652 | /* |
653 | * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware |
654 | * bug. Set the muxes to the requested values before registering the |
655 | * ldb_di_sel clocks. |
656 | */ |
657 | init_ldb_clks(np, ccm_base: base); |
658 | |
659 | hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_ldb("ldb_di0_sel" , base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); |
660 | hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_ldb("ldb_di1_sel" , base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); |
661 | } |
662 | |
663 | hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel" , base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
664 | hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel" , base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
665 | hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel" , base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
666 | hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di1_pre_sel" , base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
667 | hws[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_hw_mux("hsi_tx_sel" , base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); |
668 | hws[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_hw_mux("pcie_axi_sel" , base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); |
669 | |
670 | if (clk_on_imx6qp()) { |
671 | hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel" , base + 0x34, 0, 3, ipu1_di0_sels_2, ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT); |
672 | hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel" , base + 0x34, 9, 3, ipu1_di1_sels_2, ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT); |
673 | hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel" , base + 0x38, 0, 3, ipu2_di0_sels_2, ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT); |
674 | hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel" , base + 0x38, 9, 3, ipu2_di1_sels_2, ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT); |
675 | hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel" , base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); |
676 | hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel" , base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); |
677 | hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel" , base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); |
678 | hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel" , base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); |
679 | hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel" , base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); |
680 | hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel" , base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); |
681 | hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_mux("usdhc4_sel" , base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); |
682 | hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel" , base + 0x2c, 15, 3, enfc_sels_2, ARRAY_SIZE(enfc_sels_2)); |
683 | hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_mux("eim_sel" , base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels)); |
684 | hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel" , base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); |
685 | hws[IMX6QDL_CLK_PRE_AXI] = imx_clk_hw_mux("pre_axi" , base + 0x18, 1, 1, pre_axi_sels, ARRAY_SIZE(pre_axi_sels)); |
686 | } else { |
687 | hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel" , base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); |
688 | hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel" , base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); |
689 | hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel" , base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); |
690 | hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel" , base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); |
691 | hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux(name: "ssi1_sel" , reg: base + 0x1c, shift: 10, width: 2, parents: ssi_sels, ARRAY_SIZE(ssi_sels), fixup: imx_cscmr1_fixup); |
692 | hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux(name: "ssi2_sel" , reg: base + 0x1c, shift: 12, width: 2, parents: ssi_sels, ARRAY_SIZE(ssi_sels), fixup: imx_cscmr1_fixup); |
693 | hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux(name: "ssi3_sel" , reg: base + 0x1c, shift: 14, width: 2, parents: ssi_sels, ARRAY_SIZE(ssi_sels), fixup: imx_cscmr1_fixup); |
694 | hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux(name: "usdhc1_sel" , reg: base + 0x1c, shift: 16, width: 1, parents: usdhc_sels, ARRAY_SIZE(usdhc_sels), fixup: imx_cscmr1_fixup); |
695 | hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux(name: "usdhc2_sel" , reg: base + 0x1c, shift: 17, width: 1, parents: usdhc_sels, ARRAY_SIZE(usdhc_sels), fixup: imx_cscmr1_fixup); |
696 | hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux(name: "usdhc3_sel" , reg: base + 0x1c, shift: 18, width: 1, parents: usdhc_sels, ARRAY_SIZE(usdhc_sels), fixup: imx_cscmr1_fixup); |
697 | hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux(name: "usdhc4_sel" , reg: base + 0x1c, shift: 19, width: 1, parents: usdhc_sels, ARRAY_SIZE(usdhc_sels), fixup: imx_cscmr1_fixup); |
698 | hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel" , base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); |
699 | hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_fixup_mux(name: "eim_sel" , reg: base + 0x1c, shift: 27, width: 2, parents: eim_sels, ARRAY_SIZE(eim_sels), fixup: imx_cscmr1_fixup); |
700 | hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_fixup_mux(name: "eim_slow_sel" , reg: base + 0x1c, shift: 29, width: 2, parents: eim_slow_sels, ARRAY_SIZE(eim_slow_sels), fixup: imx_cscmr1_fixup); |
701 | } |
702 | |
703 | hws[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_hw_mux("vdo_axi_sel" , base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); |
704 | hws[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_hw_mux("vpu_axi_sel" , base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); |
705 | hws[IMX6QDL_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel" , base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); |
706 | hws[IMX6QDL_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel" , base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); |
707 | hws[IMX6QDL_CLK_CKO] = imx_clk_hw_mux("cko" , base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); |
708 | |
709 | /* name reg shift width busy: reg, shift parent_names num_parents */ |
710 | hws[IMX6QDL_CLK_PERIPH] = imx_clk_hw_busy_mux(name: "periph" , reg: base + 0x14, shift: 25, width: 1, busy_reg: base + 0x48, busy_shift: 5, parent_names: periph_sels, ARRAY_SIZE(periph_sels)); |
711 | hws[IMX6QDL_CLK_PERIPH2] = imx_clk_hw_busy_mux(name: "periph2" , reg: base + 0x14, shift: 26, width: 1, busy_reg: base + 0x48, busy_shift: 3, parent_names: periph2_sels, ARRAY_SIZE(periph2_sels)); |
712 | |
713 | /* name parent_name reg shift width */ |
714 | hws[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2" , "periph_clk2_sel" , base + 0x14, 27, 3); |
715 | hws[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2" , "periph2_clk2_sel" , base + 0x14, 0, 3); |
716 | hws[IMX6QDL_CLK_IPG] = imx_clk_hw_divider("ipg" , "ahb" , base + 0x14, 8, 2); |
717 | hws[IMX6QDL_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred" , "esai_sel" , base + 0x28, 9, 3); |
718 | hws[IMX6QDL_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf" , "esai_pred" , base + 0x28, 25, 3); |
719 | hws[IMX6QDL_CLK_ASRC_PRED] = imx_clk_hw_divider("asrc_pred" , "asrc_sel" , base + 0x30, 12, 3); |
720 | hws[IMX6QDL_CLK_ASRC_PODF] = imx_clk_hw_divider("asrc_podf" , "asrc_pred" , base + 0x30, 9, 3); |
721 | hws[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred" , "spdif_sel" , base + 0x30, 25, 3); |
722 | hws[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf" , "spdif_pred" , base + 0x30, 22, 3); |
723 | |
724 | if (clk_on_imx6qp()) { |
725 | hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_divider("ipg_per" , "ipg_per_sel" , base + 0x1c, 0, 6); |
726 | hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root" , "ecspi_sel" , base + 0x38, 19, 6); |
727 | hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root" , "can_sel" , base + 0x20, 2, 6); |
728 | hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf" , "uart_sel" , base + 0x24, 0, 6); |
729 | hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor(name: "ldb_di0_div_3_5" , parent: "ldb_di0" , mult: 2, div: 7); |
730 | hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor(name: "ldb_di1_div_3_5" , parent: "ldb_di1" , mult: 2, div: 7); |
731 | } else { |
732 | hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root" , "pll3_60m" , base + 0x38, 19, 6); |
733 | hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root" , "pll3_60m" , base + 0x20, 2, 6); |
734 | hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_fixup_divider(name: "ipg_per" , parent: "ipg" , reg: base + 0x1c, shift: 0, width: 6, fixup: imx_cscmr1_fixup); |
735 | hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf" , "pll3_80m" , base + 0x24, 0, 6); |
736 | hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor(name: "ldb_di0_div_3_5" , parent: "ldb_di0_sel" , mult: 2, div: 7); |
737 | hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor(name: "ldb_di1_div_3_5" , parent: "ldb_di1_sel" , mult: 2, div: 7); |
738 | } |
739 | |
740 | if (clk_on_imx6dl()) |
741 | hws[IMX6QDL_CLK_MLB_PODF] = imx_clk_hw_divider("mlb_podf" , "mlb_sel" , base + 0x18, 23, 3); |
742 | else |
743 | hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf" , "gpu2d_core_sel" , base + 0x18, 23, 3); |
744 | hws[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_hw_divider("gpu3d_core_podf" , "gpu3d_core_sel" , base + 0x18, 26, 3); |
745 | if (clk_on_imx6dl()) |
746 | hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf" , "gpu2d_core_sel" , base + 0x18, 29, 3); |
747 | else |
748 | hws[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_hw_divider("gpu3d_shader" , "gpu3d_shader_sel" , base + 0x18, 29, 3); |
749 | hws[IMX6QDL_CLK_IPU1_PODF] = imx_clk_hw_divider("ipu1_podf" , "ipu1_sel" , base + 0x3c, 11, 3); |
750 | hws[IMX6QDL_CLK_IPU2_PODF] = imx_clk_hw_divider("ipu2_podf" , "ipu2_sel" , base + 0x3c, 16, 3); |
751 | hws[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_hw_divider_flags("ldb_di0_podf" , "ldb_di0_div_3_5" , base + 0x20, 10, 1, 0); |
752 | hws[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_hw_divider_flags("ldb_di1_podf" , "ldb_di1_div_3_5" , base + 0x20, 11, 1, 0); |
753 | hws[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_hw_divider("ipu1_di0_pre" , "ipu1_di0_pre_sel" , base + 0x34, 3, 3); |
754 | hws[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_hw_divider("ipu1_di1_pre" , "ipu1_di1_pre_sel" , base + 0x34, 12, 3); |
755 | hws[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_hw_divider("ipu2_di0_pre" , "ipu2_di0_pre_sel" , base + 0x38, 3, 3); |
756 | hws[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_hw_divider("ipu2_di1_pre" , "ipu2_di1_pre_sel" , base + 0x38, 12, 3); |
757 | hws[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_hw_divider("hsi_tx_podf" , "hsi_tx_sel" , base + 0x30, 29, 3); |
758 | hws[IMX6QDL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred" , "ssi1_sel" , base + 0x28, 6, 3); |
759 | hws[IMX6QDL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf" , "ssi1_pred" , base + 0x28, 0, 6); |
760 | hws[IMX6QDL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred" , "ssi2_sel" , base + 0x2c, 6, 3); |
761 | hws[IMX6QDL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf" , "ssi2_pred" , base + 0x2c, 0, 6); |
762 | hws[IMX6QDL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred" , "ssi3_sel" , base + 0x28, 22, 3); |
763 | hws[IMX6QDL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf" , "ssi3_pred" , base + 0x28, 16, 6); |
764 | hws[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf" , "usdhc1_sel" , base + 0x24, 11, 3); |
765 | hws[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf" , "usdhc2_sel" , base + 0x24, 16, 3); |
766 | hws[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf" , "usdhc3_sel" , base + 0x24, 19, 3); |
767 | hws[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf" , "usdhc4_sel" , base + 0x24, 22, 3); |
768 | hws[IMX6QDL_CLK_ENFC_PRED] = imx_clk_hw_divider("enfc_pred" , "enfc_sel" , base + 0x2c, 18, 3); |
769 | hws[IMX6QDL_CLK_ENFC_PODF] = imx_clk_hw_divider("enfc_podf" , "enfc_pred" , base + 0x2c, 21, 6); |
770 | if (clk_on_imx6qp()) { |
771 | hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_divider("eim_podf" , "eim_sel" , base + 0x1c, 20, 3); |
772 | hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf" , "eim_slow_sel" , base + 0x1c, 23, 3); |
773 | } else { |
774 | hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_fixup_divider(name: "eim_podf" , parent: "eim_sel" , reg: base + 0x1c, shift: 20, width: 3, fixup: imx_cscmr1_fixup); |
775 | hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_fixup_divider(name: "eim_slow_podf" , parent: "eim_slow_sel" , reg: base + 0x1c, shift: 23, width: 3, fixup: imx_cscmr1_fixup); |
776 | } |
777 | |
778 | hws[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_hw_divider("vpu_axi_podf" , "vpu_axi_sel" , base + 0x24, 25, 3); |
779 | hws[IMX6QDL_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf" , "cko1_sel" , base + 0x60, 4, 3); |
780 | hws[IMX6QDL_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf" , "cko2_sel" , base + 0x60, 21, 3); |
781 | |
782 | /* name parent_name reg shift width busy: reg, shift */ |
783 | hws[IMX6QDL_CLK_AXI] = imx_clk_hw_busy_divider(name: "axi" , parent_name: "axi_sel" , reg: base + 0x14, shift: 16, width: 3, busy_reg: base + 0x48, busy_shift: 0); |
784 | hws[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_hw_busy_divider(name: "mmdc_ch0_axi_podf" , parent_name: "periph" , reg: base + 0x14, shift: 19, width: 3, busy_reg: base + 0x48, busy_shift: 4); |
785 | if (clk_on_imx6qp()) { |
786 | hws[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_hw_gate("mmdc_ch1_axi_cg" , "periph2" , base + 0x4, 18); |
787 | hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider(name: "mmdc_ch1_axi_podf" , parent_name: "mmdc_ch1_axi_cg" , reg: base + 0x14, shift: 3, width: 3, busy_reg: base + 0x48, busy_shift: 2); |
788 | } else { |
789 | hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider(name: "mmdc_ch1_axi_podf" , parent_name: "periph2" , reg: base + 0x14, shift: 3, width: 3, busy_reg: base + 0x48, busy_shift: 2); |
790 | } |
791 | hws[IMX6QDL_CLK_ARM] = imx_clk_hw_busy_divider(name: "arm" , parent_name: "pll1_sw" , reg: base + 0x10, shift: 0, width: 3, busy_reg: base + 0x48, busy_shift: 16); |
792 | hws[IMX6QDL_CLK_AHB] = imx_clk_hw_busy_divider(name: "ahb" , parent_name: "periph" , reg: base + 0x14, shift: 10, width: 3, busy_reg: base + 0x48, busy_shift: 1); |
793 | |
794 | /* name parent_name reg shift */ |
795 | hws[IMX6QDL_CLK_APBH_DMA] = imx_clk_hw_gate2("apbh_dma" , "usdhc3" , base + 0x68, 4); |
796 | hws[IMX6QDL_CLK_ASRC] = imx_clk_hw_gate2_shared("asrc" , "asrc_podf" , base + 0x68, 6, &share_count_asrc); |
797 | hws[IMX6QDL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg" , "ahb" , base + 0x68, 6, &share_count_asrc); |
798 | hws[IMX6QDL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem" , "ahb" , base + 0x68, 6, &share_count_asrc); |
799 | hws[IMX6QDL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem" , "ahb" , base + 0x68, 8); |
800 | hws[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk" , "ahb" , base + 0x68, 10); |
801 | hws[IMX6QDL_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg" , "ipg" , base + 0x68, 12); |
802 | hws[IMX6QDL_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg" , "ipg" , base + 0x68, 14); |
803 | hws[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial" , "can_root" , base + 0x68, 16); |
804 | hws[IMX6QDL_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg" , "ipg" , base + 0x68, 18); |
805 | hws[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial" , "can_root" , base + 0x68, 20); |
806 | hws[IMX6QDL_CLK_DCIC1] = imx_clk_hw_gate2("dcic1" , "ipu1_podf" , base + 0x68, 24); |
807 | hws[IMX6QDL_CLK_DCIC2] = imx_clk_hw_gate2("dcic2" , "ipu2_podf" , base + 0x68, 26); |
808 | hws[IMX6QDL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1" , "ecspi_root" , base + 0x6c, 0); |
809 | hws[IMX6QDL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2" , "ecspi_root" , base + 0x6c, 2); |
810 | hws[IMX6QDL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3" , "ecspi_root" , base + 0x6c, 4); |
811 | hws[IMX6QDL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4" , "ecspi_root" , base + 0x6c, 6); |
812 | if (clk_on_imx6dl()) |
813 | hws[IMX6DL_CLK_I2C4] = imx_clk_hw_gate2("i2c4" , "ipg_per" , base + 0x6c, 8); |
814 | else |
815 | hws[IMX6Q_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5" , "ecspi_root" , base + 0x6c, 8); |
816 | hws[IMX6QDL_CLK_ENET] = imx_clk_hw_gate2("enet" , "ipg" , base + 0x6c, 10); |
817 | hws[IMX6QDL_CLK_EPIT1] = imx_clk_hw_gate2("epit1" , "ipg" , base + 0x6c, 12); |
818 | hws[IMX6QDL_CLK_EPIT2] = imx_clk_hw_gate2("epit2" , "ipg" , base + 0x6c, 14); |
819 | hws[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal" , "esai_podf" , base + 0x6c, 16, &share_count_esai); |
820 | hws[IMX6QDL_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg" , "ahb" , base + 0x6c, 16, &share_count_esai); |
821 | hws[IMX6QDL_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem" , "ahb" , base + 0x6c, 16, &share_count_esai); |
822 | hws[IMX6QDL_CLK_GPT_IPG] = imx_clk_hw_gate2("gpt_ipg" , "ipg" , base + 0x6c, 20); |
823 | hws[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_hw_gate2("gpt_ipg_per" , "ipg_per" , base + 0x6c, 22); |
824 | hws[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_hw_gate2("gpu2d_core" , "gpu2d_core_podf" , base + 0x6c, 24); |
825 | hws[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_hw_gate2("gpu3d_core" , "gpu3d_core_podf" , base + 0x6c, 26); |
826 | hws[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_hw_gate2("hdmi_iahb" , "ahb" , base + 0x70, 0); |
827 | hws[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_hw_gate2("hdmi_isfr" , "mipi_core_cfg" , base + 0x70, 4); |
828 | hws[IMX6QDL_CLK_I2C1] = imx_clk_hw_gate2("i2c1" , "ipg_per" , base + 0x70, 6); |
829 | hws[IMX6QDL_CLK_I2C2] = imx_clk_hw_gate2("i2c2" , "ipg_per" , base + 0x70, 8); |
830 | hws[IMX6QDL_CLK_I2C3] = imx_clk_hw_gate2("i2c3" , "ipg_per" , base + 0x70, 10); |
831 | hws[IMX6QDL_CLK_IIM] = imx_clk_hw_gate2("iim" , "ipg" , base + 0x70, 12); |
832 | hws[IMX6QDL_CLK_ENFC] = imx_clk_hw_gate2("enfc" , "enfc_podf" , base + 0x70, 14); |
833 | hws[IMX6QDL_CLK_VDOA] = imx_clk_hw_gate2("vdoa" , "vdo_axi" , base + 0x70, 26); |
834 | hws[IMX6QDL_CLK_IPU1] = imx_clk_hw_gate2("ipu1" , "ipu1_podf" , base + 0x74, 0); |
835 | hws[IMX6QDL_CLK_IPU1_DI0] = imx_clk_hw_gate2("ipu1_di0" , "ipu1_di0_sel" , base + 0x74, 2); |
836 | hws[IMX6QDL_CLK_IPU1_DI1] = imx_clk_hw_gate2("ipu1_di1" , "ipu1_di1_sel" , base + 0x74, 4); |
837 | hws[IMX6QDL_CLK_IPU2] = imx_clk_hw_gate2("ipu2" , "ipu2_podf" , base + 0x74, 6); |
838 | hws[IMX6QDL_CLK_IPU2_DI0] = imx_clk_hw_gate2("ipu2_di0" , "ipu2_di0_sel" , base + 0x74, 8); |
839 | if (clk_on_imx6qp()) { |
840 | hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0" , "ldb_di0_sel" , base + 0x74, 12); |
841 | hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1" , "ldb_di1_sel" , base + 0x74, 14); |
842 | } else { |
843 | hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0" , "ldb_di0_podf" , base + 0x74, 12); |
844 | hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1" , "ldb_di1_podf" , base + 0x74, 14); |
845 | } |
846 | hws[IMX6QDL_CLK_IPU2_DI1] = imx_clk_hw_gate2("ipu2_di1" , "ipu2_di1_sel" , base + 0x74, 10); |
847 | hws[IMX6QDL_CLK_HSI_TX] = imx_clk_hw_gate2_shared("hsi_tx" , "hsi_tx_podf" , base + 0x74, 16, &share_count_mipi_core_cfg); |
848 | hws[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_hw_gate2_shared("mipi_core_cfg" , "video_27m" , base + 0x74, 16, &share_count_mipi_core_cfg); |
849 | hws[IMX6QDL_CLK_MIPI_IPG] = imx_clk_hw_gate2_shared("mipi_ipg" , "ipg" , base + 0x74, 16, &share_count_mipi_core_cfg); |
850 | |
851 | if (clk_on_imx6dl()) |
852 | /* |
853 | * The multiplexer and divider of the imx6q clock gpu2d get |
854 | * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. |
855 | */ |
856 | hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb" , "mlb_podf" , base + 0x74, 18); |
857 | else |
858 | hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb" , "axi" , base + 0x74, 18); |
859 | hws[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_hw_gate2_flags("mmdc_ch0_axi" , "mmdc_ch0_axi_podf" , base + 0x74, 20, CLK_IS_CRITICAL); |
860 | hws[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_hw_gate2("mmdc_ch1_axi" , "mmdc_ch1_axi_podf" , base + 0x74, 22); |
861 | hws[IMX6QDL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg" , "ipg" , base + 0x74, 24, CLK_IS_CRITICAL); |
862 | hws[IMX6QDL_CLK_OCRAM] = imx_clk_hw_gate2("ocram" , "ahb" , base + 0x74, 28); |
863 | hws[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_hw_gate2("openvg_axi" , "axi" , base + 0x74, 30); |
864 | hws[IMX6QDL_CLK_PCIE_AXI] = imx_clk_hw_gate2("pcie_axi" , "pcie_axi_sel" , base + 0x78, 0); |
865 | hws[IMX6QDL_CLK_PER1_BCH] = imx_clk_hw_gate2("per1_bch" , "usdhc3" , base + 0x78, 12); |
866 | hws[IMX6QDL_CLK_PWM1] = imx_clk_hw_gate2("pwm1" , "ipg_per" , base + 0x78, 16); |
867 | hws[IMX6QDL_CLK_PWM2] = imx_clk_hw_gate2("pwm2" , "ipg_per" , base + 0x78, 18); |
868 | hws[IMX6QDL_CLK_PWM3] = imx_clk_hw_gate2("pwm3" , "ipg_per" , base + 0x78, 20); |
869 | hws[IMX6QDL_CLK_PWM4] = imx_clk_hw_gate2("pwm4" , "ipg_per" , base + 0x78, 22); |
870 | hws[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb" , "usdhc3" , base + 0x78, 24); |
871 | hws[IMX6QDL_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch" , "usdhc4" , base + 0x78, 26); |
872 | hws[IMX6QDL_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io" , "enfc" , base + 0x78, 28); |
873 | hws[IMX6QDL_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb" , "usdhc3" , base + 0x78, 30); |
874 | hws[IMX6QDL_CLK_ROM] = imx_clk_hw_gate2_flags("rom" , "ahb" , base + 0x7c, 0, CLK_IS_CRITICAL); |
875 | hws[IMX6QDL_CLK_SATA] = imx_clk_hw_gate2("sata" , "ahb" , base + 0x7c, 4); |
876 | hws[IMX6QDL_CLK_SDMA] = imx_clk_hw_gate2("sdma" , "ahb" , base + 0x7c, 6); |
877 | hws[IMX6QDL_CLK_SPBA] = imx_clk_hw_gate2("spba" , "ipg" , base + 0x7c, 12); |
878 | hws[IMX6QDL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif" , "spdif_podf" , base + 0x7c, 14, &share_count_spdif); |
879 | hws[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk" , "ipg" , base + 0x7c, 14, &share_count_spdif); |
880 | hws[IMX6QDL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg" , "ipg" , base + 0x7c, 18, &share_count_ssi1); |
881 | hws[IMX6QDL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg" , "ipg" , base + 0x7c, 20, &share_count_ssi2); |
882 | hws[IMX6QDL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg" , "ipg" , base + 0x7c, 22, &share_count_ssi3); |
883 | hws[IMX6QDL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1" , "ssi1_podf" , base + 0x7c, 18, &share_count_ssi1); |
884 | hws[IMX6QDL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2" , "ssi2_podf" , base + 0x7c, 20, &share_count_ssi2); |
885 | hws[IMX6QDL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3" , "ssi3_podf" , base + 0x7c, 22, &share_count_ssi3); |
886 | hws[IMX6QDL_CLK_UART_IPG] = imx_clk_hw_gate2("uart_ipg" , "ipg" , base + 0x7c, 24); |
887 | hws[IMX6QDL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial" , "uart_serial_podf" , base + 0x7c, 26); |
888 | hws[IMX6QDL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3" , "ipg" , base + 0x80, 0); |
889 | hws[IMX6QDL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1" , "usdhc1_podf" , base + 0x80, 2); |
890 | hws[IMX6QDL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2" , "usdhc2_podf" , base + 0x80, 4); |
891 | hws[IMX6QDL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3" , "usdhc3_podf" , base + 0x80, 6); |
892 | hws[IMX6QDL_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4" , "usdhc4_podf" , base + 0x80, 8); |
893 | hws[IMX6QDL_CLK_EIM_SLOW] = imx_clk_hw_gate2("eim_slow" , "eim_slow_podf" , base + 0x80, 10); |
894 | hws[IMX6QDL_CLK_VDO_AXI] = imx_clk_hw_gate2("vdo_axi" , "vdo_axi_sel" , base + 0x80, 12); |
895 | hws[IMX6QDL_CLK_VPU_AXI] = imx_clk_hw_gate2("vpu_axi" , "vpu_axi_podf" , base + 0x80, 14); |
896 | if (clk_on_imx6qp()) { |
897 | hws[IMX6QDL_CLK_PRE0] = imx_clk_hw_gate2("pre0" , "pre_axi" , base + 0x80, 16); |
898 | hws[IMX6QDL_CLK_PRE1] = imx_clk_hw_gate2("pre1" , "pre_axi" , base + 0x80, 18); |
899 | hws[IMX6QDL_CLK_PRE2] = imx_clk_hw_gate2("pre2" , "pre_axi" , base + 0x80, 20); |
900 | hws[IMX6QDL_CLK_PRE3] = imx_clk_hw_gate2("pre3" , "pre_axi" , base + 0x80, 22); |
901 | hws[IMX6QDL_CLK_PRG0_AXI] = imx_clk_hw_gate2_shared("prg0_axi" , "ipu1_podf" , base + 0x80, 24, &share_count_prg0); |
902 | hws[IMX6QDL_CLK_PRG1_AXI] = imx_clk_hw_gate2_shared("prg1_axi" , "ipu2_podf" , base + 0x80, 26, &share_count_prg1); |
903 | hws[IMX6QDL_CLK_PRG0_APB] = imx_clk_hw_gate2_shared("prg0_apb" , "ipg" , base + 0x80, 24, &share_count_prg0); |
904 | hws[IMX6QDL_CLK_PRG1_APB] = imx_clk_hw_gate2_shared("prg1_apb" , "ipg" , base + 0x80, 26, &share_count_prg1); |
905 | } |
906 | hws[IMX6QDL_CLK_CKO1] = imx_clk_hw_gate("cko1" , "cko1_podf" , base + 0x60, 7); |
907 | hws[IMX6QDL_CLK_CKO2] = imx_clk_hw_gate("cko2" , "cko2_podf" , base + 0x60, 24); |
908 | |
909 | /* |
910 | * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it |
911 | * to clock gpt_ipg_per to ease the gpt driver code. |
912 | */ |
913 | if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) |
914 | hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER]; |
915 | |
916 | hws[IMX6QDL_CLK_ENET_REF_PAD] = imx6q_obtain_fixed_clk_hw(np: ccm_node, name: "enet_ref_pad" , rate: 0); |
917 | |
918 | hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux(name: "enet_ref_sel" , compatible: "fsl,imx6q-iomuxc-gpr" , |
919 | IOMUXC_GPR1, parent_names: enet_ref_sels, ARRAY_SIZE(enet_ref_sels), |
920 | mux_table: enet_ref_sels_table, mask: enet_ref_sels_table_mask); |
921 | |
922 | imx_check_clk_hws(clks: hws, IMX6QDL_CLK_END); |
923 | |
924 | of_clk_add_hw_provider(np, get: of_clk_hw_onecell_get, data: clk_hw_data); |
925 | |
926 | clk_hw_register_clkdev(hws[IMX6QDL_CLK_ENET_REF], "enet_ref" , NULL); |
927 | |
928 | clk_set_rate(clk: hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, rate: 540000000); |
929 | if (clk_on_imx6dl()) |
930 | clk_set_parent(clk: hws[IMX6QDL_CLK_IPU1_SEL]->clk, parent: hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); |
931 | |
932 | clk_set_parent(clk: hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, parent: hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); |
933 | clk_set_parent(clk: hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, parent: hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); |
934 | clk_set_parent(clk: hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, parent: hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); |
935 | clk_set_parent(clk: hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, parent: hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); |
936 | clk_set_parent(clk: hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, parent: hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk); |
937 | clk_set_parent(clk: hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, parent: hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk); |
938 | clk_set_parent(clk: hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, parent: hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk); |
939 | clk_set_parent(clk: hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, parent: hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk); |
940 | |
941 | /* |
942 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, |
943 | * We can not get the 100MHz from the pll2_pfd0_352m. |
944 | * So choose pll2_pfd2_396m as enfc_sel's parent. |
945 | */ |
946 | clk_set_parent(clk: hws[IMX6QDL_CLK_ENFC_SEL]->clk, parent: hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk); |
947 | |
948 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
949 | clk_prepare_enable(clk: hws[IMX6QDL_CLK_USBPHY1_GATE]->clk); |
950 | clk_prepare_enable(clk: hws[IMX6QDL_CLK_USBPHY2_GATE]->clk); |
951 | } |
952 | |
953 | /* |
954 | * Let's initially set up CLKO with OSC24M, since this configuration |
955 | * is widely used by imx6q board designs to clock audio codec. |
956 | */ |
957 | ret = clk_set_parent(clk: hws[IMX6QDL_CLK_CKO2_SEL]->clk, parent: hws[IMX6QDL_CLK_OSC]->clk); |
958 | if (!ret) |
959 | ret = clk_set_parent(clk: hws[IMX6QDL_CLK_CKO]->clk, parent: hws[IMX6QDL_CLK_CKO2]->clk); |
960 | if (ret) |
961 | pr_warn("failed to set up CLKO: %d\n" , ret); |
962 | |
963 | /* Audio-related clocks configuration */ |
964 | clk_set_parent(clk: hws[IMX6QDL_CLK_SPDIF_SEL]->clk, parent: hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk); |
965 | |
966 | /* All existing boards with PCIe use LVDS1 */ |
967 | if (IS_ENABLED(CONFIG_PCI_IMX6)) |
968 | clk_set_parent(clk: hws[IMX6QDL_CLK_LVDS1_SEL]->clk, parent: hws[IMX6QDL_CLK_SATA_REF_100M]->clk); |
969 | |
970 | /* |
971 | * Initialize the GPU clock muxes, so that the maximum specified clock |
972 | * rates for the respective SoC are not exceeded. |
973 | */ |
974 | if (clk_on_imx6dl()) { |
975 | clk_set_parent(clk: hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, |
976 | parent: hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); |
977 | clk_set_parent(clk: hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, |
978 | parent: hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); |
979 | } else if (clk_on_imx6q()) { |
980 | clk_set_parent(clk: hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, |
981 | parent: hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk); |
982 | clk_set_parent(clk: hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk, |
983 | parent: hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); |
984 | clk_set_parent(clk: hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, |
985 | parent: hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); |
986 | } |
987 | |
988 | clk_set_parent(clk: hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, parent: hws[IMX6QDL_CLK_ENET_REF]->clk); |
989 | |
990 | imx_register_uart_clocks(); |
991 | } |
992 | CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm" , imx6q_clocks_init); |
993 | |