1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 */
5
6#include <dt-bindings/clock/imx6sx-clock.h>
7#include <linux/bits.h>
8#include <linux/clk.h>
9#include <linux/clkdev.h>
10#include <linux/clk-provider.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/types.h>
18
19#include "clk.h"
20
21static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
22static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
23static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
24static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
25static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
26static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
27static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
28static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
29static const char *ocram_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
30static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
31static const char *gpu_axi_sels[] = { "pll2_pfd2_396m", "pll3_pfd0_720m", "pll3_pfd1_540m", "pll2_bus", };
32static const char *gpu_core_sels[] = { "pll3_pfd1_540m", "pll3_pfd0_720m", "pll2_bus", "pll2_pfd2_396m", };
33static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
34static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
35static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
36static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
37static const char *pcie_axi_sels[] = { "axi", "ahb", };
38static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
39static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
40static const char *perclk_sels[] = { "ipg", "osc", };
41static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
42static const char *vid_sels[] = { "pll3_pfd1_540m", "pll3_usb_otg", "pll3_pfd3_454m", "pll4_audio_div", "pll5_video_div", };
43static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
44static const char *uart_sels[] = { "pll3_80m", "osc", };
45static const char *qspi2_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
46static const char *enet_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
47static const char *enet_sels[] = { "enet_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
48static const char *m4_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "osc", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd3_454m", };
49static const char *m4_sels[] = { "m4_pre_sel", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
50static const char *eim_slow_sels[] = { "ocram", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
51static const char *ecspi_sels[] = { "pll3_60m", "osc", };
52static const char *lcdif1_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
53static const char *lcdif1_sels[] = { "lcdif1_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
54static const char *lcdif2_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd3_594m", "pll3_pfd1_540m", };
55static const char *lcdif2_sels[] = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
56static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
57static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
58static const char *cko1_sels[] = {
59 "dummy", "dummy", "dummy", "dummy",
60 "vadc", "ocram", "qspi2", "m4", "enet_ahb", "lcdif2_pix",
61 "lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
62};
63static const char *cko2_sels[] = {
64 "dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
65 "ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
66 "display_axi", "dummy", "osc", "dummy", "dummy",
67 "usdhc2", "ssi1", "ssi2", "ssi3", "gpu_axi_podf", "dummy",
68 "can_podf", "lvds1_out", "qspi1", "esai_extal", "eim_slow",
69 "uart_serial", "spdif", "audio", "dummy",
70};
71static const char *cko_sels[] = { "cko1", "cko2", };
72static const char *lvds_sels[] = {
73 "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
74 "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
75};
76static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
77static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
78static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
79static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
80static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
81static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
82static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
83static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
84
85static struct clk_hw **hws;
86static struct clk_hw_onecell_data *clk_hw_data;
87
88static const struct clk_div_table clk_enet_ref_table[] = {
89 { .val = 0, .div = 20, },
90 { .val = 1, .div = 10, },
91 { .val = 2, .div = 5, },
92 { .val = 3, .div = 4, },
93 { }
94};
95
96static const struct clk_div_table post_div_table[] = {
97 { .val = 2, .div = 1, },
98 { .val = 1, .div = 2, },
99 { .val = 0, .div = 4, },
100 { }
101};
102
103static const struct clk_div_table video_div_table[] = {
104 { .val = 0, .div = 1, },
105 { .val = 1, .div = 2, },
106 { .val = 2, .div = 1, },
107 { .val = 3, .div = 4, },
108 { }
109};
110
111static u32 share_count_asrc;
112static u32 share_count_audio;
113static u32 share_count_esai;
114static u32 share_count_ssi1;
115static u32 share_count_ssi2;
116static u32 share_count_ssi3;
117static u32 share_count_sai1;
118static u32 share_count_sai2;
119
120static void __init imx6sx_clocks_init(struct device_node *ccm_node)
121{
122 struct device_node *np;
123 void __iomem *base;
124 bool lcdif1_assigned_clk;
125
126 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
127 IMX6SX_CLK_CLK_END), GFP_KERNEL);
128 if (WARN_ON(!clk_hw_data))
129 return;
130
131 clk_hw_data->num = IMX6SX_CLK_CLK_END;
132 hws = clk_hw_data->hws;
133
134 hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed(name: "dummy", rate: 0);
135
136 hws[IMX6SX_CLK_CKIL] = imx_get_clk_hw_by_name(np: ccm_node, name: "ckil");
137 hws[IMX6SX_CLK_OSC] = imx_get_clk_hw_by_name(np: ccm_node, name: "osc");
138
139 /* ipp_di clock is external input */
140 hws[IMX6SX_CLK_IPP_DI0] = imx_get_clk_hw_by_name(np: ccm_node, name: "ipp_di0");
141 hws[IMX6SX_CLK_IPP_DI1] = imx_get_clk_hw_by_name(np: ccm_node, name: "ipp_di1");
142
143 /* Clock source from external clock via CLK1/2 PAD */
144 hws[IMX6SX_CLK_ANACLK1] = imx_get_clk_hw_by_name(np: ccm_node, name: "anaclk1");
145 hws[IMX6SX_CLK_ANACLK2] = imx_get_clk_hw_by_name(np: ccm_node, name: "anaclk2");
146
147 np = of_find_compatible_node(NULL, NULL, compat: "fsl,imx6sx-anatop");
148 base = of_iomap(node: np, index: 0);
149 WARN_ON(!base);
150 of_node_put(node: np);
151
152 hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
153 hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
154 hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
155 hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
156 hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
157 hws[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
158 hws[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
159
160 /* type name parent_name base div_mask */
161 hws[IMX6SX_CLK_PLL1] = imx_clk_hw_pllv3(type: IMX_PLLV3_SYS, name: "pll1", parent_name: "osc", base: base + 0x00, div_mask: 0x7f);
162 hws[IMX6SX_CLK_PLL2] = imx_clk_hw_pllv3(type: IMX_PLLV3_GENERIC, name: "pll2", parent_name: "osc", base: base + 0x30, div_mask: 0x1);
163 hws[IMX6SX_CLK_PLL3] = imx_clk_hw_pllv3(type: IMX_PLLV3_USB, name: "pll3", parent_name: "osc", base: base + 0x10, div_mask: 0x3);
164 hws[IMX6SX_CLK_PLL4] = imx_clk_hw_pllv3(type: IMX_PLLV3_AV, name: "pll4", parent_name: "osc", base: base + 0x70, div_mask: 0x7f);
165 hws[IMX6SX_CLK_PLL5] = imx_clk_hw_pllv3(type: IMX_PLLV3_AV, name: "pll5", parent_name: "osc", base: base + 0xa0, div_mask: 0x7f);
166 hws[IMX6SX_CLK_PLL6] = imx_clk_hw_pllv3(type: IMX_PLLV3_ENET, name: "pll6", parent_name: "osc", base: base + 0xe0, div_mask: 0x3);
167 hws[IMX6SX_CLK_PLL7] = imx_clk_hw_pllv3(type: IMX_PLLV3_USB, name: "pll7", parent_name: "osc", base: base + 0x20, div_mask: 0x3);
168
169 hws[IMX6SX_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
170 hws[IMX6SX_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
171 hws[IMX6SX_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
172 hws[IMX6SX_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
173 hws[IMX6SX_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
174 hws[IMX6SX_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
175 hws[IMX6SX_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
176
177 /* Do not bypass PLLs initially */
178 clk_set_parent(clk: hws[IMX6SX_PLL1_BYPASS]->clk, parent: hws[IMX6SX_CLK_PLL1]->clk);
179 clk_set_parent(clk: hws[IMX6SX_PLL2_BYPASS]->clk, parent: hws[IMX6SX_CLK_PLL2]->clk);
180 clk_set_parent(clk: hws[IMX6SX_PLL3_BYPASS]->clk, parent: hws[IMX6SX_CLK_PLL3]->clk);
181 clk_set_parent(clk: hws[IMX6SX_PLL4_BYPASS]->clk, parent: hws[IMX6SX_CLK_PLL4]->clk);
182 clk_set_parent(clk: hws[IMX6SX_PLL5_BYPASS]->clk, parent: hws[IMX6SX_CLK_PLL5]->clk);
183 clk_set_parent(clk: hws[IMX6SX_PLL6_BYPASS]->clk, parent: hws[IMX6SX_CLK_PLL6]->clk);
184 clk_set_parent(clk: hws[IMX6SX_PLL7_BYPASS]->clk, parent: hws[IMX6SX_CLK_PLL7]->clk);
185
186 hws[IMX6SX_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
187 hws[IMX6SX_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
188 hws[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
189 hws[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
190 hws[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
191 hws[IMX6SX_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
192 hws[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
193
194 /*
195 * Bit 20 is the reserved and read-only bit, we do this only for:
196 * - Do nothing for usbphy clk_enable/disable
197 * - Keep refcount when do usbphy clk_enable/disable, in that case,
198 * the clk framework may need to enable/disable usbphy's parent
199 */
200 hws[IMX6SX_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
201 hws[IMX6SX_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
202
203 /*
204 * usbphy*_gate needs to be on after system boots up, and software
205 * never needs to control it anymore.
206 */
207 hws[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6);
208 hws[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6);
209
210 /* FIXME 100MHz is used for pcie ref for all imx6 pcie, excepted imx6q */
211 hws[IMX6SX_CLK_PCIE_REF] = imx_clk_hw_fixed_factor(name: "pcie_ref", parent: "pll6_enet", mult: 1, div: 5);
212 hws[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
213
214 hws[IMX6SX_CLK_LVDS1_OUT] = imx_clk_hw_gate_exclusive(name: "lvds1_out", parent: "lvds1_sel", reg: base + 0x160, shift: 10, BIT(12));
215 hws[IMX6SX_CLK_LVDS2_OUT] = imx_clk_hw_gate_exclusive(name: "lvds2_out", parent: "lvds2_sel", reg: base + 0x160, shift: 11, BIT(13));
216 hws[IMX6SX_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive(name: "lvds1_in", parent: "anaclk1", reg: base + 0x160, shift: 12, BIT(10));
217 hws[IMX6SX_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive(name: "lvds2_in", parent: "anaclk2", reg: base + 0x160, shift: 13, BIT(11));
218
219 hws[IMX6SX_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
220 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
221 &imx_ccm_lock);
222 hws[IMX6SX_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
223 base + 0xe0, 2, 2, 0, clk_enet_ref_table,
224 &imx_ccm_lock);
225 hws[IMX6SX_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20);
226
227 hws[IMX6SX_CLK_ENET_PTP_REF] = imx_clk_hw_fixed_factor(name: "enet_ptp_ref", parent: "pll6_enet", mult: 1, div: 20);
228 hws[IMX6SX_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp_25m", "enet_ptp_ref", base + 0xe0, 21);
229
230 /* name parent_name reg idx */
231 hws[IMX6SX_CLK_PLL2_PFD0] = imx_clk_hw_pfd(name: "pll2_pfd0_352m", parent_name: "pll2_bus", reg: base + 0x100, idx: 0);
232 hws[IMX6SX_CLK_PLL2_PFD1] = imx_clk_hw_pfd(name: "pll2_pfd1_594m", parent_name: "pll2_bus", reg: base + 0x100, idx: 1);
233 hws[IMX6SX_CLK_PLL2_PFD2] = imx_clk_hw_pfd(name: "pll2_pfd2_396m", parent_name: "pll2_bus", reg: base + 0x100, idx: 2);
234 hws[IMX6SX_CLK_PLL2_PFD3] = imx_clk_hw_pfd(name: "pll2_pfd3_594m", parent_name: "pll2_bus", reg: base + 0x100, idx: 3);
235 hws[IMX6SX_CLK_PLL3_PFD0] = imx_clk_hw_pfd(name: "pll3_pfd0_720m", parent_name: "pll3_usb_otg", reg: base + 0xf0, idx: 0);
236 hws[IMX6SX_CLK_PLL3_PFD1] = imx_clk_hw_pfd(name: "pll3_pfd1_540m", parent_name: "pll3_usb_otg", reg: base + 0xf0, idx: 1);
237 hws[IMX6SX_CLK_PLL3_PFD2] = imx_clk_hw_pfd(name: "pll3_pfd2_508m", parent_name: "pll3_usb_otg", reg: base + 0xf0, idx: 2);
238 hws[IMX6SX_CLK_PLL3_PFD3] = imx_clk_hw_pfd(name: "pll3_pfd3_454m", parent_name: "pll3_usb_otg", reg: base + 0xf0, idx: 3);
239
240 /* name parent_name mult div */
241 hws[IMX6SX_CLK_PLL2_198M] = imx_clk_hw_fixed_factor(name: "pll2_198m", parent: "pll2_pfd2_396m", mult: 1, div: 2);
242 hws[IMX6SX_CLK_PLL3_120M] = imx_clk_hw_fixed_factor(name: "pll3_120m", parent: "pll3_usb_otg", mult: 1, div: 4);
243 hws[IMX6SX_CLK_PLL3_80M] = imx_clk_hw_fixed_factor(name: "pll3_80m", parent: "pll3_usb_otg", mult: 1, div: 6);
244 hws[IMX6SX_CLK_PLL3_60M] = imx_clk_hw_fixed_factor(name: "pll3_60m", parent: "pll3_usb_otg", mult: 1, div: 8);
245 hws[IMX6SX_CLK_TWD] = imx_clk_hw_fixed_factor(name: "twd", parent: "arm", mult: 1, div: 2);
246 hws[IMX6SX_CLK_GPT_3M] = imx_clk_hw_fixed_factor(name: "gpt_3m", parent: "osc", mult: 1, div: 8);
247
248 hws[IMX6SX_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
249 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
250 hws[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
251 CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
252 hws[IMX6SX_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video",
253 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
254 hws[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
255 CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
256
257 /* name reg shift width parent_names num_parents */
258 hws[IMX6SX_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
259 hws[IMX6SX_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
260
261 np = ccm_node;
262 base = of_iomap(node: np, index: 0);
263 WARN_ON(!base);
264
265 /* name reg shift width parent_names num_parents */
266 hws[IMX6SX_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
267 hws[IMX6SX_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
268 hws[IMX6SX_CLK_OCRAM_SEL] = imx_clk_hw_mux("ocram_sel", base + 0x14, 6, 2, ocram_sels, ARRAY_SIZE(ocram_sels));
269 hws[IMX6SX_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
270 hws[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
271 hws[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
272 hws[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
273 hws[IMX6SX_CLK_PCIE_AXI_SEL] = imx_clk_hw_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
274 hws[IMX6SX_CLK_GPU_AXI_SEL] = imx_clk_hw_mux("gpu_axi_sel", base + 0x18, 8, 2, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
275 hws[IMX6SX_CLK_GPU_CORE_SEL] = imx_clk_hw_mux("gpu_core_sel", base + 0x18, 4, 2, gpu_core_sels, ARRAY_SIZE(gpu_core_sels));
276 hws[IMX6SX_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
277 hws[IMX6SX_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
278 hws[IMX6SX_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
279 hws[IMX6SX_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
280 hws[IMX6SX_CLK_USDHC4_SEL] = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
281 hws[IMX6SX_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
282 hws[IMX6SX_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
283 hws[IMX6SX_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
284 hws[IMX6SX_CLK_QSPI1_SEL] = imx_clk_hw_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
285 hws[IMX6SX_CLK_PERCLK_SEL] = imx_clk_hw_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
286 hws[IMX6SX_CLK_VID_SEL] = imx_clk_hw_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels));
287 hws[IMX6SX_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
288 hws[IMX6SX_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
289 hws[IMX6SX_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
290 hws[IMX6SX_CLK_QSPI2_SEL] = imx_clk_hw_mux("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels));
291 hws[IMX6SX_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
292 hws[IMX6SX_CLK_AUDIO_SEL] = imx_clk_hw_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
293 hws[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_hw_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels));
294 hws[IMX6SX_CLK_ENET_SEL] = imx_clk_hw_mux("enet_sel", base + 0x34, 9, 3, enet_sels, ARRAY_SIZE(enet_sels));
295 hws[IMX6SX_CLK_M4_PRE_SEL] = imx_clk_hw_mux("m4_pre_sel", base + 0x34, 6, 3, m4_pre_sels, ARRAY_SIZE(m4_pre_sels));
296 hws[IMX6SX_CLK_M4_SEL] = imx_clk_hw_mux("m4_sel", base + 0x34, 0, 3, m4_sels, ARRAY_SIZE(m4_sels));
297 hws[IMX6SX_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
298 hws[IMX6SX_CLK_LCDIF2_PRE_SEL] = imx_clk_hw_mux("lcdif2_pre_sel", base + 0x38, 6, 3, lcdif2_pre_sels, ARRAY_SIZE(lcdif2_pre_sels));
299 hws[IMX6SX_CLK_LCDIF2_SEL] = imx_clk_hw_mux("lcdif2_sel", base + 0x38, 0, 3, lcdif2_sels, ARRAY_SIZE(lcdif2_sels));
300 hws[IMX6SX_CLK_DISPLAY_SEL] = imx_clk_hw_mux("display_sel", base + 0x3c, 14, 2, display_sels, ARRAY_SIZE(display_sels));
301 hws[IMX6SX_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
302 hws[IMX6SX_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
303 hws[IMX6SX_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
304 hws[IMX6SX_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
305
306 hws[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
307 hws[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
308 hws[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_hw_mux("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels));
309 hws[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_hw_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
310 hws[IMX6SX_CLK_LCDIF1_PRE_SEL] = imx_clk_hw_mux_flags("lcdif1_pre_sel", base + 0x38, 15, 3, lcdif1_pre_sels, ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT);
311 hws[IMX6SX_CLK_LCDIF1_SEL] = imx_clk_hw_mux_flags("lcdif1_sel", base + 0x38, 9, 3, lcdif1_sels, ARRAY_SIZE(lcdif1_sels), CLK_SET_RATE_PARENT);
312
313 /* name parent_name reg shift width */
314 hws[IMX6SX_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
315 hws[IMX6SX_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
316 hws[IMX6SX_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2);
317 hws[IMX6SX_CLK_GPU_CORE_PODF] = imx_clk_hw_divider("gpu_core_podf", "gpu_core_sel", base + 0x18, 29, 3);
318 hws[IMX6SX_CLK_GPU_AXI_PODF] = imx_clk_hw_divider("gpu_axi_podf", "gpu_axi_sel", base + 0x18, 26, 3);
319 hws[IMX6SX_CLK_LCDIF1_PODF] = imx_clk_hw_divider("lcdif1_podf", "lcdif1_pred", base + 0x18, 23, 3);
320 hws[IMX6SX_CLK_QSPI1_PODF] = imx_clk_hw_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3);
321 hws[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
322 hws[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_hw_divider("lcdif2_podf", "lcdif2_pred", base + 0x1c, 20, 3);
323 hws[IMX6SX_CLK_PERCLK] = imx_clk_hw_divider_flags("perclk", "perclk_sel", base + 0x1c, 0, 6, CLK_IS_CRITICAL);
324 hws[IMX6SX_CLK_VID_PODF] = imx_clk_hw_divider("vid_podf", "vid_sel", base + 0x20, 24, 2);
325 hws[IMX6SX_CLK_CAN_PODF] = imx_clk_hw_divider("can_podf", "can_sel", base + 0x20, 2, 6);
326 hws[IMX6SX_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
327 hws[IMX6SX_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
328 hws[IMX6SX_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
329 hws[IMX6SX_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
330 hws[IMX6SX_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
331 hws[IMX6SX_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
332 hws[IMX6SX_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
333 hws[IMX6SX_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
334 hws[IMX6SX_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
335 hws[IMX6SX_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
336 hws[IMX6SX_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
337 hws[IMX6SX_CLK_QSPI2_PRED] = imx_clk_hw_divider("qspi2_pred", "qspi2_sel", base + 0x2c, 18, 3);
338 hws[IMX6SX_CLK_QSPI2_PODF] = imx_clk_hw_divider("qspi2_podf", "qspi2_pred", base + 0x2c, 21, 6);
339 hws[IMX6SX_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
340 hws[IMX6SX_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
341 hws[IMX6SX_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
342 hws[IMX6SX_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
343 hws[IMX6SX_CLK_AUDIO_PRED] = imx_clk_hw_divider("audio_pred", "audio_sel", base + 0x30, 12, 3);
344 hws[IMX6SX_CLK_AUDIO_PODF] = imx_clk_hw_divider("audio_podf", "audio_pred", base + 0x30, 9, 3);
345 hws[IMX6SX_CLK_ENET_PODF] = imx_clk_hw_divider("enet_podf", "enet_pre_sel", base + 0x34, 12, 3);
346 hws[IMX6SX_CLK_M4_PODF] = imx_clk_hw_divider("m4_podf", "m4_sel", base + 0x34, 3, 3);
347 hws[IMX6SX_CLK_ECSPI_PODF] = imx_clk_hw_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
348 hws[IMX6SX_CLK_LCDIF1_PRED] = imx_clk_hw_divider("lcdif1_pred", "lcdif1_pre_sel", base + 0x38, 12, 3);
349 hws[IMX6SX_CLK_LCDIF2_PRED] = imx_clk_hw_divider("lcdif2_pred", "lcdif2_pre_sel", base + 0x38, 3, 3);
350 hws[IMX6SX_CLK_DISPLAY_PODF] = imx_clk_hw_divider("display_podf", "display_sel", base + 0x3c, 16, 3);
351 hws[IMX6SX_CLK_CSI_PODF] = imx_clk_hw_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
352 hws[IMX6SX_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
353 hws[IMX6SX_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
354
355 hws[IMX6SX_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor(name: "ldb_di0_div_3_5", parent: "ldb_di0_sel", mult: 2, div: 7);
356 hws[IMX6SX_CLK_LDB_DI0_DIV_7] = imx_clk_hw_fixed_factor(name: "ldb_di0_div_7", parent: "ldb_di0_sel", mult: 1, div: 7);
357 hws[IMX6SX_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor(name: "ldb_di1_div_3_5", parent: "ldb_di1_sel", mult: 2, div: 7);
358 hws[IMX6SX_CLK_LDB_DI1_DIV_7] = imx_clk_hw_fixed_factor(name: "ldb_di1_div_7", parent: "ldb_di1_sel", mult: 1, div: 7);
359
360 /* name reg shift width busy: reg, shift parent_names num_parents */
361 hws[IMX6SX_CLK_PERIPH] = imx_clk_hw_busy_mux(name: "periph", reg: base + 0x14, shift: 25, width: 1, busy_reg: base + 0x48, busy_shift: 5, parent_names: periph_sels, ARRAY_SIZE(periph_sels));
362 hws[IMX6SX_CLK_PERIPH2] = imx_clk_hw_busy_mux(name: "periph2", reg: base + 0x14, shift: 26, width: 1, busy_reg: base + 0x48, busy_shift: 3, parent_names: periph2_sels, ARRAY_SIZE(periph2_sels));
363 /* name parent_name reg shift width busy: reg, shift */
364 hws[IMX6SX_CLK_OCRAM_PODF] = imx_clk_hw_busy_divider(name: "ocram_podf", parent_name: "ocram_sel", reg: base + 0x14, shift: 16, width: 3, busy_reg: base + 0x48, busy_shift: 0);
365 hws[IMX6SX_CLK_AHB] = imx_clk_hw_busy_divider(name: "ahb", parent_name: "periph", reg: base + 0x14, shift: 10, width: 3, busy_reg: base + 0x48, busy_shift: 1);
366 hws[IMX6SX_CLK_MMDC_PODF] = imx_clk_hw_busy_divider(name: "mmdc_podf", parent_name: "periph2", reg: base + 0x14, shift: 3, width: 3, busy_reg: base + 0x48, busy_shift: 2);
367 hws[IMX6SX_CLK_ARM] = imx_clk_hw_busy_divider(name: "arm", parent_name: "pll1_sw", reg: base + 0x10, shift: 0, width: 3, busy_reg: base + 0x48, busy_shift: 16);
368
369 /* name parent_name reg shift */
370 /* CCGR0 */
371 hws[IMX6SX_CLK_AIPS_TZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);
372 hws[IMX6SX_CLK_AIPS_TZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);
373 hws[IMX6SX_CLK_APBH_DMA] = imx_clk_hw_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
374 hws[IMX6SX_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
375 hws[IMX6SX_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
376 hws[IMX6SX_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8);
377 hws[IMX6SX_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10);
378 hws[IMX6SX_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12);
379 hws[IMX6SX_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14);
380 hws[IMX6SX_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial", "can_podf", base + 0x68, 16);
381 hws[IMX6SX_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18);
382 hws[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial", "can_podf", base + 0x68, 20);
383 hws[IMX6SX_CLK_DCIC1] = imx_clk_hw_gate2("dcic1", "display_podf", base + 0x68, 24);
384 hws[IMX6SX_CLK_DCIC2] = imx_clk_hw_gate2("dcic2", "display_podf", base + 0x68, 26);
385 hws[IMX6SX_CLK_AIPS_TZ3] = imx_clk_hw_gate2_flags("aips_tz3", "ahb", base + 0x68, 30, CLK_IS_CRITICAL);
386
387 /* CCGR1 */
388 hws[IMX6SX_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
389 hws[IMX6SX_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
390 hws[IMX6SX_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
391 hws[IMX6SX_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
392 hws[IMX6SX_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5", "ecspi_podf", base + 0x6c, 8);
393 hws[IMX6SX_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "perclk", base + 0x6c, 12);
394 hws[IMX6SX_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "perclk", base + 0x6c, 14);
395 hws[IMX6SX_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
396 hws[IMX6SX_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
397 hws[IMX6SX_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
398 hws[IMX6SX_CLK_WAKEUP] = imx_clk_hw_gate2_flags("wakeup", "ipg", base + 0x6c, 18, CLK_IS_CRITICAL);
399 hws[IMX6SX_CLK_GPT_BUS] = imx_clk_hw_gate2("gpt_bus", "perclk", base + 0x6c, 20);
400 hws[IMX6SX_CLK_GPT_SERIAL] = imx_clk_hw_gate2("gpt_serial", "perclk", base + 0x6c, 22);
401 hws[IMX6SX_CLK_GPU] = imx_clk_hw_gate2("gpu", "gpu_core_podf", base + 0x6c, 26);
402 hws[IMX6SX_CLK_OCRAM_S] = imx_clk_hw_gate2("ocram_s", "ahb", base + 0x6c, 28);
403 hws[IMX6SX_CLK_CANFD] = imx_clk_hw_gate2("canfd", "can_podf", base + 0x6c, 30);
404
405 /* CCGR2 */
406 hws[IMX6SX_CLK_CSI] = imx_clk_hw_gate2("csi", "csi_podf", base + 0x70, 2);
407 hws[IMX6SX_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6);
408 hws[IMX6SX_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8);
409 hws[IMX6SX_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10);
410 hws[IMX6SX_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, 12);
411 hws[IMX6SX_CLK_IOMUXC] = imx_clk_hw_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14);
412 hws[IMX6SX_CLK_IPMUX1] = imx_clk_hw_gate2_flags("ipmux1", "ahb", base + 0x70, 16, CLK_IS_CRITICAL);
413 hws[IMX6SX_CLK_IPMUX2] = imx_clk_hw_gate2_flags("ipmux2", "ahb", base + 0x70, 18, CLK_IS_CRITICAL);
414 hws[IMX6SX_CLK_IPMUX3] = imx_clk_hw_gate2_flags("ipmux3", "ahb", base + 0x70, 20, CLK_IS_CRITICAL);
415 hws[IMX6SX_CLK_TZASC1] = imx_clk_hw_gate2_flags("tzasc1", "mmdc_podf", base + 0x70, 22, CLK_IS_CRITICAL);
416 hws[IMX6SX_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif_apb", "display_podf", base + 0x70, 28);
417 hws[IMX6SX_CLK_PXP_AXI] = imx_clk_hw_gate2("pxp_axi", "display_podf", base + 0x70, 30);
418
419 /* CCGR3 */
420 hws[IMX6SX_CLK_M4] = imx_clk_hw_gate2("m4", "m4_podf", base + 0x74, 2);
421 hws[IMX6SX_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x74, 4);
422 hws[IMX6SX_CLK_ENET_AHB] = imx_clk_hw_gate2("enet_ahb", "enet_sel", base + 0x74, 4);
423 hws[IMX6SX_CLK_DISPLAY_AXI] = imx_clk_hw_gate2("display_axi", "display_podf", base + 0x74, 6);
424 hws[IMX6SX_CLK_LCDIF2_PIX] = imx_clk_hw_gate2("lcdif2_pix", "lcdif2_sel", base + 0x74, 8);
425 hws[IMX6SX_CLK_LCDIF1_PIX] = imx_clk_hw_gate2("lcdif1_pix", "lcdif1_sel", base + 0x74, 10);
426 hws[IMX6SX_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
427 hws[IMX6SX_CLK_QSPI1] = imx_clk_hw_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
428 hws[IMX6SX_CLK_MLB] = imx_clk_hw_gate2("mlb", "ahb", base + 0x74, 18);
429 hws[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_hw_gate2_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
430 hws[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
431 hws[IMX6SX_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2_flags("mmdc_p1_ipg", "ipg", base + 0x74, 26, CLK_IS_CRITICAL);
432 hws[IMX6SX_CLK_OCRAM] = imx_clk_hw_gate2_flags("ocram", "ocram_podf", base + 0x74, 28, CLK_IS_CRITICAL);
433
434 /* CCGR4 */
435 hws[IMX6SX_CLK_PCIE_AXI] = imx_clk_hw_gate2("pcie_axi", "display_podf", base + 0x78, 0);
436 hws[IMX6SX_CLK_QSPI2] = imx_clk_hw_gate2("qspi2", "qspi2_podf", base + 0x78, 10);
437 hws[IMX6SX_CLK_PER1_BCH] = imx_clk_hw_gate2("per1_bch", "usdhc3", base + 0x78, 12);
438 hws[IMX6SX_CLK_PER2_MAIN] = imx_clk_hw_gate2_flags("per2_main", "ahb", base + 0x78, 14, CLK_IS_CRITICAL);
439 hws[IMX6SX_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "perclk", base + 0x78, 16);
440 hws[IMX6SX_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "perclk", base + 0x78, 18);
441 hws[IMX6SX_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "perclk", base + 0x78, 20);
442 hws[IMX6SX_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "perclk", base + 0x78, 22);
443 hws[IMX6SX_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
444 hws[IMX6SX_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
445 hws[IMX6SX_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io", "qspi2_podf", base + 0x78, 28);
446 hws[IMX6SX_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
447
448 /* CCGR5 */
449 hws[IMX6SX_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
450 hws[IMX6SX_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6);
451 hws[IMX6SX_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12);
452 hws[IMX6SX_CLK_AUDIO] = imx_clk_hw_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
453 hws[IMX6SX_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
454 hws[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
455 hws[IMX6SX_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
456 hws[IMX6SX_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
457 hws[IMX6SX_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
458 hws[IMX6SX_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
459 hws[IMX6SX_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
460 hws[IMX6SX_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
461 hws[IMX6SX_CLK_UART_IPG] = imx_clk_hw_gate2("uart_ipg", "ipg", base + 0x7c, 24);
462 hws[IMX6SX_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
463 hws[IMX6SX_CLK_SAI1_IPG] = imx_clk_hw_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1);
464 hws[IMX6SX_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2);
465 hws[IMX6SX_CLK_SAI1] = imx_clk_hw_gate2_shared("sai1", "ssi1_podf", base + 0x7c, 28, &share_count_sai1);
466 hws[IMX6SX_CLK_SAI2] = imx_clk_hw_gate2_shared("sai2", "ssi2_podf", base + 0x7c, 30, &share_count_sai2);
467
468 /* CCGR6 */
469 hws[IMX6SX_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0);
470 hws[IMX6SX_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
471 hws[IMX6SX_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
472 hws[IMX6SX_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
473 hws[IMX6SX_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
474 hws[IMX6SX_CLK_EIM_SLOW] = imx_clk_hw_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
475 hws[IMX6SX_CLK_PWM8] = imx_clk_hw_gate2("pwm8", "perclk", base + 0x80, 16);
476 hws[IMX6SX_CLK_VADC] = imx_clk_hw_gate2("vadc", "vid_podf", base + 0x80, 20);
477 hws[IMX6SX_CLK_GIS] = imx_clk_hw_gate2("gis", "display_podf", base + 0x80, 22);
478 hws[IMX6SX_CLK_I2C4] = imx_clk_hw_gate2("i2c4", "perclk", base + 0x80, 24);
479 hws[IMX6SX_CLK_PWM5] = imx_clk_hw_gate2("pwm5", "perclk", base + 0x80, 26);
480 hws[IMX6SX_CLK_PWM6] = imx_clk_hw_gate2("pwm6", "perclk", base + 0x80, 28);
481 hws[IMX6SX_CLK_PWM7] = imx_clk_hw_gate2("pwm7", "perclk", base + 0x80, 30);
482
483 hws[IMX6SX_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7);
484 hws[IMX6SX_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24);
485
486 /* mask handshake of mmdc */
487 imx_mmdc_mask_handshake(ccm_base: base, chn: 0);
488
489 imx_check_clk_hws(clks: hws, IMX6SX_CLK_CLK_END);
490
491 of_clk_add_hw_provider(np, get: of_clk_hw_onecell_get, data: clk_hw_data);
492
493 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
494 clk_prepare_enable(clk: hws[IMX6SX_CLK_USBPHY1_GATE]->clk);
495 clk_prepare_enable(clk: hws[IMX6SX_CLK_USBPHY2_GATE]->clk);
496 }
497
498 /* Set the default 132MHz for EIM module */
499 clk_set_parent(clk: hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, parent: hws[IMX6SX_CLK_PLL2_PFD2]->clk);
500 clk_set_rate(clk: hws[IMX6SX_CLK_EIM_SLOW]->clk, rate: 132000000);
501
502 np = of_find_node_by_path(path: "/soc/bus@2200000/spba-bus@2240000/lcdif@2220000");
503 lcdif1_assigned_clk = of_find_property(np, name: "assigned-clock-parents", NULL);
504
505 /* Set parent clock for LCDIF1 pixel clock if not done via devicetree */
506 if (!lcdif1_assigned_clk) {
507 clk_set_parent(clk: hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk,
508 parent: hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk);
509 clk_set_parent(clk: hws[IMX6SX_CLK_LCDIF1_SEL]->clk,
510 parent: hws[IMX6SX_CLK_LCDIF1_PODF]->clk);
511 }
512
513 /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
514 if (clk_set_parent(clk: hws[IMX6SX_CLK_LVDS1_SEL]->clk, parent: hws[IMX6SX_CLK_PCIE_REF_125M]->clk))
515 pr_err("Failed to set pcie bus parent clk.\n");
516
517 /*
518 * Init enet system AHB clock, set to 200MHz
519 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
520 */
521 clk_set_parent(clk: hws[IMX6SX_CLK_ENET_PRE_SEL]->clk, parent: hws[IMX6SX_CLK_PLL2_PFD2]->clk);
522 clk_set_parent(clk: hws[IMX6SX_CLK_ENET_SEL]->clk, parent: hws[IMX6SX_CLK_ENET_PODF]->clk);
523 clk_set_rate(clk: hws[IMX6SX_CLK_ENET_PODF]->clk, rate: 200000000);
524 clk_set_rate(clk: hws[IMX6SX_CLK_ENET_REF]->clk, rate: 125000000);
525 clk_set_rate(clk: hws[IMX6SX_CLK_ENET2_REF]->clk, rate: 125000000);
526
527 /* Audio clocks */
528 clk_set_rate(clk: hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, rate: 393216000);
529
530 clk_set_parent(clk: hws[IMX6SX_CLK_SPDIF_SEL]->clk, parent: hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
531 clk_set_rate(clk: hws[IMX6SX_CLK_SPDIF_PODF]->clk, rate: 98304000);
532
533 clk_set_parent(clk: hws[IMX6SX_CLK_AUDIO_SEL]->clk, parent: hws[IMX6SX_CLK_PLL3_USB_OTG]->clk);
534 clk_set_rate(clk: hws[IMX6SX_CLK_AUDIO_PODF]->clk, rate: 24000000);
535
536 clk_set_parent(clk: hws[IMX6SX_CLK_SSI1_SEL]->clk, parent: hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
537 clk_set_parent(clk: hws[IMX6SX_CLK_SSI2_SEL]->clk, parent: hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
538 clk_set_parent(clk: hws[IMX6SX_CLK_SSI3_SEL]->clk, parent: hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
539 clk_set_rate(clk: hws[IMX6SX_CLK_SSI1_PODF]->clk, rate: 24576000);
540 clk_set_rate(clk: hws[IMX6SX_CLK_SSI2_PODF]->clk, rate: 24576000);
541 clk_set_rate(clk: hws[IMX6SX_CLK_SSI3_PODF]->clk, rate: 24576000);
542
543 clk_set_parent(clk: hws[IMX6SX_CLK_ESAI_SEL]->clk, parent: hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);
544 clk_set_rate(clk: hws[IMX6SX_CLK_ESAI_PODF]->clk, rate: 24576000);
545
546 /* Set parent clock for vadc */
547 clk_set_parent(clk: hws[IMX6SX_CLK_VID_SEL]->clk, parent: hws[IMX6SX_CLK_PLL3_USB_OTG]->clk);
548
549 /* default parent of can_sel clock is invalid, manually set it here */
550 clk_set_parent(clk: hws[IMX6SX_CLK_CAN_SEL]->clk, parent: hws[IMX6SX_CLK_PLL3_60M]->clk);
551
552 /* Update gpu clock from default 528M to 720M */
553 clk_set_parent(clk: hws[IMX6SX_CLK_GPU_CORE_SEL]->clk, parent: hws[IMX6SX_CLK_PLL3_PFD0]->clk);
554 clk_set_parent(clk: hws[IMX6SX_CLK_GPU_AXI_SEL]->clk, parent: hws[IMX6SX_CLK_PLL3_PFD0]->clk);
555
556 clk_set_parent(clk: hws[IMX6SX_CLK_QSPI1_SEL]->clk, parent: hws[IMX6SX_CLK_PLL2_BUS]->clk);
557 clk_set_parent(clk: hws[IMX6SX_CLK_QSPI2_SEL]->clk, parent: hws[IMX6SX_CLK_PLL2_BUS]->clk);
558
559 imx_register_uart_clocks();
560}
561CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
562

source code of linux/drivers/clk/imx/clk-imx6sx.c