1 | // SPDX-License-Identifier: GPL-2.0 |
2 | #include <linux/bits.h> |
3 | #include <linux/clk-provider.h> |
4 | #include <linux/io.h> |
5 | #include <linux/slab.h> |
6 | #include <linux/kernel.h> |
7 | #include <linux/err.h> |
8 | |
9 | #include "clk.h" |
10 | |
11 | #define MFN_BITS (10) |
12 | #define MFN_SIGN (BIT(MFN_BITS - 1)) |
13 | #define MFN_MASK (MFN_SIGN - 1) |
14 | |
15 | /** |
16 | * struct clk_pllv1 - IMX PLLv1 clock descriptor |
17 | * |
18 | * @hw: clock source |
19 | * @base: base address of pll registers |
20 | * @type: type of IMX_PLLV1 |
21 | * |
22 | * PLL clock version 1, found on i.MX1/21/25/27/31/35 |
23 | */ |
24 | struct clk_pllv1 { |
25 | struct clk_hw hw; |
26 | void __iomem *base; |
27 | enum imx_pllv1_type type; |
28 | }; |
29 | |
30 | #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk)) |
31 | |
32 | static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) |
33 | { |
34 | return pll->type == IMX_PLLV1_IMX1; |
35 | } |
36 | |
37 | static inline bool is_imx21_pllv1(struct clk_pllv1 *pll) |
38 | { |
39 | return pll->type == IMX_PLLV1_IMX21; |
40 | } |
41 | |
42 | static inline bool is_imx27_pllv1(struct clk_pllv1 *pll) |
43 | { |
44 | return pll->type == IMX_PLLV1_IMX27; |
45 | } |
46 | |
47 | static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn) |
48 | { |
49 | return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN); |
50 | } |
51 | |
52 | static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, |
53 | unsigned long parent_rate) |
54 | { |
55 | struct clk_pllv1 *pll = to_clk_pllv1(hw); |
56 | unsigned long long ull; |
57 | int mfn_abs; |
58 | unsigned int mfi, mfn, mfd, pd; |
59 | u32 reg; |
60 | unsigned long rate; |
61 | |
62 | reg = readl(addr: pll->base); |
63 | |
64 | /* |
65 | * Get the resulting clock rate from a PLL register value and the input |
66 | * frequency. PLLs with this register layout can be found on i.MX1, |
67 | * i.MX21, i.MX27 and i,MX31 |
68 | * |
69 | * mfi + mfn / (mfd + 1) |
70 | * f = 2 * f_ref * -------------------- |
71 | * pd + 1 |
72 | */ |
73 | |
74 | mfi = (reg >> 10) & 0xf; |
75 | mfn = reg & 0x3ff; |
76 | mfd = (reg >> 16) & 0x3ff; |
77 | pd = (reg >> 26) & 0xf; |
78 | |
79 | mfi = mfi <= 5 ? 5 : mfi; |
80 | |
81 | mfn_abs = mfn; |
82 | |
83 | /* |
84 | * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit |
85 | * 2's complements number. |
86 | * On i.MX27 the bit 9 is the sign bit. |
87 | */ |
88 | if (mfn_is_negative(pll, mfn)) { |
89 | if (is_imx27_pllv1(pll)) |
90 | mfn_abs = mfn & MFN_MASK; |
91 | else |
92 | mfn_abs = BIT(MFN_BITS) - mfn; |
93 | } |
94 | |
95 | rate = parent_rate * 2; |
96 | rate /= pd + 1; |
97 | |
98 | ull = (unsigned long long)rate * mfn_abs; |
99 | |
100 | do_div(ull, mfd + 1); |
101 | |
102 | if (mfn_is_negative(pll, mfn)) |
103 | ull = (rate * mfi) - ull; |
104 | else |
105 | ull = (rate * mfi) + ull; |
106 | |
107 | return ull; |
108 | } |
109 | |
110 | static const struct clk_ops clk_pllv1_ops = { |
111 | .recalc_rate = clk_pllv1_recalc_rate, |
112 | }; |
113 | |
114 | struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name, |
115 | const char *parent, void __iomem *base) |
116 | { |
117 | struct clk_pllv1 *pll; |
118 | struct clk_hw *hw; |
119 | struct clk_init_data init; |
120 | int ret; |
121 | |
122 | pll = kmalloc(size: sizeof(*pll), GFP_KERNEL); |
123 | if (!pll) |
124 | return ERR_PTR(error: -ENOMEM); |
125 | |
126 | pll->base = base; |
127 | pll->type = type; |
128 | |
129 | init.name = name; |
130 | init.ops = &clk_pllv1_ops; |
131 | init.flags = 0; |
132 | init.parent_names = &parent; |
133 | init.num_parents = 1; |
134 | |
135 | pll->hw.init = &init; |
136 | hw = &pll->hw; |
137 | |
138 | ret = clk_hw_register(NULL, hw); |
139 | if (ret) { |
140 | kfree(objp: pll); |
141 | return ERR_PTR(error: ret); |
142 | } |
143 | |
144 | return hw; |
145 | } |
146 | |