1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright 2012-2013 Freescale Semiconductor, Inc. |
4 | */ |
5 | |
6 | #include <linux/of_address.h> |
7 | #include <linux/bits.h> |
8 | #include <linux/clk.h> |
9 | #include <linux/syscore_ops.h> |
10 | #include <dt-bindings/clock/vf610-clock.h> |
11 | |
12 | #include "clk.h" |
13 | |
14 | #define CCM_CCR (ccm_base + 0x00) |
15 | #define CCM_CSR (ccm_base + 0x04) |
16 | #define CCM_CCSR (ccm_base + 0x08) |
17 | #define CCM_CACRR (ccm_base + 0x0c) |
18 | #define CCM_CSCMR1 (ccm_base + 0x10) |
19 | #define CCM_CSCDR1 (ccm_base + 0x14) |
20 | #define CCM_CSCDR2 (ccm_base + 0x18) |
21 | #define CCM_CSCDR3 (ccm_base + 0x1c) |
22 | #define CCM_CSCMR2 (ccm_base + 0x20) |
23 | #define CCM_CSCDR4 (ccm_base + 0x24) |
24 | #define CCM_CLPCR (ccm_base + 0x2c) |
25 | #define CCM_CISR (ccm_base + 0x30) |
26 | #define CCM_CIMR (ccm_base + 0x34) |
27 | #define CCM_CGPR (ccm_base + 0x3c) |
28 | #define CCM_CCGR0 (ccm_base + 0x40) |
29 | #define CCM_CCGR1 (ccm_base + 0x44) |
30 | #define CCM_CCGR2 (ccm_base + 0x48) |
31 | #define CCM_CCGR3 (ccm_base + 0x4c) |
32 | #define CCM_CCGR4 (ccm_base + 0x50) |
33 | #define CCM_CCGR5 (ccm_base + 0x54) |
34 | #define CCM_CCGR6 (ccm_base + 0x58) |
35 | #define CCM_CCGR7 (ccm_base + 0x5c) |
36 | #define CCM_CCGR8 (ccm_base + 0x60) |
37 | #define CCM_CCGR9 (ccm_base + 0x64) |
38 | #define CCM_CCGR10 (ccm_base + 0x68) |
39 | #define CCM_CCGR11 (ccm_base + 0x6c) |
40 | #define CCM_CCGRx(x) (CCM_CCGR0 + (x) * 4) |
41 | #define CCM_CMEOR0 (ccm_base + 0x70) |
42 | #define CCM_CMEOR1 (ccm_base + 0x74) |
43 | #define CCM_CMEOR2 (ccm_base + 0x78) |
44 | #define CCM_CMEOR3 (ccm_base + 0x7c) |
45 | #define CCM_CMEOR4 (ccm_base + 0x80) |
46 | #define CCM_CMEOR5 (ccm_base + 0x84) |
47 | #define CCM_CPPDSR (ccm_base + 0x88) |
48 | #define CCM_CCOWR (ccm_base + 0x8c) |
49 | #define CCM_CCPGR0 (ccm_base + 0x90) |
50 | #define CCM_CCPGR1 (ccm_base + 0x94) |
51 | #define CCM_CCPGR2 (ccm_base + 0x98) |
52 | #define CCM_CCPGR3 (ccm_base + 0x9c) |
53 | |
54 | #define CCM_CCGRx_CGn(n) ((n) * 2) |
55 | |
56 | #define PFD_PLL1_BASE (anatop_base + 0x2b0) |
57 | #define PFD_PLL2_BASE (anatop_base + 0x100) |
58 | #define PFD_PLL3_BASE (anatop_base + 0xf0) |
59 | #define PLL1_CTRL (anatop_base + 0x270) |
60 | #define PLL2_CTRL (anatop_base + 0x30) |
61 | #define PLL3_CTRL (anatop_base + 0x10) |
62 | #define PLL4_CTRL (anatop_base + 0x70) |
63 | #define PLL5_CTRL (anatop_base + 0xe0) |
64 | #define PLL6_CTRL (anatop_base + 0xa0) |
65 | #define PLL7_CTRL (anatop_base + 0x20) |
66 | #define ANA_MISC1 (anatop_base + 0x160) |
67 | |
68 | static void __iomem *anatop_base; |
69 | static void __iomem *ccm_base; |
70 | |
71 | /* sources for multiplexer clocks, this is used multiple times */ |
72 | static const char *fast_sels[] = { "firc" , "fxosc" , }; |
73 | static const char *slow_sels[] = { "sirc_32k" , "sxosc" , }; |
74 | static const char *pll1_sels[] = { "pll1_sys" , "pll1_pfd1" , "pll1_pfd2" , "pll1_pfd3" , "pll1_pfd4" , }; |
75 | static const char *pll2_sels[] = { "pll2_bus" , "pll2_pfd1" , "pll2_pfd2" , "pll2_pfd3" , "pll2_pfd4" , }; |
76 | static const char *pll_bypass_src_sels[] = { "fast_clk_sel" , "lvds1_in" , }; |
77 | static const char *pll1_bypass_sels[] = { "pll1" , "pll1_bypass_src" , }; |
78 | static const char *pll2_bypass_sels[] = { "pll2" , "pll2_bypass_src" , }; |
79 | static const char *pll3_bypass_sels[] = { "pll3" , "pll3_bypass_src" , }; |
80 | static const char *pll4_bypass_sels[] = { "pll4" , "pll4_bypass_src" , }; |
81 | static const char *pll5_bypass_sels[] = { "pll5" , "pll5_bypass_src" , }; |
82 | static const char *pll6_bypass_sels[] = { "pll6" , "pll6_bypass_src" , }; |
83 | static const char *pll7_bypass_sels[] = { "pll7" , "pll7_bypass_src" , }; |
84 | static const char *sys_sels[] = { "fast_clk_sel" , "slow_clk_sel" , "pll2_pfd_sel" , "pll2_bus" , "pll1_pfd_sel" , "pll3_usb_otg" , }; |
85 | static const char *ddr_sels[] = { "pll2_pfd2" , "sys_sel" , }; |
86 | static const char *rmii_sels[] = { "enet_ext" , "audio_ext" , "enet_50m" , "enet_25m" , }; |
87 | static const char *enet_ts_sels[] = { "enet_ext" , "fxosc" , "audio_ext" , "usb" , "enet_ts" , "enet_25m" , "enet_50m" , }; |
88 | static const char *esai_sels[] = { "audio_ext" , "mlb" , "spdif_rx" , "pll4_audio_div" , }; |
89 | static const char *sai_sels[] = { "audio_ext" , "mlb" , "spdif_rx" , "pll4_audio_div" , }; |
90 | static const char *nfc_sels[] = { "platform_bus" , "pll1_pfd1" , "pll3_pfd1" , "pll3_pfd3" , }; |
91 | static const char *qspi_sels[] = { "pll3_usb_otg" , "pll3_pfd4" , "pll2_pfd4" , "pll1_pfd4" , }; |
92 | static const char *esdhc_sels[] = { "pll3_usb_otg" , "pll3_pfd3" , "pll1_pfd3" , "platform_bus" , }; |
93 | static const char *dcu_sels[] = { "pll1_pfd2" , "pll3_usb_otg" , }; |
94 | static const char *gpu_sels[] = { "pll2_pfd2" , "pll3_pfd2" , }; |
95 | static const char *vadc_sels[] = { "pll6_video_div" , "pll3_usb_otg_div" , "pll3_usb_otg" , }; |
96 | /* FTM counter clock source, not module clock */ |
97 | static const char *ftm_ext_sels[] = {"sirc_128k" , "sxosc" , "fxosc_half" , "audio_ext" , }; |
98 | static const char *ftm_fix_sels[] = { "sxosc" , "ipg_bus" , }; |
99 | |
100 | |
101 | static const struct clk_div_table pll4_audio_div_table[] = { |
102 | { .val = 0, .div = 1 }, |
103 | { .val = 1, .div = 2 }, |
104 | { .val = 2, .div = 6 }, |
105 | { .val = 3, .div = 8 }, |
106 | { .val = 4, .div = 10 }, |
107 | { .val = 5, .div = 12 }, |
108 | { .val = 6, .div = 14 }, |
109 | { .val = 7, .div = 16 }, |
110 | { } |
111 | }; |
112 | |
113 | static struct clk *clk[VF610_CLK_END]; |
114 | static struct clk_onecell_data clk_data; |
115 | |
116 | static u32 cscmr1; |
117 | static u32 cscmr2; |
118 | static u32 cscdr1; |
119 | static u32 cscdr2; |
120 | static u32 cscdr3; |
121 | static u32 ccgr[12]; |
122 | |
123 | static unsigned int const clks_init_on[] __initconst = { |
124 | VF610_CLK_SYS_BUS, |
125 | VF610_CLK_DDR_SEL, |
126 | VF610_CLK_DAP, |
127 | VF610_CLK_DDRMC, |
128 | VF610_CLK_WKPU, |
129 | }; |
130 | |
131 | static struct clk * __init vf610_get_fixed_clock( |
132 | struct device_node *ccm_node, const char *name) |
133 | { |
134 | struct clk *clk = of_clk_get_by_name(np: ccm_node, name); |
135 | |
136 | /* Backward compatibility if device tree is missing clks assignments */ |
137 | if (IS_ERR(ptr: clk)) |
138 | clk = imx_obtain_fixed_clock(name, rate: 0); |
139 | return clk; |
140 | }; |
141 | |
142 | static int vf610_clk_suspend(void) |
143 | { |
144 | int i; |
145 | |
146 | cscmr1 = readl_relaxed(CCM_CSCMR1); |
147 | cscmr2 = readl_relaxed(CCM_CSCMR2); |
148 | |
149 | cscdr1 = readl_relaxed(CCM_CSCDR1); |
150 | cscdr2 = readl_relaxed(CCM_CSCDR2); |
151 | cscdr3 = readl_relaxed(CCM_CSCDR3); |
152 | |
153 | for (i = 0; i < 12; i++) |
154 | ccgr[i] = readl_relaxed(CCM_CCGRx(i)); |
155 | |
156 | return 0; |
157 | } |
158 | |
159 | static void vf610_clk_resume(void) |
160 | { |
161 | int i; |
162 | |
163 | writel_relaxed(cscmr1, CCM_CSCMR1); |
164 | writel_relaxed(cscmr2, CCM_CSCMR2); |
165 | |
166 | writel_relaxed(cscdr1, CCM_CSCDR1); |
167 | writel_relaxed(cscdr2, CCM_CSCDR2); |
168 | writel_relaxed(cscdr3, CCM_CSCDR3); |
169 | |
170 | for (i = 0; i < 12; i++) |
171 | writel_relaxed(ccgr[i], CCM_CCGRx(i)); |
172 | } |
173 | |
174 | static struct syscore_ops vf610_clk_syscore_ops = { |
175 | .suspend = vf610_clk_suspend, |
176 | .resume = vf610_clk_resume, |
177 | }; |
178 | |
179 | static void __init vf610_clocks_init(struct device_node *ccm_node) |
180 | { |
181 | struct device_node *np; |
182 | int i; |
183 | |
184 | clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy" , 0); |
185 | clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k" , 128000); |
186 | clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k" , 32000); |
187 | clk[VF610_CLK_FIRC] = imx_clk_fixed("firc" , 24000000); |
188 | |
189 | clk[VF610_CLK_SXOSC] = vf610_get_fixed_clock(ccm_node, name: "sxosc" ); |
190 | clk[VF610_CLK_FXOSC] = vf610_get_fixed_clock(ccm_node, name: "fxosc" ); |
191 | clk[VF610_CLK_AUDIO_EXT] = vf610_get_fixed_clock(ccm_node, name: "audio_ext" ); |
192 | clk[VF610_CLK_ENET_EXT] = vf610_get_fixed_clock(ccm_node, name: "enet_ext" ); |
193 | |
194 | /* Clock source from external clock via LVDs PAD */ |
195 | clk[VF610_CLK_ANACLK1] = vf610_get_fixed_clock(ccm_node, name: "anaclk1" ); |
196 | |
197 | clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half" , "fxosc" , 1, 2); |
198 | |
199 | np = of_find_compatible_node(NULL, NULL, compat: "fsl,vf610-anatop" ); |
200 | anatop_base = of_iomap(node: np, index: 0); |
201 | BUG_ON(!anatop_base); |
202 | of_node_put(node: np); |
203 | |
204 | np = ccm_node; |
205 | ccm_base = of_iomap(node: np, index: 0); |
206 | BUG_ON(!ccm_base); |
207 | |
208 | clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel" , CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); |
209 | clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel" , CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); |
210 | |
211 | clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src" , PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
212 | clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src" , PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
213 | clk[VF610_CLK_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src" , PLL3_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
214 | clk[VF610_CLK_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src" , PLL4_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
215 | clk[VF610_CLK_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src" , PLL5_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
216 | clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src" , PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
217 | clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src" , PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
218 | |
219 | clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS_VF610, "pll1" , "pll1_bypass_src" , PLL1_CTRL, 0x1); |
220 | clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_SYS_VF610, "pll2" , "pll2_bypass_src" , PLL2_CTRL, 0x1); |
221 | clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3" , "pll3_bypass_src" , PLL3_CTRL, 0x2); |
222 | clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4" , "pll4_bypass_src" , PLL4_CTRL, 0x7f); |
223 | clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5" , "pll5_bypass_src" , PLL5_CTRL, 0x3); |
224 | clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6" , "pll6_bypass_src" , PLL6_CTRL, 0x7f); |
225 | clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll7" , "pll7_bypass_src" , PLL7_CTRL, 0x2); |
226 | |
227 | clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass" , PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); |
228 | clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass" , PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); |
229 | clk[VF610_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass" , PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); |
230 | clk[VF610_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass" , PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); |
231 | clk[VF610_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass" , PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); |
232 | clk[VF610_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass" , PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); |
233 | clk[VF610_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass" , PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); |
234 | |
235 | /* Do not bypass PLLs initially */ |
236 | clk_set_parent(clk: clk[VF610_PLL1_BYPASS], parent: clk[VF610_CLK_PLL1]); |
237 | clk_set_parent(clk: clk[VF610_PLL2_BYPASS], parent: clk[VF610_CLK_PLL2]); |
238 | clk_set_parent(clk: clk[VF610_PLL3_BYPASS], parent: clk[VF610_CLK_PLL3]); |
239 | clk_set_parent(clk: clk[VF610_PLL4_BYPASS], parent: clk[VF610_CLK_PLL4]); |
240 | clk_set_parent(clk: clk[VF610_PLL5_BYPASS], parent: clk[VF610_CLK_PLL5]); |
241 | clk_set_parent(clk: clk[VF610_PLL6_BYPASS], parent: clk[VF610_CLK_PLL6]); |
242 | clk_set_parent(clk: clk[VF610_PLL7_BYPASS], parent: clk[VF610_CLK_PLL7]); |
243 | |
244 | clk[VF610_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys" , "pll1_bypass" , PLL1_CTRL, 13); |
245 | clk[VF610_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus" , "pll2_bypass" , PLL2_CTRL, 13); |
246 | clk[VF610_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg" , "pll3_bypass" , PLL3_CTRL, 13); |
247 | clk[VF610_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio" , "pll4_bypass" , PLL4_CTRL, 13); |
248 | clk[VF610_CLK_PLL5_ENET] = imx_clk_gate("pll5_enet" , "pll5_bypass" , PLL5_CTRL, 13); |
249 | clk[VF610_CLK_PLL6_VIDEO] = imx_clk_gate("pll6_video" , "pll6_bypass" , PLL6_CTRL, 13); |
250 | clk[VF610_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host" , "pll7_bypass" , PLL7_CTRL, 13); |
251 | |
252 | clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in" , "anaclk1" , ANA_MISC1, 12, BIT(10)); |
253 | |
254 | clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1" , "pll1_sys" , PFD_PLL1_BASE, 0); |
255 | clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2" , "pll1_sys" , PFD_PLL1_BASE, 1); |
256 | clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3" , "pll1_sys" , PFD_PLL1_BASE, 2); |
257 | clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4" , "pll1_sys" , PFD_PLL1_BASE, 3); |
258 | |
259 | clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1" , "pll2_bus" , PFD_PLL2_BASE, 0); |
260 | clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2" , "pll2_bus" , PFD_PLL2_BASE, 1); |
261 | clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3" , "pll2_bus" , PFD_PLL2_BASE, 2); |
262 | clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4" , "pll2_bus" , PFD_PLL2_BASE, 3); |
263 | |
264 | clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1" , "pll3_usb_otg" , PFD_PLL3_BASE, 0); |
265 | clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2" , "pll3_usb_otg" , PFD_PLL3_BASE, 1); |
266 | clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3" , "pll3_usb_otg" , PFD_PLL3_BASE, 2); |
267 | clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4" , "pll3_usb_otg" , PFD_PLL3_BASE, 3); |
268 | |
269 | clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel" , CCM_CCSR, 16, 3, pll1_sels, 5); |
270 | clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel" , CCM_CCSR, 19, 3, pll2_sels, 5); |
271 | clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel" , CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); |
272 | clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel" , CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels)); |
273 | clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus" , "sys_sel" , CCM_CACRR, 0, 3); |
274 | clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus" , "sys_bus" , CCM_CACRR, 3, 3); |
275 | clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus" , "platform_bus" , CCM_CACRR, 11, 2); |
276 | |
277 | clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_usb_otg_div" , "pll3_usb_otg" , CCM_CACRR, 20, 1); |
278 | clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, name: "pll4_audio_div" , parent_name: "pll4_audio" , flags: 0, CCM_CACRR, shift: 6, width: 3, clk_divider_flags: 0, table: pll4_audio_div_table, lock: &imx_ccm_lock); |
279 | clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div" , "pll6_video" , CCM_CACRR, 21, 1); |
280 | |
281 | clk[VF610_CLK_DDRMC] = imx_clk_gate2_cgr("ddrmc" , "ddr_sel" , CCM_CCGR6, CCM_CCGRx_CGn(14), 0x2); |
282 | clk[VF610_CLK_WKPU] = imx_clk_gate2_cgr("wkpu" , "ipg_bus" , CCM_CCGR4, CCM_CCGRx_CGn(10), 0x2); |
283 | |
284 | clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0" , "pll3_usb_otg" , PLL3_CTRL, 6); |
285 | clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1" , "pll7_usb_host" , PLL7_CTRL, 6); |
286 | |
287 | clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(4)); |
288 | clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1" , "ipg_bus" , CCM_CCGR7, CCM_CCGRx_CGn(4)); |
289 | |
290 | clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel" , CCM_CSCMR1, 22, 2, qspi_sels, 4); |
291 | clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en" , "qspi0_sel" , CCM_CSCDR3, 4); |
292 | clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4" , "qspi0_en" , CCM_CSCDR3, 0, 2); |
293 | clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2" , "qspi0_x4" , CCM_CSCDR3, 2, 1); |
294 | clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1" , "qspi0_x2" , CCM_CSCDR3, 3, 1); |
295 | clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0" , "qspi0_x1" , CCM_CCGR2, CCM_CCGRx_CGn(4)); |
296 | |
297 | clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel" , CCM_CSCMR1, 24, 2, qspi_sels, 4); |
298 | clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en" , "qspi1_sel" , CCM_CSCDR3, 12); |
299 | clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4" , "qspi1_en" , CCM_CSCDR3, 8, 2); |
300 | clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2" , "qspi1_x4" , CCM_CSCDR3, 10, 1); |
301 | clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1" , "qspi1_x2" , CCM_CSCDR3, 11, 1); |
302 | clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1" , "qspi1_x1" , CCM_CCGR8, CCM_CCGRx_CGn(4)); |
303 | |
304 | clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m" , "pll5_enet" , 1, 10); |
305 | clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m" , "pll5_enet" , 1, 20); |
306 | clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel" , CCM_CSCMR2, 4, 2, rmii_sels, 4); |
307 | clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel" , CCM_CSCMR2, 0, 3, enet_ts_sels, 7); |
308 | clk[VF610_CLK_ENET] = imx_clk_gate("enet" , "enet_sel" , CCM_CSCDR1, 24); |
309 | clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts" , "enet_ts_sel" , CCM_CSCDR1, 23); |
310 | clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0" , "ipg_bus" , CCM_CCGR9, CCM_CCGRx_CGn(0)); |
311 | clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1" , "ipg_bus" , CCM_CCGR9, CCM_CCGRx_CGn(1)); |
312 | |
313 | clk[VF610_CLK_PIT] = imx_clk_gate2("pit" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(7)); |
314 | |
315 | clk[VF610_CLK_UART0] = imx_clk_gate2_cgr("uart0" , "ipg_bus" , CCM_CCGR0, CCM_CCGRx_CGn(7), 0x2); |
316 | clk[VF610_CLK_UART1] = imx_clk_gate2_cgr("uart1" , "ipg_bus" , CCM_CCGR0, CCM_CCGRx_CGn(8), 0x2); |
317 | clk[VF610_CLK_UART2] = imx_clk_gate2_cgr("uart2" , "ipg_bus" , CCM_CCGR0, CCM_CCGRx_CGn(9), 0x2); |
318 | clk[VF610_CLK_UART3] = imx_clk_gate2_cgr("uart3" , "ipg_bus" , CCM_CCGR0, CCM_CCGRx_CGn(10), 0x2); |
319 | clk[VF610_CLK_UART4] = imx_clk_gate2_cgr("uart4" , "ipg_bus" , CCM_CCGR6, CCM_CCGRx_CGn(9), 0x2); |
320 | clk[VF610_CLK_UART5] = imx_clk_gate2_cgr("uart5" , "ipg_bus" , CCM_CCGR6, CCM_CCGRx_CGn(10), 0x2); |
321 | |
322 | clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0" , "ipg_bus" , CCM_CCGR4, CCM_CCGRx_CGn(6)); |
323 | clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1" , "ipg_bus" , CCM_CCGR4, CCM_CCGRx_CGn(7)); |
324 | clk[VF610_CLK_I2C2] = imx_clk_gate2("i2c2" , "ipg_bus" , CCM_CCGR10, CCM_CCGRx_CGn(6)); |
325 | clk[VF610_CLK_I2C3] = imx_clk_gate2("i2c3" , "ipg_bus" , CCM_CCGR10, CCM_CCGRx_CGn(7)); |
326 | |
327 | clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0" , "ipg_bus" , CCM_CCGR0, CCM_CCGRx_CGn(12)); |
328 | clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1" , "ipg_bus" , CCM_CCGR0, CCM_CCGRx_CGn(13)); |
329 | clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2" , "ipg_bus" , CCM_CCGR6, CCM_CCGRx_CGn(12)); |
330 | clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3" , "ipg_bus" , CCM_CCGR6, CCM_CCGRx_CGn(13)); |
331 | |
332 | clk[VF610_CLK_CRC] = imx_clk_gate2("crc" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(3)); |
333 | clk[VF610_CLK_WDT] = imx_clk_gate2("wdt" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(14)); |
334 | |
335 | clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel" , CCM_CSCMR1, 16, 2, esdhc_sels, 4); |
336 | clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en" , "esdhc0_sel" , CCM_CSCDR2, 28); |
337 | clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div" , "esdhc0_en" , CCM_CSCDR2, 16, 4); |
338 | clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0" , "esdhc0_div" , CCM_CCGR7, CCM_CCGRx_CGn(1)); |
339 | |
340 | clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel" , CCM_CSCMR1, 18, 2, esdhc_sels, 4); |
341 | clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en" , "esdhc1_sel" , CCM_CSCDR2, 29); |
342 | clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div" , "esdhc1_en" , CCM_CSCDR2, 20, 4); |
343 | clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1" , "esdhc1_div" , CCM_CCGR7, CCM_CCGRx_CGn(2)); |
344 | |
345 | /* |
346 | * ftm_ext_clk and ftm_fix_clk are FTM timer counter's |
347 | * selectable clock sources, both use a common enable bit |
348 | * in CCM_CSCDR1, selecting "dummy" clock as parent of |
349 | * "ftm0_ext_fix" make it serve only for enable/disable. |
350 | */ |
351 | clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel" , CCM_CSCMR2, 6, 2, ftm_ext_sels, 4); |
352 | clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel" , CCM_CSCMR2, 14, 1, ftm_fix_sels, 2); |
353 | clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en" , "dummy" , CCM_CSCDR1, 25); |
354 | clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel" , CCM_CSCMR2, 8, 2, ftm_ext_sels, 4); |
355 | clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel" , CCM_CSCMR2, 15, 1, ftm_fix_sels, 2); |
356 | clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en" , "dummy" , CCM_CSCDR1, 26); |
357 | clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel" , CCM_CSCMR2, 10, 2, ftm_ext_sels, 4); |
358 | clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel" , CCM_CSCMR2, 16, 1, ftm_fix_sels, 2); |
359 | clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en" , "dummy" , CCM_CSCDR1, 27); |
360 | clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel" , CCM_CSCMR2, 12, 2, ftm_ext_sels, 4); |
361 | clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel" , CCM_CSCMR2, 17, 1, ftm_fix_sels, 2); |
362 | clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en" , "dummy" , CCM_CSCDR1, 28); |
363 | |
364 | /* ftm(n)_clk are FTM module operation clock */ |
365 | clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(8)); |
366 | clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(9)); |
367 | clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2" , "ipg_bus" , CCM_CCGR7, CCM_CCGRx_CGn(8)); |
368 | clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3" , "ipg_bus" , CCM_CCGR7, CCM_CCGRx_CGn(9)); |
369 | |
370 | clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel" , CCM_CSCMR1, 28, 1, dcu_sels, 2); |
371 | clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en" , "dcu0_sel" , CCM_CSCDR3, 19); |
372 | clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div" , "dcu0_en" , CCM_CSCDR3, 16, 3); |
373 | clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0" , "ipg_bus" , CCM_CCGR3, CCM_CCGRx_CGn(8)); |
374 | clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel" , CCM_CSCMR1, 29, 1, dcu_sels, 2); |
375 | clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en" , "dcu1_sel" , CCM_CSCDR3, 23); |
376 | clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div" , "dcu1_en" , CCM_CSCDR3, 20, 3); |
377 | clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1" , "ipg_bus" , CCM_CCGR9, CCM_CCGRx_CGn(8)); |
378 | |
379 | clk[VF610_CLK_TCON0] = imx_clk_gate2("tcon0" , "platform_bus" , CCM_CCGR1, CCM_CCGRx_CGn(13)); |
380 | clk[VF610_CLK_TCON1] = imx_clk_gate2("tcon1" , "platform_bus" , CCM_CCGR7, CCM_CCGRx_CGn(13)); |
381 | |
382 | clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel" , CCM_CSCMR1, 20, 2, esai_sels, 4); |
383 | clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en" , "esai_sel" , CCM_CSCDR2, 30); |
384 | clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div" , "esai_en" , CCM_CSCDR2, 24, 4); |
385 | clk[VF610_CLK_ESAI] = imx_clk_gate2("esai" , "esai_div" , CCM_CCGR4, CCM_CCGRx_CGn(2)); |
386 | |
387 | clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel" , CCM_CSCMR1, 0, 2, sai_sels, 4); |
388 | clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en" , "sai0_sel" , CCM_CSCDR1, 16); |
389 | clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div" , "sai0_en" , CCM_CSCDR1, 0, 4); |
390 | clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0" , "ipg_bus" , CCM_CCGR0, CCM_CCGRx_CGn(15)); |
391 | |
392 | clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel" , CCM_CSCMR1, 2, 2, sai_sels, 4); |
393 | clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en" , "sai1_sel" , CCM_CSCDR1, 17); |
394 | clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div" , "sai1_en" , CCM_CSCDR1, 4, 4); |
395 | clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(0)); |
396 | |
397 | clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel" , CCM_CSCMR1, 4, 2, sai_sels, 4); |
398 | clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en" , "sai2_sel" , CCM_CSCDR1, 18); |
399 | clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div" , "sai2_en" , CCM_CSCDR1, 8, 4); |
400 | clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(1)); |
401 | |
402 | clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel" , CCM_CSCMR1, 6, 2, sai_sels, 4); |
403 | clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en" , "sai3_sel" , CCM_CSCDR1, 19); |
404 | clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div" , "sai3_en" , CCM_CSCDR1, 12, 4); |
405 | clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(2)); |
406 | |
407 | clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel" , CCM_CSCMR1, 12, 2, nfc_sels, 4); |
408 | clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en" , "nfc_sel" , CCM_CSCDR2, 9); |
409 | clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div" , "nfc_en" , CCM_CSCDR3, 13, 3); |
410 | clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div" , "nfc_pre_div" , CCM_CSCDR2, 4, 4); |
411 | clk[VF610_CLK_NFC] = imx_clk_gate2("nfc" , "nfc_frac_div" , CCM_CCGR10, CCM_CCGRx_CGn(0)); |
412 | |
413 | clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel" , CCM_CSCMR1, 14, 1, gpu_sels, 2); |
414 | clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en" , "gpu_sel" , CCM_CSCDR2, 10); |
415 | clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu" , "gpu_en" , CCM_CCGR8, CCM_CCGRx_CGn(15)); |
416 | |
417 | clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel" , CCM_CSCMR1, 8, 2, vadc_sels, 3); |
418 | clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en" , "vadc_sel" , CCM_CSCDR1, 22); |
419 | clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div" , "vadc_en" , CCM_CSCDR1, 20, 2); |
420 | clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half" , "vadc_div" , 1, 2); |
421 | clk[VF610_CLK_VADC] = imx_clk_gate2("vadc" , "vadc_div" , CCM_CCGR8, CCM_CCGRx_CGn(7)); |
422 | |
423 | clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0" , "ipg_bus" , CCM_CCGR1, CCM_CCGRx_CGn(11)); |
424 | clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1" , "ipg_bus" , CCM_CCGR7, CCM_CCGRx_CGn(11)); |
425 | clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0" , "ipg_bus" , CCM_CCGR8, CCM_CCGRx_CGn(12)); |
426 | clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1" , "ipg_bus" , CCM_CCGR8, CCM_CCGRx_CGn(13)); |
427 | |
428 | clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc" , "ipg_bus" , CCM_CCGR4, CCM_CCGRx_CGn(1)); |
429 | |
430 | clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en" , "ipg_bus" , CCM_CSCDR2, 11); |
431 | clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0" , "flexcan0_en" , CCM_CCGR0, CCM_CCGRx_CGn(0)); |
432 | clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en" , "ipg_bus" , CCM_CSCDR2, 12); |
433 | clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1" , "flexcan1_en" , CCM_CCGR9, CCM_CCGRx_CGn(4)); |
434 | |
435 | clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0" , "platform_bus" , CCM_CCGR0, CCM_CCGRx_CGn(4)); |
436 | clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1" , "platform_bus" , CCM_CCGR0, CCM_CCGRx_CGn(5)); |
437 | clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2" , "platform_bus" , CCM_CCGR6, CCM_CCGRx_CGn(1)); |
438 | clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3" , "platform_bus" , CCM_CCGR6, CCM_CCGRx_CGn(2)); |
439 | |
440 | clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc" , "ipg_bus" , CCM_CCGR6, CCM_CCGRx_CGn(7)); |
441 | clk[VF610_CLK_DAP] = imx_clk_gate("dap" , "platform_bus" , CCM_CCSR, 24); |
442 | clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp" , "ipg_bus" , CCM_CCGR6, CCM_CCGRx_CGn(5)); |
443 | clk[VF610_CLK_CAAM] = imx_clk_gate2("caam" , "ipg_bus" , CCM_CCGR11, CCM_CCGRx_CGn(0)); |
444 | |
445 | imx_check_clocks(clks: clk, ARRAY_SIZE(clk)); |
446 | |
447 | clk_set_parent(clk: clk[VF610_CLK_QSPI0_SEL], parent: clk[VF610_CLK_PLL1_PFD4]); |
448 | clk_set_rate(clk: clk[VF610_CLK_QSPI0_X4_DIV], rate: clk_get_rate(clk: clk[VF610_CLK_QSPI0_SEL]) / 2); |
449 | clk_set_rate(clk: clk[VF610_CLK_QSPI0_X2_DIV], rate: clk_get_rate(clk: clk[VF610_CLK_QSPI0_X4_DIV]) / 2); |
450 | clk_set_rate(clk: clk[VF610_CLK_QSPI0_X1_DIV], rate: clk_get_rate(clk: clk[VF610_CLK_QSPI0_X2_DIV]) / 2); |
451 | |
452 | clk_set_parent(clk: clk[VF610_CLK_QSPI1_SEL], parent: clk[VF610_CLK_PLL1_PFD4]); |
453 | clk_set_rate(clk: clk[VF610_CLK_QSPI1_X4_DIV], rate: clk_get_rate(clk: clk[VF610_CLK_QSPI1_SEL]) / 2); |
454 | clk_set_rate(clk: clk[VF610_CLK_QSPI1_X2_DIV], rate: clk_get_rate(clk: clk[VF610_CLK_QSPI1_X4_DIV]) / 2); |
455 | clk_set_rate(clk: clk[VF610_CLK_QSPI1_X1_DIV], rate: clk_get_rate(clk: clk[VF610_CLK_QSPI1_X2_DIV]) / 2); |
456 | |
457 | clk_set_parent(clk: clk[VF610_CLK_SAI0_SEL], parent: clk[VF610_CLK_AUDIO_EXT]); |
458 | clk_set_parent(clk: clk[VF610_CLK_SAI1_SEL], parent: clk[VF610_CLK_AUDIO_EXT]); |
459 | clk_set_parent(clk: clk[VF610_CLK_SAI2_SEL], parent: clk[VF610_CLK_AUDIO_EXT]); |
460 | clk_set_parent(clk: clk[VF610_CLK_SAI3_SEL], parent: clk[VF610_CLK_AUDIO_EXT]); |
461 | |
462 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
463 | clk_prepare_enable(clk: clk[clks_init_on[i]]); |
464 | |
465 | register_syscore_ops(ops: &vf610_clk_syscore_ops); |
466 | |
467 | /* Add the clocks to provider list */ |
468 | clk_data.clks = clk; |
469 | clk_data.clk_num = ARRAY_SIZE(clk); |
470 | of_clk_add_provider(np, clk_src_get: of_clk_src_onecell_get, data: &clk_data); |
471 | } |
472 | CLK_OF_DECLARE(vf610, "fsl,vf610-ccm" , vf610_clocks_init); |
473 | |