1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2017 MediaTek Inc. |
4 | * Author: Weiyi Lu <weiyi.lu@mediatek.com> |
5 | */ |
6 | |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/platform_device.h> |
9 | |
10 | #include "clk-mtk.h" |
11 | #include "clk-gate.h" |
12 | |
13 | #include <dt-bindings/clock/mt2712-clk.h> |
14 | |
15 | static const struct mtk_gate_regs bdp_cg_regs = { |
16 | .set_ofs = 0x100, |
17 | .clr_ofs = 0x100, |
18 | .sta_ofs = 0x100, |
19 | }; |
20 | |
21 | #define GATE_BDP(_id, _name, _parent, _shift) \ |
22 | GATE_MTK(_id, _name, _parent, &bdp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) |
23 | |
24 | static const struct mtk_gate bdp_clks[] = { |
25 | GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b" , "mm_sel" , 0), |
26 | GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d" , "mm_sel" , 1), |
27 | GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d" , "mm_sel" , 2), |
28 | GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl" , "tvd_sel" , 3), |
29 | GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d" , "mm_sel" , 4), |
30 | GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b" , "mm_sel" , 5), |
31 | GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b" , "mm_sel" , 9), |
32 | GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m" , "di_sel" , 10), |
33 | GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout" , "di_sel" , 11), |
34 | GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74" , "di_sel" , 12), |
35 | GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs" , "di_sel" , 13), |
36 | GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148" , "di_sel" , 14), |
37 | GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b" , "mm_sel" , 15), |
38 | GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d" , "mm_sel" , 16), |
39 | GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs" , "di_sel" , 17), |
40 | GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b" , "mm_sel" , 18), |
41 | GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl" , "di_sel" , 19), |
42 | GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d" , "mm_sel" , 20), |
43 | GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b" , "mm_sel" , 21), |
44 | GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent" , "nr_sel" , 22), |
45 | GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d" , "mm_sel" , 23), |
46 | GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b" , "mm_sel" , 24), |
47 | GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b" , "mm_sel" , 25), |
48 | GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d" , "mm_sel" , 26), |
49 | GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d" , "mm_sel" , 27), |
50 | GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc" , "mm_sel" , 28), |
51 | GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54" , "tvd_sel" , 29), |
52 | GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus" , "mm_sel" , 30), |
53 | }; |
54 | |
55 | static const struct mtk_clk_desc bdp_desc = { |
56 | .clks = bdp_clks, |
57 | .num_clks = ARRAY_SIZE(bdp_clks), |
58 | }; |
59 | |
60 | static const struct of_device_id of_match_clk_mt2712_bdp[] = { |
61 | { |
62 | .compatible = "mediatek,mt2712-bdpsys" , |
63 | .data = &bdp_desc, |
64 | }, { |
65 | /* sentinel */ |
66 | } |
67 | }; |
68 | MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_bdp); |
69 | |
70 | static struct platform_driver clk_mt2712_bdp_drv = { |
71 | .probe = mtk_clk_simple_probe, |
72 | .remove_new = mtk_clk_simple_remove, |
73 | .driver = { |
74 | .name = "clk-mt2712-bdp" , |
75 | .of_match_table = of_match_clk_mt2712_bdp, |
76 | }, |
77 | }; |
78 | module_platform_driver(clk_mt2712_bdp_drv); |
79 | MODULE_LICENSE("GPL" ); |
80 | |