1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2017 MediaTek Inc. |
4 | * Author: Chen Zhong <chen.zhong@mediatek.com> |
5 | * Sean Wang <sean.wang@mediatek.com> |
6 | */ |
7 | |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/mod_devicetable.h> |
10 | #include <linux/platform_device.h> |
11 | |
12 | #include "clk-mtk.h" |
13 | #include "clk-gate.h" |
14 | |
15 | #include <dt-bindings/clock/mt7622-clk.h> |
16 | |
17 | #define GATE_PCIE(_id, _name, _parent, _shift) \ |
18 | GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
19 | |
20 | #define GATE_SSUSB(_id, _name, _parent, _shift) \ |
21 | GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
22 | |
23 | static const struct mtk_gate_regs pcie_cg_regs = { |
24 | .set_ofs = 0x30, |
25 | .clr_ofs = 0x30, |
26 | .sta_ofs = 0x30, |
27 | }; |
28 | |
29 | static const struct mtk_gate_regs ssusb_cg_regs = { |
30 | .set_ofs = 0x30, |
31 | .clr_ofs = 0x30, |
32 | .sta_ofs = 0x30, |
33 | }; |
34 | |
35 | static const struct mtk_gate ssusb_clks[] = { |
36 | GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p" , |
37 | "to_u2_phy_1p" , 0), |
38 | GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en" , "to_u2_phy" , 1), |
39 | GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en" , "to_usb3_ref" , 5), |
40 | GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en" , "to_usb3_sys" , 6), |
41 | GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en" , "axi_sel" , 7), |
42 | GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en" , "hif_sel" , 8), |
43 | }; |
44 | |
45 | static const struct mtk_gate pcie_clks[] = { |
46 | GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en" , "p1_1mhz" , 12), |
47 | GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en" , "free_run_4mhz" , 13), |
48 | GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en" , "axi_sel" , 14), |
49 | GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en" , "hif_sel" , 15), |
50 | GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en" , "pcie1_mac_en" , 16), |
51 | GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en" , "pcie1_pipe_en" , 17), |
52 | GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en" , "p0_1mhz" , 18), |
53 | GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en" , "free_run_4mhz" , 19), |
54 | GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en" , "axi_sel" , 20), |
55 | GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en" , "hif_sel" , 21), |
56 | GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en" , "pcie0_mac_en" , 22), |
57 | GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en" , "pcie0_pipe_en" , 23), |
58 | GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en" , "axi_sel" , 26), |
59 | GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en" , "hif_sel" , 27), |
60 | GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en" , "sata_asic" , 28), |
61 | GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en" , "sata_rbc" , 29), |
62 | GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en" , "univpll2_d4" , 30), |
63 | }; |
64 | |
65 | static u16 rst_ofs[] = { 0x34, }; |
66 | |
67 | static const struct mtk_clk_rst_desc clk_rst_desc = { |
68 | .version = MTK_RST_SIMPLE, |
69 | .rst_bank_ofs = rst_ofs, |
70 | .rst_bank_nr = ARRAY_SIZE(rst_ofs), |
71 | }; |
72 | |
73 | static const struct mtk_clk_desc ssusb_desc = { |
74 | .clks = ssusb_clks, |
75 | .num_clks = ARRAY_SIZE(ssusb_clks), |
76 | .rst_desc = &clk_rst_desc, |
77 | }; |
78 | |
79 | static const struct mtk_clk_desc pcie_desc = { |
80 | .clks = pcie_clks, |
81 | .num_clks = ARRAY_SIZE(pcie_clks), |
82 | .rst_desc = &clk_rst_desc, |
83 | }; |
84 | |
85 | static const struct of_device_id of_match_clk_mt7622_hif[] = { |
86 | { .compatible = "mediatek,mt7622-pciesys" , .data = &pcie_desc }, |
87 | { .compatible = "mediatek,mt7622-ssusbsys" , .data = &ssusb_desc }, |
88 | { /* sentinel */ } |
89 | }; |
90 | MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_hif); |
91 | |
92 | static struct platform_driver clk_mt7622_hif_drv = { |
93 | .probe = mtk_clk_simple_probe, |
94 | .remove_new = mtk_clk_simple_remove, |
95 | .driver = { |
96 | .name = "clk-mt7622-hif" , |
97 | .of_match_table = of_match_clk_mt7622_hif, |
98 | }, |
99 | }; |
100 | module_platform_driver(clk_mt7622_hif_drv); |
101 | MODULE_LICENSE("GPL" ); |
102 | |