1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/container_of.h>
9#include <linux/delay.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of_address.h>
14#include <linux/slab.h>
15
16#include "clk-pll.h"
17
18#define MHZ (1000 * 1000)
19
20#define REG_CON0 0
21#define REG_CON1 4
22
23#define CON0_BASE_EN BIT(0)
24#define CON0_PWR_ON BIT(0)
25#define CON0_ISO_EN BIT(1)
26#define PCW_CHG_MASK BIT(31)
27
28#define AUDPLL_TUNER_EN BIT(31)
29
30/* default 7 bits integer, can be overridden with pcwibits. */
31#define INTEGER_BITS 7
32
33int mtk_pll_is_prepared(struct clk_hw *hw)
34{
35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
36
37 return (readl(addr: pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
38}
39
40static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
41 u32 pcw, int postdiv)
42{
43 int pcwbits = pll->data->pcwbits;
44 int pcwfbits = 0;
45 int ibits;
46 u64 vco;
47 u8 c = 0;
48
49 /* The fractional part of the PLL divider. */
50 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
51 if (pcwbits > ibits)
52 pcwfbits = pcwbits - ibits;
53
54 vco = (u64)fin * pcw;
55
56 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
57 c = 1;
58
59 vco >>= pcwfbits;
60
61 if (c)
62 vco++;
63
64 return ((unsigned long)vco + postdiv - 1) / postdiv;
65}
66
67static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
68{
69 u32 r;
70
71 if (pll->tuner_en_addr) {
72 r = readl(addr: pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
73 writel(val: r, addr: pll->tuner_en_addr);
74 } else if (pll->tuner_addr) {
75 r = readl(addr: pll->tuner_addr) | AUDPLL_TUNER_EN;
76 writel(val: r, addr: pll->tuner_addr);
77 }
78}
79
80static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
81{
82 u32 r;
83
84 if (pll->tuner_en_addr) {
85 r = readl(addr: pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
86 writel(val: r, addr: pll->tuner_en_addr);
87 } else if (pll->tuner_addr) {
88 r = readl(addr: pll->tuner_addr) & ~AUDPLL_TUNER_EN;
89 writel(val: r, addr: pll->tuner_addr);
90 }
91}
92
93static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
94 int postdiv)
95{
96 u32 chg, val;
97
98 /* disable tuner */
99 __mtk_pll_tuner_disable(pll);
100
101 /* set postdiv */
102 val = readl(addr: pll->pd_addr);
103 val &= ~(POSTDIV_MASK << pll->data->pd_shift);
104 val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
105
106 /* postdiv and pcw need to set at the same time if on same register */
107 if (pll->pd_addr != pll->pcw_addr) {
108 writel(val, addr: pll->pd_addr);
109 val = readl(addr: pll->pcw_addr);
110 }
111
112 /* set pcw */
113 val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
114 pll->data->pcw_shift);
115 val |= pcw << pll->data->pcw_shift;
116 writel(val, addr: pll->pcw_addr);
117 chg = readl(addr: pll->pcw_chg_addr) | PCW_CHG_MASK;
118 writel(val: chg, addr: pll->pcw_chg_addr);
119 if (pll->tuner_addr)
120 writel(val: val + 1, addr: pll->tuner_addr);
121
122 /* restore tuner_en */
123 __mtk_pll_tuner_enable(pll);
124
125 udelay(20);
126}
127
128/*
129 * mtk_pll_calc_values - calculate good values for a given input frequency.
130 * @pll: The pll
131 * @pcw: The pcw value (output)
132 * @postdiv: The post divider (output)
133 * @freq: The desired target frequency
134 * @fin: The input frequency
135 *
136 */
137void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
138 u32 freq, u32 fin)
139{
140 unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
141 const struct mtk_pll_div_table *div_table = pll->data->div_table;
142 u64 _pcw;
143 int ibits;
144 u32 val;
145
146 if (freq > pll->data->fmax)
147 freq = pll->data->fmax;
148
149 if (div_table) {
150 if (freq > div_table[0].freq)
151 freq = div_table[0].freq;
152
153 for (val = 0; div_table[val + 1].freq != 0; val++) {
154 if (freq > div_table[val + 1].freq)
155 break;
156 }
157 *postdiv = 1 << val;
158 } else {
159 for (val = 0; val < 5; val++) {
160 *postdiv = 1 << val;
161 if ((u64)freq * *postdiv >= fmin)
162 break;
163 }
164 }
165
166 /* _pcw = freq * postdiv / fin * 2^pcwfbits */
167 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
168 _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
169 do_div(_pcw, fin);
170
171 *pcw = (u32)_pcw;
172}
173
174int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
175 unsigned long parent_rate)
176{
177 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
178 u32 pcw = 0;
179 u32 postdiv;
180
181 mtk_pll_calc_values(pll, pcw: &pcw, postdiv: &postdiv, freq: rate, fin: parent_rate);
182 mtk_pll_set_rate_regs(pll, pcw, postdiv);
183
184 return 0;
185}
186
187unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
188{
189 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
190 u32 postdiv;
191 u32 pcw;
192
193 postdiv = (readl(addr: pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
194 postdiv = 1 << postdiv;
195
196 pcw = readl(addr: pll->pcw_addr) >> pll->data->pcw_shift;
197 pcw &= GENMASK(pll->data->pcwbits - 1, 0);
198
199 return __mtk_pll_recalc_rate(pll, fin: parent_rate, pcw, postdiv);
200}
201
202long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
203 unsigned long *prate)
204{
205 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
206 u32 pcw = 0;
207 int postdiv;
208
209 mtk_pll_calc_values(pll, pcw: &pcw, postdiv: &postdiv, freq: rate, fin: *prate);
210
211 return __mtk_pll_recalc_rate(pll, fin: *prate, pcw, postdiv);
212}
213
214int mtk_pll_prepare(struct clk_hw *hw)
215{
216 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
217 u32 r;
218
219 r = readl(addr: pll->pwr_addr) | CON0_PWR_ON;
220 writel(val: r, addr: pll->pwr_addr);
221 udelay(1);
222
223 r = readl(addr: pll->pwr_addr) & ~CON0_ISO_EN;
224 writel(val: r, addr: pll->pwr_addr);
225 udelay(1);
226
227 r = readl(addr: pll->en_addr) | BIT(pll->data->pll_en_bit);
228 writel(val: r, addr: pll->en_addr);
229
230 if (pll->data->en_mask) {
231 r = readl(addr: pll->base_addr + REG_CON0) | pll->data->en_mask;
232 writel(val: r, addr: pll->base_addr + REG_CON0);
233 }
234
235 __mtk_pll_tuner_enable(pll);
236
237 udelay(20);
238
239 if (pll->data->flags & HAVE_RST_BAR) {
240 r = readl(addr: pll->base_addr + REG_CON0);
241 r |= pll->data->rst_bar_mask;
242 writel(val: r, addr: pll->base_addr + REG_CON0);
243 }
244
245 return 0;
246}
247
248void mtk_pll_unprepare(struct clk_hw *hw)
249{
250 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
251 u32 r;
252
253 if (pll->data->flags & HAVE_RST_BAR) {
254 r = readl(addr: pll->base_addr + REG_CON0);
255 r &= ~pll->data->rst_bar_mask;
256 writel(val: r, addr: pll->base_addr + REG_CON0);
257 }
258
259 __mtk_pll_tuner_disable(pll);
260
261 if (pll->data->en_mask) {
262 r = readl(addr: pll->base_addr + REG_CON0) & ~pll->data->en_mask;
263 writel(val: r, addr: pll->base_addr + REG_CON0);
264 }
265
266 r = readl(addr: pll->en_addr) & ~BIT(pll->data->pll_en_bit);
267 writel(val: r, addr: pll->en_addr);
268
269 r = readl(addr: pll->pwr_addr) | CON0_ISO_EN;
270 writel(val: r, addr: pll->pwr_addr);
271
272 r = readl(addr: pll->pwr_addr) & ~CON0_PWR_ON;
273 writel(val: r, addr: pll->pwr_addr);
274}
275
276const struct clk_ops mtk_pll_ops = {
277 .is_prepared = mtk_pll_is_prepared,
278 .prepare = mtk_pll_prepare,
279 .unprepare = mtk_pll_unprepare,
280 .recalc_rate = mtk_pll_recalc_rate,
281 .round_rate = mtk_pll_round_rate,
282 .set_rate = mtk_pll_set_rate,
283};
284
285struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
286 const struct mtk_pll_data *data,
287 void __iomem *base,
288 const struct clk_ops *pll_ops)
289{
290 struct clk_init_data init = {};
291 int ret;
292 const char *parent_name = "clk26m";
293
294 pll->base_addr = base + data->reg;
295 pll->pwr_addr = base + data->pwr_reg;
296 pll->pd_addr = base + data->pd_reg;
297 pll->pcw_addr = base + data->pcw_reg;
298 if (data->pcw_chg_reg)
299 pll->pcw_chg_addr = base + data->pcw_chg_reg;
300 else
301 pll->pcw_chg_addr = pll->base_addr + REG_CON1;
302 if (data->tuner_reg)
303 pll->tuner_addr = base + data->tuner_reg;
304 if (data->tuner_en_reg || data->tuner_en_bit)
305 pll->tuner_en_addr = base + data->tuner_en_reg;
306 if (data->en_reg)
307 pll->en_addr = base + data->en_reg;
308 else
309 pll->en_addr = pll->base_addr + REG_CON0;
310 pll->hw.init = &init;
311 pll->data = data;
312
313 init.name = data->name;
314 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
315 init.ops = pll_ops;
316 if (data->parent_name)
317 init.parent_names = &data->parent_name;
318 else
319 init.parent_names = &parent_name;
320 init.num_parents = 1;
321
322 ret = clk_hw_register(NULL, hw: &pll->hw);
323
324 if (ret)
325 return ERR_PTR(error: ret);
326
327 return &pll->hw;
328}
329
330struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
331 void __iomem *base)
332{
333 struct mtk_clk_pll *pll;
334 struct clk_hw *hw;
335
336 pll = kzalloc(size: sizeof(*pll), GFP_KERNEL);
337 if (!pll)
338 return ERR_PTR(error: -ENOMEM);
339
340 hw = mtk_clk_register_pll_ops(pll, data, base, pll_ops: &mtk_pll_ops);
341 if (IS_ERR(ptr: hw))
342 kfree(objp: pll);
343
344 return hw;
345}
346
347void mtk_clk_unregister_pll(struct clk_hw *hw)
348{
349 struct mtk_clk_pll *pll;
350
351 if (!hw)
352 return;
353
354 pll = to_mtk_clk_pll(hw);
355
356 clk_hw_unregister(hw);
357 kfree(objp: pll);
358}
359
360int mtk_clk_register_plls(struct device_node *node,
361 const struct mtk_pll_data *plls, int num_plls,
362 struct clk_hw_onecell_data *clk_data)
363{
364 void __iomem *base;
365 int i;
366 struct clk_hw *hw;
367
368 base = of_iomap(node, index: 0);
369 if (!base) {
370 pr_err("%s(): ioremap failed\n", __func__);
371 return -EINVAL;
372 }
373
374 for (i = 0; i < num_plls; i++) {
375 const struct mtk_pll_data *pll = &plls[i];
376
377 if (!IS_ERR_OR_NULL(ptr: clk_data->hws[pll->id])) {
378 pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
379 node, pll->id);
380 continue;
381 }
382
383 hw = mtk_clk_register_pll(data: pll, base);
384
385 if (IS_ERR(ptr: hw)) {
386 pr_err("Failed to register clk %s: %pe\n", pll->name,
387 hw);
388 goto err;
389 }
390
391 clk_data->hws[pll->id] = hw;
392 }
393
394 return 0;
395
396err:
397 while (--i >= 0) {
398 const struct mtk_pll_data *pll = &plls[i];
399
400 mtk_clk_unregister_pll(hw: clk_data->hws[pll->id]);
401 clk_data->hws[pll->id] = ERR_PTR(error: -ENOENT);
402 }
403
404 iounmap(addr: base);
405
406 return PTR_ERR(ptr: hw);
407}
408EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
409
410__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
411 const struct mtk_pll_data *data)
412{
413 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
414
415 return pll->base_addr - data->reg;
416}
417
418void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
419 struct clk_hw_onecell_data *clk_data)
420{
421 __iomem void *base = NULL;
422 int i;
423
424 if (!clk_data)
425 return;
426
427 for (i = num_plls; i > 0; i--) {
428 const struct mtk_pll_data *pll = &plls[i - 1];
429
430 if (IS_ERR_OR_NULL(ptr: clk_data->hws[pll->id]))
431 continue;
432
433 /*
434 * This is quite ugly but unfortunately the clks don't have
435 * any device tied to them, so there's no place to store the
436 * pointer to the I/O region base address. We have to fetch
437 * it from one of the registered clks.
438 */
439 base = mtk_clk_pll_get_base(hw: clk_data->hws[pll->id], data: pll);
440
441 mtk_clk_unregister_pll(hw: clk_data->hws[pll->id]);
442 clk_data->hws[pll->id] = ERR_PTR(error: -ENOENT);
443 }
444
445 iounmap(addr: base);
446}
447EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls);
448
449MODULE_LICENSE("GPL");
450

source code of linux/drivers/clk/mediatek/clk-pll.c