| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2018 BayLibre, SAS. |
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| 4 | * Author: Jerome Brunet <jbrunet@baylibre.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __AXG_AUDIO_CLKC_H |
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| 8 | #define __AXG_AUDIO_CLKC_H |
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| 9 | |
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| 10 | /* |
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| 11 | * Audio Clock register offsets |
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| 12 | * |
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| 13 | * Register offsets from the datasheet must be multiplied by 4 before |
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| 14 | * to get the right offset |
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| 15 | */ |
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| 16 | #define AUDIO_CLK_GATE_EN 0x000 |
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| 17 | #define AUDIO_MCLK_A_CTRL 0x004 |
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| 18 | #define AUDIO_MCLK_B_CTRL 0x008 |
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| 19 | #define AUDIO_MCLK_C_CTRL 0x00C |
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| 20 | #define AUDIO_MCLK_D_CTRL 0x010 |
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| 21 | #define AUDIO_MCLK_E_CTRL 0x014 |
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| 22 | #define AUDIO_MCLK_F_CTRL 0x018 |
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| 23 | #define AUDIO_MST_PAD_CTRL0 0x01c |
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| 24 | #define AUDIO_MST_PAD_CTRL1 0x020 |
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| 25 | #define AUDIO_SW_RESET 0x024 |
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| 26 | #define AUDIO_MST_A_SCLK_CTRL0 0x040 |
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| 27 | #define AUDIO_MST_A_SCLK_CTRL1 0x044 |
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| 28 | #define AUDIO_MST_B_SCLK_CTRL0 0x048 |
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| 29 | #define AUDIO_MST_B_SCLK_CTRL1 0x04C |
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| 30 | #define AUDIO_MST_C_SCLK_CTRL0 0x050 |
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| 31 | #define AUDIO_MST_C_SCLK_CTRL1 0x054 |
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| 32 | #define AUDIO_MST_D_SCLK_CTRL0 0x058 |
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| 33 | #define AUDIO_MST_D_SCLK_CTRL1 0x05C |
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| 34 | #define AUDIO_MST_E_SCLK_CTRL0 0x060 |
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| 35 | #define AUDIO_MST_E_SCLK_CTRL1 0x064 |
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| 36 | #define AUDIO_MST_F_SCLK_CTRL0 0x068 |
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| 37 | #define AUDIO_MST_F_SCLK_CTRL1 0x06C |
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| 38 | #define AUDIO_CLK_TDMIN_A_CTRL 0x080 |
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| 39 | #define AUDIO_CLK_TDMIN_B_CTRL 0x084 |
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| 40 | #define AUDIO_CLK_TDMIN_C_CTRL 0x088 |
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| 41 | #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C |
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| 42 | #define AUDIO_CLK_TDMOUT_A_CTRL 0x090 |
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| 43 | #define AUDIO_CLK_TDMOUT_B_CTRL 0x094 |
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| 44 | #define AUDIO_CLK_TDMOUT_C_CTRL 0x098 |
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| 45 | #define AUDIO_CLK_SPDIFIN_CTRL 0x09C |
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| 46 | #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 |
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| 47 | #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 |
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| 48 | #define AUDIO_CLK_LOCKER_CTRL 0x0A8 |
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| 49 | #define AUDIO_CLK_PDMIN_CTRL0 0x0AC |
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| 50 | #define AUDIO_CLK_PDMIN_CTRL1 0x0B0 |
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| 51 | #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 |
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| 52 | |
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| 53 | /* SM1 introduce new register and some shifts :( */ |
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| 54 | #define AUDIO_CLK_GATE_EN1 0x004 |
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| 55 | #define AUDIO_SM1_MCLK_A_CTRL 0x008 |
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| 56 | #define AUDIO_SM1_MCLK_B_CTRL 0x00C |
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| 57 | #define AUDIO_SM1_MCLK_C_CTRL 0x010 |
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| 58 | #define AUDIO_SM1_MCLK_D_CTRL 0x014 |
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| 59 | #define AUDIO_SM1_MCLK_E_CTRL 0x018 |
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| 60 | #define AUDIO_SM1_MCLK_F_CTRL 0x01C |
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| 61 | #define AUDIO_SM1_MST_PAD_CTRL0 0x020 |
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| 62 | #define AUDIO_SM1_MST_PAD_CTRL1 0x024 |
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| 63 | #define AUDIO_SM1_SW_RESET0 0x028 |
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| 64 | #define AUDIO_SM1_SW_RESET1 0x02C |
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| 65 | #define AUDIO_CLK81_CTRL 0x030 |
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| 66 | #define AUDIO_CLK81_EN 0x034 |
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| 67 | |
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| 68 | #endif /*__AXG_AUDIO_CLKC_H */ |
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| 69 | |
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