| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2016 AmLogic, Inc. |
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| 4 | * Author: Michael Turquette <mturquette@baylibre.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __GXBB_H |
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| 8 | #define __GXBB_H |
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| 9 | |
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| 10 | /* |
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| 11 | * Clock controller register offsets |
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| 12 | * |
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| 13 | * Register offsets from the data sheet are listed in comment blocks below. |
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| 14 | * Those offsets must be multiplied by 4 before adding them to the base address |
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| 15 | * to get the right value |
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| 16 | */ |
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| 17 | #define SCR 0x2C /* 0x0b offset in data sheet */ |
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| 18 | #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ |
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| 19 | |
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| 20 | #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ |
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| 21 | #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ |
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| 22 | #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ |
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| 23 | #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ |
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| 24 | #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ |
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| 25 | #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ |
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| 26 | |
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| 27 | #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ |
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| 28 | #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ |
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| 29 | |
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| 30 | #define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ |
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| 31 | #define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ |
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| 32 | #define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ |
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| 33 | #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ |
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| 34 | #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ |
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| 35 | |
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| 36 | #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ |
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| 37 | #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ |
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| 38 | #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ |
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| 39 | #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ |
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| 40 | #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ |
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| 41 | #define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ |
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| 42 | #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ |
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| 43 | #define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ |
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| 44 | #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ |
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| 45 | |
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| 46 | #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ |
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| 47 | #define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ |
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| 48 | #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ |
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| 49 | #define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ |
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| 50 | #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ |
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| 51 | #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ |
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| 52 | #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ |
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| 53 | #define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ |
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| 54 | #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ |
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| 55 | #define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ |
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| 56 | |
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| 57 | #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ |
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| 58 | #define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ |
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| 59 | #define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ |
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| 60 | #define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ |
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| 61 | #define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ |
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| 62 | #define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ |
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| 63 | #define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ |
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| 64 | |
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| 65 | #define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ |
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| 66 | #define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ |
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| 67 | #define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ |
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| 68 | #define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ |
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| 69 | |
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| 70 | #define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ |
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| 71 | #define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ |
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| 72 | #define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ |
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| 73 | |
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| 74 | #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ |
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| 75 | #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ |
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| 76 | #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ |
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| 77 | #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ |
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| 78 | #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ |
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| 79 | #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ |
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| 80 | #define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */ |
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| 81 | #define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */ |
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| 82 | #define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */ |
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| 83 | #define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */ |
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| 84 | |
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| 85 | #define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ |
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| 86 | #define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ |
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| 87 | #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ |
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| 88 | #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ |
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| 89 | |
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| 90 | #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ |
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| 91 | #define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ |
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| 92 | #define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ |
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| 93 | #define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ |
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| 94 | #define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ |
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| 95 | #define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ |
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| 96 | #define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ |
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| 97 | #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ |
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| 98 | #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ |
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| 99 | #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ |
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| 100 | #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ |
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| 101 | #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ |
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| 102 | #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ |
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| 103 | #define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ |
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| 104 | #define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ |
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| 105 | |
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| 106 | #define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ |
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| 107 | #define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ |
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| 108 | #define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ |
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| 109 | #define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ |
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| 110 | |
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| 111 | #define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ |
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| 112 | #define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ |
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| 113 | #define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ |
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| 114 | |
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| 115 | #endif /* __GXBB_H */ |
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| 116 | |
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