| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2015 Endless Mobile, Inc. |
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| 4 | * Author: Carlo Caione <carlo@endlessm.com> |
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| 5 | * |
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| 6 | * Copyright (c) 2016 BayLibre, Inc. |
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| 7 | * Michael Turquette <mturquette@baylibre.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __MESON8B_H |
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| 11 | #define __MESON8B_H |
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| 12 | |
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| 13 | /* |
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| 14 | * Clock controller register offsets |
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| 15 | * |
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| 16 | * Register offsets from the HardKernel[0] data sheet are listed in comment |
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| 17 | * blocks below. Those offsets must be multiplied by 4 before adding them to |
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| 18 | * the base address to get the right value |
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| 19 | * |
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| 20 | * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf |
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| 21 | */ |
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| 22 | #define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ |
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| 23 | #define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ |
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| 24 | #define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ |
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| 25 | #define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */ |
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| 26 | #define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ |
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| 27 | #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ |
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| 28 | #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ |
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| 29 | #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ |
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| 30 | #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ |
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| 31 | #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ |
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| 32 | #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ |
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| 33 | #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ |
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| 34 | #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ |
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| 35 | #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ |
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| 36 | #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ |
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| 37 | #define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ |
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| 38 | #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ |
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| 39 | #define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ |
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| 40 | #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ |
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| 41 | #define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ |
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| 42 | #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ |
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| 43 | #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ |
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| 44 | #define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */ |
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| 45 | #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ |
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| 46 | #define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */ |
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| 47 | #define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */ |
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| 48 | #define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */ |
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| 49 | #define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */ |
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| 50 | #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ |
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| 51 | #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ |
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| 52 | #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ |
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| 53 | #define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ |
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| 54 | #define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ |
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| 55 | #define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */ |
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| 56 | #define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ |
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| 57 | #define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ |
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| 58 | #define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */ |
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| 59 | #define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */ |
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| 60 | #define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */ |
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| 61 | #define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */ |
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| 62 | #define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */ |
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| 63 | #define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */ |
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| 64 | |
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| 65 | /* |
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| 66 | * MPLL register offeset taken from the S905 datasheet. Vendor kernel source |
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| 67 | * confirm these are the same for the S805. |
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| 68 | */ |
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| 69 | #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ |
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| 70 | #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ |
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| 71 | #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ |
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| 72 | #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ |
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| 73 | #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ |
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| 74 | #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ |
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| 75 | #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ |
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| 76 | #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ |
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| 77 | #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ |
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| 78 | #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ |
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| 79 | |
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| 80 | #endif /* __MESON8B_H */ |
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| 81 | |
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