1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
2 | /* |
3 | * Copyright (c) 2018 BayLibre, SAS. |
4 | * Author: Jerome Brunet <jbrunet@baylibre.com> |
5 | * |
6 | * Sample clock generator divider: |
7 | * This HW divider gates with value 0 but is otherwise a zero based divider: |
8 | * |
9 | * val >= 1 |
10 | * divider = val + 1 |
11 | * |
12 | * The duty cycle may also be set for the LR clock variant. The duty cycle |
13 | * ratio is: |
14 | * |
15 | * hi = [0 - val] |
16 | * duty_cycle = (1 + hi) / (1 + val) |
17 | */ |
18 | |
19 | #include <linux/clk-provider.h> |
20 | #include <linux/module.h> |
21 | |
22 | #include "clk-regmap.h" |
23 | #include "sclk-div.h" |
24 | |
25 | static inline struct meson_sclk_div_data * |
26 | meson_sclk_div_data(struct clk_regmap *clk) |
27 | { |
28 | return (struct meson_sclk_div_data *)clk->data; |
29 | } |
30 | |
31 | static int sclk_div_maxval(struct meson_sclk_div_data *sclk) |
32 | { |
33 | return (1 << sclk->div.width) - 1; |
34 | } |
35 | |
36 | static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) |
37 | { |
38 | return sclk_div_maxval(sclk) + 1; |
39 | } |
40 | |
41 | static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate, |
42 | unsigned long prate, int maxdiv) |
43 | { |
44 | int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate); |
45 | |
46 | return clamp(div, 2, maxdiv); |
47 | } |
48 | |
49 | static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, |
50 | unsigned long *prate, |
51 | struct meson_sclk_div_data *sclk) |
52 | { |
53 | struct clk_hw *parent = clk_hw_get_parent(hw); |
54 | int bestdiv = 0, i; |
55 | unsigned long maxdiv, now, parent_now; |
56 | unsigned long best = 0, best_parent = 0; |
57 | |
58 | if (!rate) |
59 | rate = 1; |
60 | |
61 | maxdiv = sclk_div_maxdiv(sclk); |
62 | |
63 | if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) |
64 | return sclk_div_getdiv(hw, rate, prate: *prate, maxdiv); |
65 | |
66 | /* |
67 | * The maximum divider we can use without overflowing |
68 | * unsigned long in rate * i below |
69 | */ |
70 | maxdiv = min(ULONG_MAX / rate, maxdiv); |
71 | |
72 | for (i = 2; i <= maxdiv; i++) { |
73 | /* |
74 | * It's the most ideal case if the requested rate can be |
75 | * divided from parent clock without needing to change |
76 | * parent rate, so return the divider immediately. |
77 | */ |
78 | if (rate * i == *prate) |
79 | return i; |
80 | |
81 | parent_now = clk_hw_round_rate(hw: parent, rate: rate * i); |
82 | now = DIV_ROUND_UP_ULL((u64)parent_now, i); |
83 | |
84 | if (abs(rate - now) < abs(rate - best)) { |
85 | bestdiv = i; |
86 | best = now; |
87 | best_parent = parent_now; |
88 | } |
89 | } |
90 | |
91 | if (!bestdiv) |
92 | bestdiv = sclk_div_maxdiv(sclk); |
93 | else |
94 | *prate = best_parent; |
95 | |
96 | return bestdiv; |
97 | } |
98 | |
99 | static int sclk_div_determine_rate(struct clk_hw *hw, |
100 | struct clk_rate_request *req) |
101 | { |
102 | struct clk_regmap *clk = to_clk_regmap(hw); |
103 | struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); |
104 | int div; |
105 | |
106 | div = sclk_div_bestdiv(hw, rate: req->rate, prate: &req->best_parent_rate, sclk); |
107 | req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); |
108 | |
109 | return 0; |
110 | } |
111 | |
112 | static void sclk_apply_ratio(struct clk_regmap *clk, |
113 | struct meson_sclk_div_data *sclk) |
114 | { |
115 | unsigned int hi = DIV_ROUND_CLOSEST(sclk->cached_div * |
116 | sclk->cached_duty.num, |
117 | sclk->cached_duty.den); |
118 | |
119 | if (hi) |
120 | hi -= 1; |
121 | |
122 | meson_parm_write(map: clk->map, p: &sclk->hi, val: hi); |
123 | } |
124 | |
125 | static int sclk_div_set_duty_cycle(struct clk_hw *hw, |
126 | struct clk_duty *duty) |
127 | { |
128 | struct clk_regmap *clk = to_clk_regmap(hw); |
129 | struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); |
130 | |
131 | if (MESON_PARM_APPLICABLE(&sclk->hi)) { |
132 | memcpy(&sclk->cached_duty, duty, sizeof(*duty)); |
133 | sclk_apply_ratio(clk, sclk); |
134 | } |
135 | |
136 | return 0; |
137 | } |
138 | |
139 | static int sclk_div_get_duty_cycle(struct clk_hw *hw, |
140 | struct clk_duty *duty) |
141 | { |
142 | struct clk_regmap *clk = to_clk_regmap(hw); |
143 | struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); |
144 | int hi; |
145 | |
146 | if (!MESON_PARM_APPLICABLE(&sclk->hi)) { |
147 | duty->num = 1; |
148 | duty->den = 2; |
149 | return 0; |
150 | } |
151 | |
152 | hi = meson_parm_read(map: clk->map, p: &sclk->hi); |
153 | duty->num = hi + 1; |
154 | duty->den = sclk->cached_div; |
155 | return 0; |
156 | } |
157 | |
158 | static void sclk_apply_divider(struct clk_regmap *clk, |
159 | struct meson_sclk_div_data *sclk) |
160 | { |
161 | if (MESON_PARM_APPLICABLE(&sclk->hi)) |
162 | sclk_apply_ratio(clk, sclk); |
163 | |
164 | meson_parm_write(map: clk->map, p: &sclk->div, val: sclk->cached_div - 1); |
165 | } |
166 | |
167 | static int sclk_div_set_rate(struct clk_hw *hw, unsigned long rate, |
168 | unsigned long prate) |
169 | { |
170 | struct clk_regmap *clk = to_clk_regmap(hw); |
171 | struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); |
172 | unsigned long maxdiv = sclk_div_maxdiv(sclk); |
173 | |
174 | sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv); |
175 | |
176 | if (clk_hw_is_enabled(hw)) |
177 | sclk_apply_divider(clk, sclk); |
178 | |
179 | return 0; |
180 | } |
181 | |
182 | static unsigned long sclk_div_recalc_rate(struct clk_hw *hw, |
183 | unsigned long prate) |
184 | { |
185 | struct clk_regmap *clk = to_clk_regmap(hw); |
186 | struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); |
187 | |
188 | return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div); |
189 | } |
190 | |
191 | static int sclk_div_enable(struct clk_hw *hw) |
192 | { |
193 | struct clk_regmap *clk = to_clk_regmap(hw); |
194 | struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); |
195 | |
196 | sclk_apply_divider(clk, sclk); |
197 | |
198 | return 0; |
199 | } |
200 | |
201 | static void sclk_div_disable(struct clk_hw *hw) |
202 | { |
203 | struct clk_regmap *clk = to_clk_regmap(hw); |
204 | struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); |
205 | |
206 | meson_parm_write(map: clk->map, p: &sclk->div, val: 0); |
207 | } |
208 | |
209 | static int sclk_div_is_enabled(struct clk_hw *hw) |
210 | { |
211 | struct clk_regmap *clk = to_clk_regmap(hw); |
212 | struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); |
213 | |
214 | if (meson_parm_read(map: clk->map, p: &sclk->div)) |
215 | return 1; |
216 | |
217 | return 0; |
218 | } |
219 | |
220 | static int sclk_div_init(struct clk_hw *hw) |
221 | { |
222 | struct clk_regmap *clk = to_clk_regmap(hw); |
223 | struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); |
224 | unsigned int val; |
225 | |
226 | val = meson_parm_read(map: clk->map, p: &sclk->div); |
227 | |
228 | /* if the divider is initially disabled, assume max */ |
229 | if (!val) |
230 | sclk->cached_div = sclk_div_maxdiv(sclk); |
231 | else |
232 | sclk->cached_div = val + 1; |
233 | |
234 | sclk_div_get_duty_cycle(hw, duty: &sclk->cached_duty); |
235 | |
236 | return 0; |
237 | } |
238 | |
239 | const struct clk_ops meson_sclk_div_ops = { |
240 | .recalc_rate = sclk_div_recalc_rate, |
241 | .determine_rate = sclk_div_determine_rate, |
242 | .set_rate = sclk_div_set_rate, |
243 | .enable = sclk_div_enable, |
244 | .disable = sclk_div_disable, |
245 | .is_enabled = sclk_div_is_enabled, |
246 | .get_duty_cycle = sclk_div_get_duty_cycle, |
247 | .set_duty_cycle = sclk_div_set_duty_cycle, |
248 | .init = sclk_div_init, |
249 | }; |
250 | EXPORT_SYMBOL_GPL(meson_sclk_div_ops); |
251 | |
252 | MODULE_DESCRIPTION("Amlogic Sample divider driver" ); |
253 | MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>" ); |
254 | MODULE_LICENSE("GPL v2" ); |
255 | |