1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #include <linux/kernel.h> |
7 | #include <linux/bitops.h> |
8 | #include <linux/err.h> |
9 | #include <linux/platform_device.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> |
12 | #include <linux/clk-provider.h> |
13 | #include <linux/regmap.h> |
14 | #include <linux/reset-controller.h> |
15 | |
16 | #include <dt-bindings/clock/qcom,gcc-apq8084.h> |
17 | #include <dt-bindings/reset/qcom,gcc-apq8084.h> |
18 | |
19 | #include "common.h" |
20 | #include "clk-regmap.h" |
21 | #include "clk-pll.h" |
22 | #include "clk-rcg.h" |
23 | #include "clk-branch.h" |
24 | #include "reset.h" |
25 | #include "gdsc.h" |
26 | |
27 | enum { |
28 | P_XO, |
29 | P_GPLL0, |
30 | P_GPLL1, |
31 | P_GPLL4, |
32 | P_PCIE_0_1_PIPE_CLK, |
33 | P_SATA_ASIC0_CLK, |
34 | P_SATA_RX_CLK, |
35 | P_SLEEP_CLK, |
36 | }; |
37 | |
38 | static struct clk_pll gpll0 = { |
39 | .l_reg = 0x0004, |
40 | .m_reg = 0x0008, |
41 | .n_reg = 0x000c, |
42 | .config_reg = 0x0014, |
43 | .mode_reg = 0x0000, |
44 | .status_reg = 0x001c, |
45 | .status_bit = 17, |
46 | .clkr.hw.init = &(struct clk_init_data){ |
47 | .name = "gpll0" , |
48 | .parent_data = &(const struct clk_parent_data){ |
49 | .fw_name = "xo" , .name = "xo_board" , |
50 | }, |
51 | .num_parents = 1, |
52 | .ops = &clk_pll_ops, |
53 | }, |
54 | }; |
55 | |
56 | static struct clk_regmap gpll0_vote = { |
57 | .enable_reg = 0x1480, |
58 | .enable_mask = BIT(0), |
59 | .hw.init = &(struct clk_init_data){ |
60 | .name = "gpll0_vote" , |
61 | .parent_hws = (const struct clk_hw*[]){ |
62 | &gpll0.clkr.hw, |
63 | }, |
64 | .num_parents = 1, |
65 | .ops = &clk_pll_vote_ops, |
66 | }, |
67 | }; |
68 | |
69 | static struct clk_pll gpll1 = { |
70 | .l_reg = 0x0044, |
71 | .m_reg = 0x0048, |
72 | .n_reg = 0x004c, |
73 | .config_reg = 0x0054, |
74 | .mode_reg = 0x0040, |
75 | .status_reg = 0x005c, |
76 | .status_bit = 17, |
77 | .clkr.hw.init = &(struct clk_init_data){ |
78 | .name = "gpll1" , |
79 | .parent_data = &(const struct clk_parent_data){ |
80 | .fw_name = "xo" , .name = "xo_board" , |
81 | }, |
82 | .num_parents = 1, |
83 | .ops = &clk_pll_ops, |
84 | }, |
85 | }; |
86 | |
87 | static struct clk_regmap gpll1_vote = { |
88 | .enable_reg = 0x1480, |
89 | .enable_mask = BIT(1), |
90 | .hw.init = &(struct clk_init_data){ |
91 | .name = "gpll1_vote" , |
92 | .parent_hws = (const struct clk_hw*[]){ |
93 | &gpll1.clkr.hw, |
94 | }, |
95 | .num_parents = 1, |
96 | .ops = &clk_pll_vote_ops, |
97 | }, |
98 | }; |
99 | |
100 | static struct clk_pll gpll4 = { |
101 | .l_reg = 0x1dc4, |
102 | .m_reg = 0x1dc8, |
103 | .n_reg = 0x1dcc, |
104 | .config_reg = 0x1dd4, |
105 | .mode_reg = 0x1dc0, |
106 | .status_reg = 0x1ddc, |
107 | .status_bit = 17, |
108 | .clkr.hw.init = &(struct clk_init_data){ |
109 | .name = "gpll4" , |
110 | .parent_data = &(const struct clk_parent_data){ |
111 | .fw_name = "xo" , .name = "xo_board" , |
112 | }, |
113 | .num_parents = 1, |
114 | .ops = &clk_pll_ops, |
115 | }, |
116 | }; |
117 | |
118 | static struct clk_regmap gpll4_vote = { |
119 | .enable_reg = 0x1480, |
120 | .enable_mask = BIT(4), |
121 | .hw.init = &(struct clk_init_data){ |
122 | .name = "gpll4_vote" , |
123 | .parent_hws = (const struct clk_hw*[]){ |
124 | &gpll4.clkr.hw, |
125 | }, |
126 | .num_parents = 1, |
127 | .ops = &clk_pll_vote_ops, |
128 | }, |
129 | }; |
130 | |
131 | static const struct parent_map gcc_xo_gpll0_map[] = { |
132 | { P_XO, 0 }, |
133 | { P_GPLL0, 1 } |
134 | }; |
135 | |
136 | static const struct clk_parent_data gcc_xo_gpll0[] = { |
137 | { .fw_name = "xo" , .name = "xo_board" }, |
138 | { .hw = &gpll0_vote.hw }, |
139 | }; |
140 | |
141 | static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { |
142 | { P_XO, 0 }, |
143 | { P_GPLL0, 1 }, |
144 | { P_GPLL4, 5 } |
145 | }; |
146 | |
147 | static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { |
148 | { .fw_name = "xo" , .name = "xo_board" }, |
149 | { .hw = &gpll0_vote.hw }, |
150 | { .hw = &gpll4_vote.hw }, |
151 | }; |
152 | |
153 | static const struct parent_map gcc_xo_sata_asic0_map[] = { |
154 | { P_XO, 0 }, |
155 | { P_SATA_ASIC0_CLK, 2 } |
156 | }; |
157 | |
158 | static const struct clk_parent_data gcc_xo_sata_asic0[] = { |
159 | { .fw_name = "xo" , .name = "xo_board" }, |
160 | { .fw_name = "sata_asic0_clk" , .name = "sata_asic0_clk" }, |
161 | }; |
162 | |
163 | static const struct parent_map gcc_xo_sata_rx_map[] = { |
164 | { P_XO, 0 }, |
165 | { P_SATA_RX_CLK, 2} |
166 | }; |
167 | |
168 | static const struct clk_parent_data gcc_xo_sata_rx[] = { |
169 | { .fw_name = "xo" , .name = "xo_board" }, |
170 | { .fw_name = "sata_rx_clk" , .name = "sata_rx_clk" }, |
171 | }; |
172 | |
173 | static const struct parent_map gcc_xo_pcie_map[] = { |
174 | { P_XO, 0 }, |
175 | { P_PCIE_0_1_PIPE_CLK, 2 } |
176 | }; |
177 | |
178 | static const struct clk_parent_data gcc_xo_pcie[] = { |
179 | { .fw_name = "xo" , .name = "xo_board" }, |
180 | { .fw_name = "pcie_pipe" , .name = "pcie_pipe" }, |
181 | }; |
182 | |
183 | static const struct parent_map gcc_xo_pcie_sleep_map[] = { |
184 | { P_XO, 0 }, |
185 | { P_SLEEP_CLK, 6 } |
186 | }; |
187 | |
188 | static const struct clk_parent_data gcc_xo_pcie_sleep[] = { |
189 | { .fw_name = "xo" , .name = "xo_board" }, |
190 | { .fw_name = "sleep_clk" , .name = "sleep_clk" }, |
191 | }; |
192 | |
193 | static struct clk_rcg2 config_noc_clk_src = { |
194 | .cmd_rcgr = 0x0150, |
195 | .hid_width = 5, |
196 | .parent_map = gcc_xo_gpll0_map, |
197 | .clkr.hw.init = &(struct clk_init_data){ |
198 | .name = "config_noc_clk_src" , |
199 | .parent_data = gcc_xo_gpll0, |
200 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
201 | .ops = &clk_rcg2_ops, |
202 | }, |
203 | }; |
204 | |
205 | static struct clk_rcg2 periph_noc_clk_src = { |
206 | .cmd_rcgr = 0x0190, |
207 | .hid_width = 5, |
208 | .parent_map = gcc_xo_gpll0_map, |
209 | .clkr.hw.init = &(struct clk_init_data){ |
210 | .name = "periph_noc_clk_src" , |
211 | .parent_data = gcc_xo_gpll0, |
212 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
213 | .ops = &clk_rcg2_ops, |
214 | }, |
215 | }; |
216 | |
217 | static struct clk_rcg2 system_noc_clk_src = { |
218 | .cmd_rcgr = 0x0120, |
219 | .hid_width = 5, |
220 | .parent_map = gcc_xo_gpll0_map, |
221 | .clkr.hw.init = &(struct clk_init_data){ |
222 | .name = "system_noc_clk_src" , |
223 | .parent_data = gcc_xo_gpll0, |
224 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
225 | .ops = &clk_rcg2_ops, |
226 | }, |
227 | }; |
228 | |
229 | static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = { |
230 | F(100000000, P_GPLL0, 6, 0, 0), |
231 | F(200000000, P_GPLL0, 3, 0, 0), |
232 | F(240000000, P_GPLL0, 2.5, 0, 0), |
233 | { } |
234 | }; |
235 | |
236 | static struct clk_rcg2 ufs_axi_clk_src = { |
237 | .cmd_rcgr = 0x1d64, |
238 | .mnd_width = 8, |
239 | .hid_width = 5, |
240 | .parent_map = gcc_xo_gpll0_map, |
241 | .freq_tbl = ftbl_gcc_ufs_axi_clk, |
242 | .clkr.hw.init = &(struct clk_init_data){ |
243 | .name = "ufs_axi_clk_src" , |
244 | .parent_data = gcc_xo_gpll0, |
245 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
246 | .ops = &clk_rcg2_ops, |
247 | }, |
248 | }; |
249 | |
250 | static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { |
251 | F(125000000, P_GPLL0, 1, 5, 24), |
252 | { } |
253 | }; |
254 | |
255 | static struct clk_rcg2 usb30_master_clk_src = { |
256 | .cmd_rcgr = 0x03d4, |
257 | .mnd_width = 8, |
258 | .hid_width = 5, |
259 | .parent_map = gcc_xo_gpll0_map, |
260 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
261 | .clkr.hw.init = &(struct clk_init_data){ |
262 | .name = "usb30_master_clk_src" , |
263 | .parent_data = gcc_xo_gpll0, |
264 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
265 | .ops = &clk_rcg2_ops, |
266 | }, |
267 | }; |
268 | |
269 | static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = { |
270 | F(125000000, P_GPLL0, 1, 5, 24), |
271 | { } |
272 | }; |
273 | |
274 | static struct clk_rcg2 usb30_sec_master_clk_src = { |
275 | .cmd_rcgr = 0x1bd4, |
276 | .mnd_width = 8, |
277 | .hid_width = 5, |
278 | .parent_map = gcc_xo_gpll0_map, |
279 | .freq_tbl = ftbl_gcc_usb30_sec_master_clk, |
280 | .clkr.hw.init = &(struct clk_init_data){ |
281 | .name = "usb30_sec_master_clk_src" , |
282 | .parent_data = gcc_xo_gpll0, |
283 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
284 | .ops = &clk_rcg2_ops, |
285 | }, |
286 | }; |
287 | |
288 | static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = { |
289 | F(125000000, P_GPLL0, 1, 5, 24), |
290 | { } |
291 | }; |
292 | |
293 | static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = { |
294 | .cmd_rcgr = 0x1be8, |
295 | .hid_width = 5, |
296 | .parent_map = gcc_xo_gpll0_map, |
297 | .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk, |
298 | .clkr.hw.init = &(struct clk_init_data){ |
299 | .name = "usb30_sec_mock_utmi_clk_src" , |
300 | .parent_data = gcc_xo_gpll0, |
301 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
302 | .ops = &clk_rcg2_ops, |
303 | }, |
304 | }; |
305 | |
306 | static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { |
307 | .halt_reg = 0x1bd0, |
308 | .clkr = { |
309 | .enable_reg = 0x1bd0, |
310 | .enable_mask = BIT(0), |
311 | .hw.init = &(struct clk_init_data){ |
312 | .name = "gcc_usb30_sec_mock_utmi_clk" , |
313 | .parent_hws = (const struct clk_hw*[]){ |
314 | &usb30_sec_mock_utmi_clk_src.clkr.hw, |
315 | }, |
316 | .num_parents = 1, |
317 | .flags = CLK_SET_RATE_PARENT, |
318 | .ops = &clk_branch2_ops, |
319 | }, |
320 | }, |
321 | }; |
322 | |
323 | static struct clk_branch gcc_usb30_sec_sleep_clk = { |
324 | .halt_reg = 0x1bcc, |
325 | .clkr = { |
326 | .enable_reg = 0x1bcc, |
327 | .enable_mask = BIT(0), |
328 | .hw.init = &(struct clk_init_data){ |
329 | .name = "gcc_usb30_sec_sleep_clk" , |
330 | .parent_data = &(const struct clk_parent_data){ |
331 | .fw_name = "sleep_clk" , .name = "sleep_clk" , |
332 | }, |
333 | .num_parents = 1, |
334 | .flags = CLK_SET_RATE_PARENT, |
335 | .ops = &clk_branch2_ops, |
336 | }, |
337 | }, |
338 | }; |
339 | |
340 | static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = { |
341 | F(19200000, P_XO, 1, 0, 0), |
342 | F(50000000, P_GPLL0, 12, 0, 0), |
343 | { } |
344 | }; |
345 | |
346 | static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { |
347 | .cmd_rcgr = 0x0660, |
348 | .hid_width = 5, |
349 | .parent_map = gcc_xo_gpll0_map, |
350 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
351 | .clkr.hw.init = &(struct clk_init_data){ |
352 | .name = "blsp1_qup1_i2c_apps_clk_src" , |
353 | .parent_data = gcc_xo_gpll0, |
354 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
355 | .ops = &clk_rcg2_ops, |
356 | }, |
357 | }; |
358 | |
359 | static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = { |
360 | F(960000, P_XO, 10, 1, 2), |
361 | F(4800000, P_XO, 4, 0, 0), |
362 | F(9600000, P_XO, 2, 0, 0), |
363 | F(15000000, P_GPLL0, 10, 1, 4), |
364 | F(19200000, P_XO, 1, 0, 0), |
365 | F(25000000, P_GPLL0, 12, 1, 2), |
366 | F(50000000, P_GPLL0, 12, 0, 0), |
367 | { } |
368 | }; |
369 | |
370 | static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { |
371 | .cmd_rcgr = 0x064c, |
372 | .mnd_width = 8, |
373 | .hid_width = 5, |
374 | .parent_map = gcc_xo_gpll0_map, |
375 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
376 | .clkr.hw.init = &(struct clk_init_data){ |
377 | .name = "blsp1_qup1_spi_apps_clk_src" , |
378 | .parent_data = gcc_xo_gpll0, |
379 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
380 | .ops = &clk_rcg2_ops, |
381 | }, |
382 | }; |
383 | |
384 | static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { |
385 | .cmd_rcgr = 0x06e0, |
386 | .hid_width = 5, |
387 | .parent_map = gcc_xo_gpll0_map, |
388 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
389 | .clkr.hw.init = &(struct clk_init_data){ |
390 | .name = "blsp1_qup2_i2c_apps_clk_src" , |
391 | .parent_data = gcc_xo_gpll0, |
392 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
393 | .ops = &clk_rcg2_ops, |
394 | }, |
395 | }; |
396 | |
397 | static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { |
398 | .cmd_rcgr = 0x06cc, |
399 | .mnd_width = 8, |
400 | .hid_width = 5, |
401 | .parent_map = gcc_xo_gpll0_map, |
402 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
403 | .clkr.hw.init = &(struct clk_init_data){ |
404 | .name = "blsp1_qup2_spi_apps_clk_src" , |
405 | .parent_data = gcc_xo_gpll0, |
406 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
407 | .ops = &clk_rcg2_ops, |
408 | }, |
409 | }; |
410 | |
411 | static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { |
412 | .cmd_rcgr = 0x0760, |
413 | .hid_width = 5, |
414 | .parent_map = gcc_xo_gpll0_map, |
415 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
416 | .clkr.hw.init = &(struct clk_init_data){ |
417 | .name = "blsp1_qup3_i2c_apps_clk_src" , |
418 | .parent_data = gcc_xo_gpll0, |
419 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
420 | .ops = &clk_rcg2_ops, |
421 | }, |
422 | }; |
423 | |
424 | static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { |
425 | .cmd_rcgr = 0x074c, |
426 | .mnd_width = 8, |
427 | .hid_width = 5, |
428 | .parent_map = gcc_xo_gpll0_map, |
429 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
430 | .clkr.hw.init = &(struct clk_init_data){ |
431 | .name = "blsp1_qup3_spi_apps_clk_src" , |
432 | .parent_data = gcc_xo_gpll0, |
433 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
434 | .ops = &clk_rcg2_ops, |
435 | }, |
436 | }; |
437 | |
438 | static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { |
439 | .cmd_rcgr = 0x07e0, |
440 | .hid_width = 5, |
441 | .parent_map = gcc_xo_gpll0_map, |
442 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
443 | .clkr.hw.init = &(struct clk_init_data){ |
444 | .name = "blsp1_qup4_i2c_apps_clk_src" , |
445 | .parent_data = gcc_xo_gpll0, |
446 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
447 | .ops = &clk_rcg2_ops, |
448 | }, |
449 | }; |
450 | |
451 | static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { |
452 | .cmd_rcgr = 0x07cc, |
453 | .mnd_width = 8, |
454 | .hid_width = 5, |
455 | .parent_map = gcc_xo_gpll0_map, |
456 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
457 | .clkr.hw.init = &(struct clk_init_data){ |
458 | .name = "blsp1_qup4_spi_apps_clk_src" , |
459 | .parent_data = gcc_xo_gpll0, |
460 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
461 | .ops = &clk_rcg2_ops, |
462 | }, |
463 | }; |
464 | |
465 | static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { |
466 | .cmd_rcgr = 0x0860, |
467 | .hid_width = 5, |
468 | .parent_map = gcc_xo_gpll0_map, |
469 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
470 | .clkr.hw.init = &(struct clk_init_data){ |
471 | .name = "blsp1_qup5_i2c_apps_clk_src" , |
472 | .parent_data = gcc_xo_gpll0, |
473 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
474 | .ops = &clk_rcg2_ops, |
475 | }, |
476 | }; |
477 | |
478 | static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { |
479 | .cmd_rcgr = 0x084c, |
480 | .mnd_width = 8, |
481 | .hid_width = 5, |
482 | .parent_map = gcc_xo_gpll0_map, |
483 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
484 | .clkr.hw.init = &(struct clk_init_data){ |
485 | .name = "blsp1_qup5_spi_apps_clk_src" , |
486 | .parent_data = gcc_xo_gpll0, |
487 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
488 | .ops = &clk_rcg2_ops, |
489 | }, |
490 | }; |
491 | |
492 | static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { |
493 | .cmd_rcgr = 0x08e0, |
494 | .hid_width = 5, |
495 | .parent_map = gcc_xo_gpll0_map, |
496 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
497 | .clkr.hw.init = &(struct clk_init_data){ |
498 | .name = "blsp1_qup6_i2c_apps_clk_src" , |
499 | .parent_data = gcc_xo_gpll0, |
500 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
501 | .ops = &clk_rcg2_ops, |
502 | }, |
503 | }; |
504 | |
505 | static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { |
506 | .cmd_rcgr = 0x08cc, |
507 | .mnd_width = 8, |
508 | .hid_width = 5, |
509 | .parent_map = gcc_xo_gpll0_map, |
510 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
511 | .clkr.hw.init = &(struct clk_init_data){ |
512 | .name = "blsp1_qup6_spi_apps_clk_src" , |
513 | .parent_data = gcc_xo_gpll0, |
514 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
515 | .ops = &clk_rcg2_ops, |
516 | }, |
517 | }; |
518 | |
519 | static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = { |
520 | F(3686400, P_GPLL0, 1, 96, 15625), |
521 | F(7372800, P_GPLL0, 1, 192, 15625), |
522 | F(14745600, P_GPLL0, 1, 384, 15625), |
523 | F(16000000, P_GPLL0, 5, 2, 15), |
524 | F(19200000, P_XO, 1, 0, 0), |
525 | F(24000000, P_GPLL0, 5, 1, 5), |
526 | F(32000000, P_GPLL0, 1, 4, 75), |
527 | F(40000000, P_GPLL0, 15, 0, 0), |
528 | F(46400000, P_GPLL0, 1, 29, 375), |
529 | F(48000000, P_GPLL0, 12.5, 0, 0), |
530 | F(51200000, P_GPLL0, 1, 32, 375), |
531 | F(56000000, P_GPLL0, 1, 7, 75), |
532 | F(58982400, P_GPLL0, 1, 1536, 15625), |
533 | F(60000000, P_GPLL0, 10, 0, 0), |
534 | F(63160000, P_GPLL0, 9.5, 0, 0), |
535 | { } |
536 | }; |
537 | |
538 | static struct clk_rcg2 blsp1_uart1_apps_clk_src = { |
539 | .cmd_rcgr = 0x068c, |
540 | .mnd_width = 16, |
541 | .hid_width = 5, |
542 | .parent_map = gcc_xo_gpll0_map, |
543 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
544 | .clkr.hw.init = &(struct clk_init_data){ |
545 | .name = "blsp1_uart1_apps_clk_src" , |
546 | .parent_data = gcc_xo_gpll0, |
547 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
548 | .ops = &clk_rcg2_ops, |
549 | }, |
550 | }; |
551 | |
552 | static struct clk_rcg2 blsp1_uart2_apps_clk_src = { |
553 | .cmd_rcgr = 0x070c, |
554 | .mnd_width = 16, |
555 | .hid_width = 5, |
556 | .parent_map = gcc_xo_gpll0_map, |
557 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
558 | .clkr.hw.init = &(struct clk_init_data){ |
559 | .name = "blsp1_uart2_apps_clk_src" , |
560 | .parent_data = gcc_xo_gpll0, |
561 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
562 | .ops = &clk_rcg2_ops, |
563 | }, |
564 | }; |
565 | |
566 | static struct clk_rcg2 blsp1_uart3_apps_clk_src = { |
567 | .cmd_rcgr = 0x078c, |
568 | .mnd_width = 16, |
569 | .hid_width = 5, |
570 | .parent_map = gcc_xo_gpll0_map, |
571 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
572 | .clkr.hw.init = &(struct clk_init_data){ |
573 | .name = "blsp1_uart3_apps_clk_src" , |
574 | .parent_data = gcc_xo_gpll0, |
575 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
576 | .ops = &clk_rcg2_ops, |
577 | }, |
578 | }; |
579 | |
580 | static struct clk_rcg2 blsp1_uart4_apps_clk_src = { |
581 | .cmd_rcgr = 0x080c, |
582 | .mnd_width = 16, |
583 | .hid_width = 5, |
584 | .parent_map = gcc_xo_gpll0_map, |
585 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
586 | .clkr.hw.init = &(struct clk_init_data){ |
587 | .name = "blsp1_uart4_apps_clk_src" , |
588 | .parent_data = gcc_xo_gpll0, |
589 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
590 | .ops = &clk_rcg2_ops, |
591 | }, |
592 | }; |
593 | |
594 | static struct clk_rcg2 blsp1_uart5_apps_clk_src = { |
595 | .cmd_rcgr = 0x088c, |
596 | .mnd_width = 16, |
597 | .hid_width = 5, |
598 | .parent_map = gcc_xo_gpll0_map, |
599 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
600 | .clkr.hw.init = &(struct clk_init_data){ |
601 | .name = "blsp1_uart5_apps_clk_src" , |
602 | .parent_data = gcc_xo_gpll0, |
603 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
604 | .ops = &clk_rcg2_ops, |
605 | }, |
606 | }; |
607 | |
608 | static struct clk_rcg2 blsp1_uart6_apps_clk_src = { |
609 | .cmd_rcgr = 0x090c, |
610 | .mnd_width = 16, |
611 | .hid_width = 5, |
612 | .parent_map = gcc_xo_gpll0_map, |
613 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
614 | .clkr.hw.init = &(struct clk_init_data){ |
615 | .name = "blsp1_uart6_apps_clk_src" , |
616 | .parent_data = gcc_xo_gpll0, |
617 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
618 | .ops = &clk_rcg2_ops, |
619 | }, |
620 | }; |
621 | |
622 | static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { |
623 | .cmd_rcgr = 0x09a0, |
624 | .hid_width = 5, |
625 | .parent_map = gcc_xo_gpll0_map, |
626 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
627 | .clkr.hw.init = &(struct clk_init_data){ |
628 | .name = "blsp2_qup1_i2c_apps_clk_src" , |
629 | .parent_data = gcc_xo_gpll0, |
630 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
631 | .ops = &clk_rcg2_ops, |
632 | }, |
633 | }; |
634 | |
635 | static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { |
636 | .cmd_rcgr = 0x098c, |
637 | .mnd_width = 8, |
638 | .hid_width = 5, |
639 | .parent_map = gcc_xo_gpll0_map, |
640 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
641 | .clkr.hw.init = &(struct clk_init_data){ |
642 | .name = "blsp2_qup1_spi_apps_clk_src" , |
643 | .parent_data = gcc_xo_gpll0, |
644 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
645 | .ops = &clk_rcg2_ops, |
646 | }, |
647 | }; |
648 | |
649 | static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { |
650 | .cmd_rcgr = 0x0a20, |
651 | .hid_width = 5, |
652 | .parent_map = gcc_xo_gpll0_map, |
653 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
654 | .clkr.hw.init = &(struct clk_init_data){ |
655 | .name = "blsp2_qup2_i2c_apps_clk_src" , |
656 | .parent_data = gcc_xo_gpll0, |
657 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
658 | .ops = &clk_rcg2_ops, |
659 | }, |
660 | }; |
661 | |
662 | static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { |
663 | .cmd_rcgr = 0x0a0c, |
664 | .mnd_width = 8, |
665 | .hid_width = 5, |
666 | .parent_map = gcc_xo_gpll0_map, |
667 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
668 | .clkr.hw.init = &(struct clk_init_data){ |
669 | .name = "blsp2_qup2_spi_apps_clk_src" , |
670 | .parent_data = gcc_xo_gpll0, |
671 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
672 | .ops = &clk_rcg2_ops, |
673 | }, |
674 | }; |
675 | |
676 | static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { |
677 | .cmd_rcgr = 0x0aa0, |
678 | .hid_width = 5, |
679 | .parent_map = gcc_xo_gpll0_map, |
680 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
681 | .clkr.hw.init = &(struct clk_init_data){ |
682 | .name = "blsp2_qup3_i2c_apps_clk_src" , |
683 | .parent_data = gcc_xo_gpll0, |
684 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
685 | .ops = &clk_rcg2_ops, |
686 | }, |
687 | }; |
688 | |
689 | static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { |
690 | .cmd_rcgr = 0x0a8c, |
691 | .mnd_width = 8, |
692 | .hid_width = 5, |
693 | .parent_map = gcc_xo_gpll0_map, |
694 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
695 | .clkr.hw.init = &(struct clk_init_data){ |
696 | .name = "blsp2_qup3_spi_apps_clk_src" , |
697 | .parent_data = gcc_xo_gpll0, |
698 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
699 | .ops = &clk_rcg2_ops, |
700 | }, |
701 | }; |
702 | |
703 | static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { |
704 | .cmd_rcgr = 0x0b20, |
705 | .hid_width = 5, |
706 | .parent_map = gcc_xo_gpll0_map, |
707 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
708 | .clkr.hw.init = &(struct clk_init_data){ |
709 | .name = "blsp2_qup4_i2c_apps_clk_src" , |
710 | .parent_data = gcc_xo_gpll0, |
711 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
712 | .ops = &clk_rcg2_ops, |
713 | }, |
714 | }; |
715 | |
716 | static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { |
717 | .cmd_rcgr = 0x0b0c, |
718 | .mnd_width = 8, |
719 | .hid_width = 5, |
720 | .parent_map = gcc_xo_gpll0_map, |
721 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
722 | .clkr.hw.init = &(struct clk_init_data){ |
723 | .name = "blsp2_qup4_spi_apps_clk_src" , |
724 | .parent_data = gcc_xo_gpll0, |
725 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
726 | .ops = &clk_rcg2_ops, |
727 | }, |
728 | }; |
729 | |
730 | static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { |
731 | .cmd_rcgr = 0x0ba0, |
732 | .hid_width = 5, |
733 | .parent_map = gcc_xo_gpll0_map, |
734 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
735 | .clkr.hw.init = &(struct clk_init_data){ |
736 | .name = "blsp2_qup5_i2c_apps_clk_src" , |
737 | .parent_data = gcc_xo_gpll0, |
738 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
739 | .ops = &clk_rcg2_ops, |
740 | }, |
741 | }; |
742 | |
743 | static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { |
744 | .cmd_rcgr = 0x0b8c, |
745 | .mnd_width = 8, |
746 | .hid_width = 5, |
747 | .parent_map = gcc_xo_gpll0_map, |
748 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
749 | .clkr.hw.init = &(struct clk_init_data){ |
750 | .name = "blsp2_qup5_spi_apps_clk_src" , |
751 | .parent_data = gcc_xo_gpll0, |
752 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
753 | .ops = &clk_rcg2_ops, |
754 | }, |
755 | }; |
756 | |
757 | static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { |
758 | .cmd_rcgr = 0x0c20, |
759 | .hid_width = 5, |
760 | .parent_map = gcc_xo_gpll0_map, |
761 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, |
762 | .clkr.hw.init = &(struct clk_init_data){ |
763 | .name = "blsp2_qup6_i2c_apps_clk_src" , |
764 | .parent_data = gcc_xo_gpll0, |
765 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
766 | .ops = &clk_rcg2_ops, |
767 | }, |
768 | }; |
769 | |
770 | static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { |
771 | .cmd_rcgr = 0x0c0c, |
772 | .mnd_width = 8, |
773 | .hid_width = 5, |
774 | .parent_map = gcc_xo_gpll0_map, |
775 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, |
776 | .clkr.hw.init = &(struct clk_init_data){ |
777 | .name = "blsp2_qup6_spi_apps_clk_src" , |
778 | .parent_data = gcc_xo_gpll0, |
779 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
780 | .ops = &clk_rcg2_ops, |
781 | }, |
782 | }; |
783 | |
784 | static struct clk_rcg2 blsp2_uart1_apps_clk_src = { |
785 | .cmd_rcgr = 0x09cc, |
786 | .mnd_width = 16, |
787 | .hid_width = 5, |
788 | .parent_map = gcc_xo_gpll0_map, |
789 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
790 | .clkr.hw.init = &(struct clk_init_data){ |
791 | .name = "blsp2_uart1_apps_clk_src" , |
792 | .parent_data = gcc_xo_gpll0, |
793 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
794 | .ops = &clk_rcg2_ops, |
795 | }, |
796 | }; |
797 | |
798 | static struct clk_rcg2 blsp2_uart2_apps_clk_src = { |
799 | .cmd_rcgr = 0x0a4c, |
800 | .mnd_width = 16, |
801 | .hid_width = 5, |
802 | .parent_map = gcc_xo_gpll0_map, |
803 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
804 | .clkr.hw.init = &(struct clk_init_data){ |
805 | .name = "blsp2_uart2_apps_clk_src" , |
806 | .parent_data = gcc_xo_gpll0, |
807 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
808 | .ops = &clk_rcg2_ops, |
809 | }, |
810 | }; |
811 | |
812 | static struct clk_rcg2 blsp2_uart3_apps_clk_src = { |
813 | .cmd_rcgr = 0x0acc, |
814 | .mnd_width = 16, |
815 | .hid_width = 5, |
816 | .parent_map = gcc_xo_gpll0_map, |
817 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
818 | .clkr.hw.init = &(struct clk_init_data){ |
819 | .name = "blsp2_uart3_apps_clk_src" , |
820 | .parent_data = gcc_xo_gpll0, |
821 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
822 | .ops = &clk_rcg2_ops, |
823 | }, |
824 | }; |
825 | |
826 | static struct clk_rcg2 blsp2_uart4_apps_clk_src = { |
827 | .cmd_rcgr = 0x0b4c, |
828 | .mnd_width = 16, |
829 | .hid_width = 5, |
830 | .parent_map = gcc_xo_gpll0_map, |
831 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
832 | .clkr.hw.init = &(struct clk_init_data){ |
833 | .name = "blsp2_uart4_apps_clk_src" , |
834 | .parent_data = gcc_xo_gpll0, |
835 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
836 | .ops = &clk_rcg2_ops, |
837 | }, |
838 | }; |
839 | |
840 | static struct clk_rcg2 blsp2_uart5_apps_clk_src = { |
841 | .cmd_rcgr = 0x0bcc, |
842 | .mnd_width = 16, |
843 | .hid_width = 5, |
844 | .parent_map = gcc_xo_gpll0_map, |
845 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
846 | .clkr.hw.init = &(struct clk_init_data){ |
847 | .name = "blsp2_uart5_apps_clk_src" , |
848 | .parent_data = gcc_xo_gpll0, |
849 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
850 | .ops = &clk_rcg2_ops, |
851 | }, |
852 | }; |
853 | |
854 | static struct clk_rcg2 blsp2_uart6_apps_clk_src = { |
855 | .cmd_rcgr = 0x0c4c, |
856 | .mnd_width = 16, |
857 | .hid_width = 5, |
858 | .parent_map = gcc_xo_gpll0_map, |
859 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
860 | .clkr.hw.init = &(struct clk_init_data){ |
861 | .name = "blsp2_uart6_apps_clk_src" , |
862 | .parent_data = gcc_xo_gpll0, |
863 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
864 | .ops = &clk_rcg2_ops, |
865 | }, |
866 | }; |
867 | |
868 | static const struct freq_tbl ftbl_gcc_ce1_clk[] = { |
869 | F(50000000, P_GPLL0, 12, 0, 0), |
870 | F(85710000, P_GPLL0, 7, 0, 0), |
871 | F(100000000, P_GPLL0, 6, 0, 0), |
872 | F(171430000, P_GPLL0, 3.5, 0, 0), |
873 | { } |
874 | }; |
875 | |
876 | static struct clk_rcg2 ce1_clk_src = { |
877 | .cmd_rcgr = 0x1050, |
878 | .hid_width = 5, |
879 | .parent_map = gcc_xo_gpll0_map, |
880 | .freq_tbl = ftbl_gcc_ce1_clk, |
881 | .clkr.hw.init = &(struct clk_init_data){ |
882 | .name = "ce1_clk_src" , |
883 | .parent_data = gcc_xo_gpll0, |
884 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
885 | .ops = &clk_rcg2_ops, |
886 | }, |
887 | }; |
888 | |
889 | static const struct freq_tbl ftbl_gcc_ce2_clk[] = { |
890 | F(50000000, P_GPLL0, 12, 0, 0), |
891 | F(85710000, P_GPLL0, 7, 0, 0), |
892 | F(100000000, P_GPLL0, 6, 0, 0), |
893 | F(171430000, P_GPLL0, 3.5, 0, 0), |
894 | { } |
895 | }; |
896 | |
897 | static struct clk_rcg2 ce2_clk_src = { |
898 | .cmd_rcgr = 0x1090, |
899 | .hid_width = 5, |
900 | .parent_map = gcc_xo_gpll0_map, |
901 | .freq_tbl = ftbl_gcc_ce2_clk, |
902 | .clkr.hw.init = &(struct clk_init_data){ |
903 | .name = "ce2_clk_src" , |
904 | .parent_data = gcc_xo_gpll0, |
905 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
906 | .ops = &clk_rcg2_ops, |
907 | }, |
908 | }; |
909 | |
910 | static const struct freq_tbl ftbl_gcc_ce3_clk[] = { |
911 | F(50000000, P_GPLL0, 12, 0, 0), |
912 | F(85710000, P_GPLL0, 7, 0, 0), |
913 | F(100000000, P_GPLL0, 6, 0, 0), |
914 | F(171430000, P_GPLL0, 3.5, 0, 0), |
915 | { } |
916 | }; |
917 | |
918 | static struct clk_rcg2 ce3_clk_src = { |
919 | .cmd_rcgr = 0x1d10, |
920 | .hid_width = 5, |
921 | .parent_map = gcc_xo_gpll0_map, |
922 | .freq_tbl = ftbl_gcc_ce3_clk, |
923 | .clkr.hw.init = &(struct clk_init_data){ |
924 | .name = "ce3_clk_src" , |
925 | .parent_data = gcc_xo_gpll0, |
926 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
927 | .ops = &clk_rcg2_ops, |
928 | }, |
929 | }; |
930 | |
931 | static const struct freq_tbl ftbl_gcc_gp_clk[] = { |
932 | F(19200000, P_XO, 1, 0, 0), |
933 | F(100000000, P_GPLL0, 6, 0, 0), |
934 | F(200000000, P_GPLL0, 3, 0, 0), |
935 | { } |
936 | }; |
937 | |
938 | static struct clk_rcg2 gp1_clk_src = { |
939 | .cmd_rcgr = 0x1904, |
940 | .mnd_width = 8, |
941 | .hid_width = 5, |
942 | .parent_map = gcc_xo_gpll0_map, |
943 | .freq_tbl = ftbl_gcc_gp_clk, |
944 | .clkr.hw.init = &(struct clk_init_data){ |
945 | .name = "gp1_clk_src" , |
946 | .parent_data = gcc_xo_gpll0, |
947 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
948 | .ops = &clk_rcg2_ops, |
949 | }, |
950 | }; |
951 | |
952 | static struct clk_rcg2 gp2_clk_src = { |
953 | .cmd_rcgr = 0x1944, |
954 | .mnd_width = 8, |
955 | .hid_width = 5, |
956 | .parent_map = gcc_xo_gpll0_map, |
957 | .freq_tbl = ftbl_gcc_gp_clk, |
958 | .clkr.hw.init = &(struct clk_init_data){ |
959 | .name = "gp2_clk_src" , |
960 | .parent_data = gcc_xo_gpll0, |
961 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
962 | .ops = &clk_rcg2_ops, |
963 | }, |
964 | }; |
965 | |
966 | static struct clk_rcg2 gp3_clk_src = { |
967 | .cmd_rcgr = 0x1984, |
968 | .mnd_width = 8, |
969 | .hid_width = 5, |
970 | .parent_map = gcc_xo_gpll0_map, |
971 | .freq_tbl = ftbl_gcc_gp_clk, |
972 | .clkr.hw.init = &(struct clk_init_data){ |
973 | .name = "gp3_clk_src" , |
974 | .parent_data = gcc_xo_gpll0, |
975 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
976 | .ops = &clk_rcg2_ops, |
977 | }, |
978 | }; |
979 | |
980 | static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = { |
981 | F(1010000, P_XO, 1, 1, 19), |
982 | { } |
983 | }; |
984 | |
985 | static struct clk_rcg2 pcie_0_aux_clk_src = { |
986 | .cmd_rcgr = 0x1b2c, |
987 | .mnd_width = 16, |
988 | .hid_width = 5, |
989 | .parent_map = gcc_xo_pcie_sleep_map, |
990 | .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk, |
991 | .clkr.hw.init = &(struct clk_init_data){ |
992 | .name = "pcie_0_aux_clk_src" , |
993 | .parent_data = gcc_xo_pcie_sleep, |
994 | .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep), |
995 | .ops = &clk_rcg2_ops, |
996 | }, |
997 | }; |
998 | |
999 | static struct clk_rcg2 pcie_1_aux_clk_src = { |
1000 | .cmd_rcgr = 0x1bac, |
1001 | .mnd_width = 16, |
1002 | .hid_width = 5, |
1003 | .parent_map = gcc_xo_pcie_sleep_map, |
1004 | .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk, |
1005 | .clkr.hw.init = &(struct clk_init_data){ |
1006 | .name = "pcie_1_aux_clk_src" , |
1007 | .parent_data = gcc_xo_pcie_sleep, |
1008 | .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep), |
1009 | .ops = &clk_rcg2_ops, |
1010 | }, |
1011 | }; |
1012 | |
1013 | static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = { |
1014 | F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0), |
1015 | F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0), |
1016 | { } |
1017 | }; |
1018 | |
1019 | static struct clk_rcg2 pcie_0_pipe_clk_src = { |
1020 | .cmd_rcgr = 0x1b18, |
1021 | .hid_width = 5, |
1022 | .parent_map = gcc_xo_pcie_map, |
1023 | .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk, |
1024 | .clkr.hw.init = &(struct clk_init_data){ |
1025 | .name = "pcie_0_pipe_clk_src" , |
1026 | .parent_data = gcc_xo_pcie, |
1027 | .num_parents = ARRAY_SIZE(gcc_xo_pcie), |
1028 | .ops = &clk_rcg2_ops, |
1029 | }, |
1030 | }; |
1031 | |
1032 | static struct clk_rcg2 pcie_1_pipe_clk_src = { |
1033 | .cmd_rcgr = 0x1b98, |
1034 | .hid_width = 5, |
1035 | .parent_map = gcc_xo_pcie_map, |
1036 | .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk, |
1037 | .clkr.hw.init = &(struct clk_init_data){ |
1038 | .name = "pcie_1_pipe_clk_src" , |
1039 | .parent_data = gcc_xo_pcie, |
1040 | .num_parents = ARRAY_SIZE(gcc_xo_pcie), |
1041 | .ops = &clk_rcg2_ops, |
1042 | }, |
1043 | }; |
1044 | |
1045 | static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { |
1046 | F(60000000, P_GPLL0, 10, 0, 0), |
1047 | { } |
1048 | }; |
1049 | |
1050 | static struct clk_rcg2 pdm2_clk_src = { |
1051 | .cmd_rcgr = 0x0cd0, |
1052 | .hid_width = 5, |
1053 | .parent_map = gcc_xo_gpll0_map, |
1054 | .freq_tbl = ftbl_gcc_pdm2_clk, |
1055 | .clkr.hw.init = &(struct clk_init_data){ |
1056 | .name = "pdm2_clk_src" , |
1057 | .parent_data = gcc_xo_gpll0, |
1058 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1059 | .ops = &clk_rcg2_ops, |
1060 | }, |
1061 | }; |
1062 | |
1063 | static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = { |
1064 | F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0), |
1065 | F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0), |
1066 | F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0), |
1067 | { } |
1068 | }; |
1069 | |
1070 | static struct clk_rcg2 sata_asic0_clk_src = { |
1071 | .cmd_rcgr = 0x1c94, |
1072 | .hid_width = 5, |
1073 | .parent_map = gcc_xo_sata_asic0_map, |
1074 | .freq_tbl = ftbl_gcc_sata_asic0_clk, |
1075 | .clkr.hw.init = &(struct clk_init_data){ |
1076 | .name = "sata_asic0_clk_src" , |
1077 | .parent_data = gcc_xo_sata_asic0, |
1078 | .num_parents = ARRAY_SIZE(gcc_xo_sata_asic0), |
1079 | .ops = &clk_rcg2_ops, |
1080 | }, |
1081 | }; |
1082 | |
1083 | static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = { |
1084 | F(19200000, P_XO, 1, 0, 0), |
1085 | F(50000000, P_GPLL0, 12, 0, 0), |
1086 | F(100000000, P_GPLL0, 6, 0, 0), |
1087 | { } |
1088 | }; |
1089 | |
1090 | static struct clk_rcg2 sata_pmalive_clk_src = { |
1091 | .cmd_rcgr = 0x1c80, |
1092 | .hid_width = 5, |
1093 | .parent_map = gcc_xo_gpll0_map, |
1094 | .freq_tbl = ftbl_gcc_sata_pmalive_clk, |
1095 | .clkr.hw.init = &(struct clk_init_data){ |
1096 | .name = "sata_pmalive_clk_src" , |
1097 | .parent_data = gcc_xo_gpll0, |
1098 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1099 | .ops = &clk_rcg2_ops, |
1100 | }, |
1101 | }; |
1102 | |
1103 | static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = { |
1104 | F(75000000, P_SATA_RX_CLK, 1, 0, 0), |
1105 | F(150000000, P_SATA_RX_CLK, 1, 0, 0), |
1106 | F(300000000, P_SATA_RX_CLK, 1, 0, 0), |
1107 | { } |
1108 | }; |
1109 | |
1110 | static struct clk_rcg2 sata_rx_clk_src = { |
1111 | .cmd_rcgr = 0x1ca8, |
1112 | .hid_width = 5, |
1113 | .parent_map = gcc_xo_sata_rx_map, |
1114 | .freq_tbl = ftbl_gcc_sata_rx_clk, |
1115 | .clkr.hw.init = &(struct clk_init_data){ |
1116 | .name = "sata_rx_clk_src" , |
1117 | .parent_data = gcc_xo_sata_rx, |
1118 | .num_parents = ARRAY_SIZE(gcc_xo_sata_rx), |
1119 | .ops = &clk_rcg2_ops, |
1120 | }, |
1121 | }; |
1122 | |
1123 | static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = { |
1124 | F(100000000, P_GPLL0, 6, 0, 0), |
1125 | { } |
1126 | }; |
1127 | |
1128 | static struct clk_rcg2 sata_rx_oob_clk_src = { |
1129 | .cmd_rcgr = 0x1c5c, |
1130 | .hid_width = 5, |
1131 | .parent_map = gcc_xo_gpll0_map, |
1132 | .freq_tbl = ftbl_gcc_sata_rx_oob_clk, |
1133 | .clkr.hw.init = &(struct clk_init_data){ |
1134 | .name = "sata_rx_oob_clk_src" , |
1135 | .parent_data = gcc_xo_gpll0, |
1136 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1137 | .ops = &clk_rcg2_ops, |
1138 | }, |
1139 | }; |
1140 | |
1141 | static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { |
1142 | F(144000, P_XO, 16, 3, 25), |
1143 | F(400000, P_XO, 12, 1, 4), |
1144 | F(20000000, P_GPLL0, 15, 1, 2), |
1145 | F(25000000, P_GPLL0, 12, 1, 2), |
1146 | F(50000000, P_GPLL0, 12, 0, 0), |
1147 | F(100000000, P_GPLL0, 6, 0, 0), |
1148 | F(192000000, P_GPLL4, 4, 0, 0), |
1149 | F(200000000, P_GPLL0, 3, 0, 0), |
1150 | F(384000000, P_GPLL4, 2, 0, 0), |
1151 | { } |
1152 | }; |
1153 | |
1154 | static struct clk_rcg2 sdcc1_apps_clk_src = { |
1155 | .cmd_rcgr = 0x04d0, |
1156 | .mnd_width = 8, |
1157 | .hid_width = 5, |
1158 | .parent_map = gcc_xo_gpll0_gpll4_map, |
1159 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, |
1160 | .clkr.hw.init = &(struct clk_init_data){ |
1161 | .name = "sdcc1_apps_clk_src" , |
1162 | .parent_data = gcc_xo_gpll0_gpll4, |
1163 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), |
1164 | .ops = &clk_rcg2_floor_ops, |
1165 | }, |
1166 | }; |
1167 | |
1168 | static struct clk_rcg2 sdcc2_apps_clk_src = { |
1169 | .cmd_rcgr = 0x0510, |
1170 | .mnd_width = 8, |
1171 | .hid_width = 5, |
1172 | .parent_map = gcc_xo_gpll0_map, |
1173 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, |
1174 | .clkr.hw.init = &(struct clk_init_data){ |
1175 | .name = "sdcc2_apps_clk_src" , |
1176 | .parent_data = gcc_xo_gpll0, |
1177 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1178 | .ops = &clk_rcg2_floor_ops, |
1179 | }, |
1180 | }; |
1181 | |
1182 | static struct clk_rcg2 sdcc3_apps_clk_src = { |
1183 | .cmd_rcgr = 0x0550, |
1184 | .mnd_width = 8, |
1185 | .hid_width = 5, |
1186 | .parent_map = gcc_xo_gpll0_map, |
1187 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, |
1188 | .clkr.hw.init = &(struct clk_init_data){ |
1189 | .name = "sdcc3_apps_clk_src" , |
1190 | .parent_data = gcc_xo_gpll0, |
1191 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1192 | .ops = &clk_rcg2_floor_ops, |
1193 | }, |
1194 | }; |
1195 | |
1196 | static struct clk_rcg2 sdcc4_apps_clk_src = { |
1197 | .cmd_rcgr = 0x0590, |
1198 | .mnd_width = 8, |
1199 | .hid_width = 5, |
1200 | .parent_map = gcc_xo_gpll0_map, |
1201 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, |
1202 | .clkr.hw.init = &(struct clk_init_data){ |
1203 | .name = "sdcc4_apps_clk_src" , |
1204 | .parent_data = gcc_xo_gpll0, |
1205 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1206 | .ops = &clk_rcg2_floor_ops, |
1207 | }, |
1208 | }; |
1209 | |
1210 | static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = { |
1211 | F(105000, P_XO, 2, 1, 91), |
1212 | { } |
1213 | }; |
1214 | |
1215 | static struct clk_rcg2 tsif_ref_clk_src = { |
1216 | .cmd_rcgr = 0x0d90, |
1217 | .mnd_width = 8, |
1218 | .hid_width = 5, |
1219 | .parent_map = gcc_xo_gpll0_map, |
1220 | .freq_tbl = ftbl_gcc_tsif_ref_clk, |
1221 | .clkr.hw.init = &(struct clk_init_data){ |
1222 | .name = "tsif_ref_clk_src" , |
1223 | .parent_data = gcc_xo_gpll0, |
1224 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1225 | .ops = &clk_rcg2_ops, |
1226 | }, |
1227 | }; |
1228 | |
1229 | static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { |
1230 | F(60000000, P_GPLL0, 10, 0, 0), |
1231 | { } |
1232 | }; |
1233 | |
1234 | static struct clk_rcg2 usb30_mock_utmi_clk_src = { |
1235 | .cmd_rcgr = 0x03e8, |
1236 | .hid_width = 5, |
1237 | .parent_map = gcc_xo_gpll0_map, |
1238 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, |
1239 | .clkr.hw.init = &(struct clk_init_data){ |
1240 | .name = "usb30_mock_utmi_clk_src" , |
1241 | .parent_data = gcc_xo_gpll0, |
1242 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1243 | .ops = &clk_rcg2_ops, |
1244 | }, |
1245 | }; |
1246 | |
1247 | static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { |
1248 | F(75000000, P_GPLL0, 8, 0, 0), |
1249 | { } |
1250 | }; |
1251 | |
1252 | static struct clk_rcg2 usb_hs_system_clk_src = { |
1253 | .cmd_rcgr = 0x0490, |
1254 | .hid_width = 5, |
1255 | .parent_map = gcc_xo_gpll0_map, |
1256 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
1257 | .clkr.hw.init = &(struct clk_init_data){ |
1258 | .name = "usb_hs_system_clk_src" , |
1259 | .parent_data = gcc_xo_gpll0, |
1260 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1261 | .ops = &clk_rcg2_ops, |
1262 | }, |
1263 | }; |
1264 | |
1265 | static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = { |
1266 | F(480000000, P_GPLL1, 1, 0, 0), |
1267 | { } |
1268 | }; |
1269 | |
1270 | static const struct parent_map usb_hsic_clk_src_map[] = { |
1271 | { P_XO, 0 }, |
1272 | { P_GPLL1, 4 } |
1273 | }; |
1274 | |
1275 | static struct clk_rcg2 usb_hsic_clk_src = { |
1276 | .cmd_rcgr = 0x0440, |
1277 | .hid_width = 5, |
1278 | .parent_map = usb_hsic_clk_src_map, |
1279 | .freq_tbl = ftbl_gcc_usb_hsic_clk, |
1280 | .clkr.hw.init = &(struct clk_init_data){ |
1281 | .name = "usb_hsic_clk_src" , |
1282 | .parent_data = (const struct clk_parent_data[]){ |
1283 | { .fw_name = "xo" , .name = "xo_board" }, |
1284 | { .hw = &gpll1_vote.hw }, |
1285 | }, |
1286 | .num_parents = 2, |
1287 | .ops = &clk_rcg2_ops, |
1288 | }, |
1289 | }; |
1290 | |
1291 | static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = { |
1292 | F(60000000, P_GPLL1, 8, 0, 0), |
1293 | { } |
1294 | }; |
1295 | |
1296 | static struct clk_rcg2 usb_hsic_ahb_clk_src = { |
1297 | .cmd_rcgr = 0x046c, |
1298 | .mnd_width = 8, |
1299 | .hid_width = 5, |
1300 | .parent_map = usb_hsic_clk_src_map, |
1301 | .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src, |
1302 | .clkr.hw.init = &(struct clk_init_data){ |
1303 | .name = "usb_hsic_ahb_clk_src" , |
1304 | .parent_data = (const struct clk_parent_data[]){ |
1305 | { .fw_name = "xo" , .name = "xo_board" }, |
1306 | { .hw = &gpll1_vote.hw }, |
1307 | }, |
1308 | .num_parents = 2, |
1309 | .ops = &clk_rcg2_ops, |
1310 | }, |
1311 | }; |
1312 | |
1313 | static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { |
1314 | F(9600000, P_XO, 2, 0, 0), |
1315 | { } |
1316 | }; |
1317 | |
1318 | static struct clk_rcg2 usb_hsic_io_cal_clk_src = { |
1319 | .cmd_rcgr = 0x0458, |
1320 | .hid_width = 5, |
1321 | .parent_map = gcc_xo_gpll0_map, |
1322 | .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, |
1323 | .clkr.hw.init = &(struct clk_init_data){ |
1324 | .name = "usb_hsic_io_cal_clk_src" , |
1325 | .parent_data = gcc_xo_gpll0, |
1326 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1327 | .ops = &clk_rcg2_ops, |
1328 | }, |
1329 | }; |
1330 | |
1331 | static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = { |
1332 | F(60000000, P_GPLL0, 10, 0, 0), |
1333 | { } |
1334 | }; |
1335 | |
1336 | static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = { |
1337 | .cmd_rcgr = 0x1f00, |
1338 | .hid_width = 5, |
1339 | .parent_map = gcc_xo_gpll0_map, |
1340 | .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk, |
1341 | .clkr.hw.init = &(struct clk_init_data){ |
1342 | .name = "usb_hsic_mock_utmi_clk_src" , |
1343 | .parent_data = gcc_xo_gpll0, |
1344 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1345 | .ops = &clk_rcg2_ops, |
1346 | }, |
1347 | }; |
1348 | |
1349 | static struct clk_branch gcc_usb_hsic_mock_utmi_clk = { |
1350 | .halt_reg = 0x1f14, |
1351 | .clkr = { |
1352 | .enable_reg = 0x1f14, |
1353 | .enable_mask = BIT(0), |
1354 | .hw.init = &(struct clk_init_data){ |
1355 | .name = "gcc_usb_hsic_mock_utmi_clk" , |
1356 | .parent_hws = (const struct clk_hw*[]){ |
1357 | &usb_hsic_mock_utmi_clk_src.clkr.hw, |
1358 | }, |
1359 | .num_parents = 1, |
1360 | .flags = CLK_SET_RATE_PARENT, |
1361 | .ops = &clk_branch2_ops, |
1362 | }, |
1363 | }, |
1364 | }; |
1365 | |
1366 | static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { |
1367 | F(75000000, P_GPLL0, 8, 0, 0), |
1368 | { } |
1369 | }; |
1370 | |
1371 | static struct clk_rcg2 usb_hsic_system_clk_src = { |
1372 | .cmd_rcgr = 0x041c, |
1373 | .hid_width = 5, |
1374 | .parent_map = gcc_xo_gpll0_map, |
1375 | .freq_tbl = ftbl_gcc_usb_hsic_system_clk, |
1376 | .clkr.hw.init = &(struct clk_init_data){ |
1377 | .name = "usb_hsic_system_clk_src" , |
1378 | .parent_data = gcc_xo_gpll0, |
1379 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
1380 | .ops = &clk_rcg2_ops, |
1381 | }, |
1382 | }; |
1383 | |
1384 | static struct clk_regmap gcc_mmss_gpll0_clk_src = { |
1385 | .enable_reg = 0x1484, |
1386 | .enable_mask = BIT(26), |
1387 | .hw.init = &(struct clk_init_data){ |
1388 | .name = "mmss_gpll0_vote" , |
1389 | .parent_hws = (const struct clk_hw*[]){ |
1390 | &gpll0_vote.hw, |
1391 | }, |
1392 | .num_parents = 1, |
1393 | .ops = &clk_branch_simple_ops, |
1394 | }, |
1395 | }; |
1396 | |
1397 | static struct clk_branch gcc_bam_dma_ahb_clk = { |
1398 | .halt_reg = 0x0d44, |
1399 | .halt_check = BRANCH_HALT_VOTED, |
1400 | .clkr = { |
1401 | .enable_reg = 0x1484, |
1402 | .enable_mask = BIT(12), |
1403 | .hw.init = &(struct clk_init_data){ |
1404 | .name = "gcc_bam_dma_ahb_clk" , |
1405 | .parent_hws = (const struct clk_hw*[]){ |
1406 | &periph_noc_clk_src.clkr.hw, |
1407 | }, |
1408 | .num_parents = 1, |
1409 | .ops = &clk_branch2_ops, |
1410 | }, |
1411 | }, |
1412 | }; |
1413 | |
1414 | static struct clk_branch gcc_blsp1_ahb_clk = { |
1415 | .halt_reg = 0x05c4, |
1416 | .halt_check = BRANCH_HALT_VOTED, |
1417 | .clkr = { |
1418 | .enable_reg = 0x1484, |
1419 | .enable_mask = BIT(17), |
1420 | .hw.init = &(struct clk_init_data){ |
1421 | .name = "gcc_blsp1_ahb_clk" , |
1422 | .parent_hws = (const struct clk_hw*[]){ |
1423 | &periph_noc_clk_src.clkr.hw, |
1424 | }, |
1425 | .num_parents = 1, |
1426 | .ops = &clk_branch2_ops, |
1427 | }, |
1428 | }, |
1429 | }; |
1430 | |
1431 | static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { |
1432 | .halt_reg = 0x0648, |
1433 | .clkr = { |
1434 | .enable_reg = 0x0648, |
1435 | .enable_mask = BIT(0), |
1436 | .hw.init = &(struct clk_init_data){ |
1437 | .name = "gcc_blsp1_qup1_i2c_apps_clk" , |
1438 | .parent_hws = (const struct clk_hw*[]){ |
1439 | &blsp1_qup1_i2c_apps_clk_src.clkr.hw, |
1440 | }, |
1441 | .num_parents = 1, |
1442 | .flags = CLK_SET_RATE_PARENT, |
1443 | .ops = &clk_branch2_ops, |
1444 | }, |
1445 | }, |
1446 | }; |
1447 | |
1448 | static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { |
1449 | .halt_reg = 0x0644, |
1450 | .clkr = { |
1451 | .enable_reg = 0x0644, |
1452 | .enable_mask = BIT(0), |
1453 | .hw.init = &(struct clk_init_data){ |
1454 | .name = "gcc_blsp1_qup1_spi_apps_clk" , |
1455 | .parent_hws = (const struct clk_hw*[]){ |
1456 | &blsp1_qup1_spi_apps_clk_src.clkr.hw, |
1457 | }, |
1458 | .num_parents = 1, |
1459 | .flags = CLK_SET_RATE_PARENT, |
1460 | .ops = &clk_branch2_ops, |
1461 | }, |
1462 | }, |
1463 | }; |
1464 | |
1465 | static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { |
1466 | .halt_reg = 0x06c8, |
1467 | .clkr = { |
1468 | .enable_reg = 0x06c8, |
1469 | .enable_mask = BIT(0), |
1470 | .hw.init = &(struct clk_init_data){ |
1471 | .name = "gcc_blsp1_qup2_i2c_apps_clk" , |
1472 | .parent_hws = (const struct clk_hw*[]){ |
1473 | &blsp1_qup2_i2c_apps_clk_src.clkr.hw, |
1474 | }, |
1475 | .num_parents = 1, |
1476 | .flags = CLK_SET_RATE_PARENT, |
1477 | .ops = &clk_branch2_ops, |
1478 | }, |
1479 | }, |
1480 | }; |
1481 | |
1482 | static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { |
1483 | .halt_reg = 0x06c4, |
1484 | .clkr = { |
1485 | .enable_reg = 0x06c4, |
1486 | .enable_mask = BIT(0), |
1487 | .hw.init = &(struct clk_init_data){ |
1488 | .name = "gcc_blsp1_qup2_spi_apps_clk" , |
1489 | .parent_hws = (const struct clk_hw*[]){ |
1490 | &blsp1_qup2_spi_apps_clk_src.clkr.hw, |
1491 | }, |
1492 | .num_parents = 1, |
1493 | .flags = CLK_SET_RATE_PARENT, |
1494 | .ops = &clk_branch2_ops, |
1495 | }, |
1496 | }, |
1497 | }; |
1498 | |
1499 | static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { |
1500 | .halt_reg = 0x0748, |
1501 | .clkr = { |
1502 | .enable_reg = 0x0748, |
1503 | .enable_mask = BIT(0), |
1504 | .hw.init = &(struct clk_init_data){ |
1505 | .name = "gcc_blsp1_qup3_i2c_apps_clk" , |
1506 | .parent_hws = (const struct clk_hw*[]){ |
1507 | &blsp1_qup3_i2c_apps_clk_src.clkr.hw, |
1508 | }, |
1509 | .num_parents = 1, |
1510 | .flags = CLK_SET_RATE_PARENT, |
1511 | .ops = &clk_branch2_ops, |
1512 | }, |
1513 | }, |
1514 | }; |
1515 | |
1516 | static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { |
1517 | .halt_reg = 0x0744, |
1518 | .clkr = { |
1519 | .enable_reg = 0x0744, |
1520 | .enable_mask = BIT(0), |
1521 | .hw.init = &(struct clk_init_data){ |
1522 | .name = "gcc_blsp1_qup3_spi_apps_clk" , |
1523 | .parent_hws = (const struct clk_hw*[]){ |
1524 | &blsp1_qup3_spi_apps_clk_src.clkr.hw, |
1525 | }, |
1526 | .num_parents = 1, |
1527 | .flags = CLK_SET_RATE_PARENT, |
1528 | .ops = &clk_branch2_ops, |
1529 | }, |
1530 | }, |
1531 | }; |
1532 | |
1533 | static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { |
1534 | .halt_reg = 0x07c8, |
1535 | .clkr = { |
1536 | .enable_reg = 0x07c8, |
1537 | .enable_mask = BIT(0), |
1538 | .hw.init = &(struct clk_init_data){ |
1539 | .name = "gcc_blsp1_qup4_i2c_apps_clk" , |
1540 | .parent_hws = (const struct clk_hw*[]){ |
1541 | &blsp1_qup4_i2c_apps_clk_src.clkr.hw, |
1542 | }, |
1543 | .num_parents = 1, |
1544 | .flags = CLK_SET_RATE_PARENT, |
1545 | .ops = &clk_branch2_ops, |
1546 | }, |
1547 | }, |
1548 | }; |
1549 | |
1550 | static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { |
1551 | .halt_reg = 0x07c4, |
1552 | .clkr = { |
1553 | .enable_reg = 0x07c4, |
1554 | .enable_mask = BIT(0), |
1555 | .hw.init = &(struct clk_init_data){ |
1556 | .name = "gcc_blsp1_qup4_spi_apps_clk" , |
1557 | .parent_hws = (const struct clk_hw*[]){ |
1558 | &blsp1_qup4_spi_apps_clk_src.clkr.hw, |
1559 | }, |
1560 | .num_parents = 1, |
1561 | .flags = CLK_SET_RATE_PARENT, |
1562 | .ops = &clk_branch2_ops, |
1563 | }, |
1564 | }, |
1565 | }; |
1566 | |
1567 | static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { |
1568 | .halt_reg = 0x0848, |
1569 | .clkr = { |
1570 | .enable_reg = 0x0848, |
1571 | .enable_mask = BIT(0), |
1572 | .hw.init = &(struct clk_init_data){ |
1573 | .name = "gcc_blsp1_qup5_i2c_apps_clk" , |
1574 | .parent_hws = (const struct clk_hw*[]){ |
1575 | &blsp1_qup5_i2c_apps_clk_src.clkr.hw, |
1576 | }, |
1577 | .num_parents = 1, |
1578 | .flags = CLK_SET_RATE_PARENT, |
1579 | .ops = &clk_branch2_ops, |
1580 | }, |
1581 | }, |
1582 | }; |
1583 | |
1584 | static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { |
1585 | .halt_reg = 0x0844, |
1586 | .clkr = { |
1587 | .enable_reg = 0x0844, |
1588 | .enable_mask = BIT(0), |
1589 | .hw.init = &(struct clk_init_data){ |
1590 | .name = "gcc_blsp1_qup5_spi_apps_clk" , |
1591 | .parent_hws = (const struct clk_hw*[]){ |
1592 | &blsp1_qup5_spi_apps_clk_src.clkr.hw, |
1593 | }, |
1594 | .num_parents = 1, |
1595 | .flags = CLK_SET_RATE_PARENT, |
1596 | .ops = &clk_branch2_ops, |
1597 | }, |
1598 | }, |
1599 | }; |
1600 | |
1601 | static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { |
1602 | .halt_reg = 0x08c8, |
1603 | .clkr = { |
1604 | .enable_reg = 0x08c8, |
1605 | .enable_mask = BIT(0), |
1606 | .hw.init = &(struct clk_init_data){ |
1607 | .name = "gcc_blsp1_qup6_i2c_apps_clk" , |
1608 | .parent_hws = (const struct clk_hw*[]){ |
1609 | &blsp1_qup6_i2c_apps_clk_src.clkr.hw, |
1610 | }, |
1611 | .num_parents = 1, |
1612 | .flags = CLK_SET_RATE_PARENT, |
1613 | .ops = &clk_branch2_ops, |
1614 | }, |
1615 | }, |
1616 | }; |
1617 | |
1618 | static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { |
1619 | .halt_reg = 0x08c4, |
1620 | .clkr = { |
1621 | .enable_reg = 0x08c4, |
1622 | .enable_mask = BIT(0), |
1623 | .hw.init = &(struct clk_init_data){ |
1624 | .name = "gcc_blsp1_qup6_spi_apps_clk" , |
1625 | .parent_hws = (const struct clk_hw*[]){ |
1626 | &blsp1_qup6_spi_apps_clk_src.clkr.hw, |
1627 | }, |
1628 | .num_parents = 1, |
1629 | .flags = CLK_SET_RATE_PARENT, |
1630 | .ops = &clk_branch2_ops, |
1631 | }, |
1632 | }, |
1633 | }; |
1634 | |
1635 | static struct clk_branch gcc_blsp1_uart1_apps_clk = { |
1636 | .halt_reg = 0x0684, |
1637 | .clkr = { |
1638 | .enable_reg = 0x0684, |
1639 | .enable_mask = BIT(0), |
1640 | .hw.init = &(struct clk_init_data){ |
1641 | .name = "gcc_blsp1_uart1_apps_clk" , |
1642 | .parent_hws = (const struct clk_hw*[]){ |
1643 | &blsp1_uart1_apps_clk_src.clkr.hw, |
1644 | }, |
1645 | .num_parents = 1, |
1646 | .flags = CLK_SET_RATE_PARENT, |
1647 | .ops = &clk_branch2_ops, |
1648 | }, |
1649 | }, |
1650 | }; |
1651 | |
1652 | static struct clk_branch gcc_blsp1_uart2_apps_clk = { |
1653 | .halt_reg = 0x0704, |
1654 | .clkr = { |
1655 | .enable_reg = 0x0704, |
1656 | .enable_mask = BIT(0), |
1657 | .hw.init = &(struct clk_init_data){ |
1658 | .name = "gcc_blsp1_uart2_apps_clk" , |
1659 | .parent_hws = (const struct clk_hw*[]){ |
1660 | &blsp1_uart2_apps_clk_src.clkr.hw, |
1661 | }, |
1662 | .num_parents = 1, |
1663 | .flags = CLK_SET_RATE_PARENT, |
1664 | .ops = &clk_branch2_ops, |
1665 | }, |
1666 | }, |
1667 | }; |
1668 | |
1669 | static struct clk_branch gcc_blsp1_uart3_apps_clk = { |
1670 | .halt_reg = 0x0784, |
1671 | .clkr = { |
1672 | .enable_reg = 0x0784, |
1673 | .enable_mask = BIT(0), |
1674 | .hw.init = &(struct clk_init_data){ |
1675 | .name = "gcc_blsp1_uart3_apps_clk" , |
1676 | .parent_hws = (const struct clk_hw*[]){ |
1677 | &blsp1_uart3_apps_clk_src.clkr.hw, |
1678 | }, |
1679 | .num_parents = 1, |
1680 | .flags = CLK_SET_RATE_PARENT, |
1681 | .ops = &clk_branch2_ops, |
1682 | }, |
1683 | }, |
1684 | }; |
1685 | |
1686 | static struct clk_branch gcc_blsp1_uart4_apps_clk = { |
1687 | .halt_reg = 0x0804, |
1688 | .clkr = { |
1689 | .enable_reg = 0x0804, |
1690 | .enable_mask = BIT(0), |
1691 | .hw.init = &(struct clk_init_data){ |
1692 | .name = "gcc_blsp1_uart4_apps_clk" , |
1693 | .parent_hws = (const struct clk_hw*[]){ |
1694 | &blsp1_uart4_apps_clk_src.clkr.hw, |
1695 | }, |
1696 | .num_parents = 1, |
1697 | .flags = CLK_SET_RATE_PARENT, |
1698 | .ops = &clk_branch2_ops, |
1699 | }, |
1700 | }, |
1701 | }; |
1702 | |
1703 | static struct clk_branch gcc_blsp1_uart5_apps_clk = { |
1704 | .halt_reg = 0x0884, |
1705 | .clkr = { |
1706 | .enable_reg = 0x0884, |
1707 | .enable_mask = BIT(0), |
1708 | .hw.init = &(struct clk_init_data){ |
1709 | .name = "gcc_blsp1_uart5_apps_clk" , |
1710 | .parent_hws = (const struct clk_hw*[]){ |
1711 | &blsp1_uart5_apps_clk_src.clkr.hw, |
1712 | }, |
1713 | .num_parents = 1, |
1714 | .flags = CLK_SET_RATE_PARENT, |
1715 | .ops = &clk_branch2_ops, |
1716 | }, |
1717 | }, |
1718 | }; |
1719 | |
1720 | static struct clk_branch gcc_blsp1_uart6_apps_clk = { |
1721 | .halt_reg = 0x0904, |
1722 | .clkr = { |
1723 | .enable_reg = 0x0904, |
1724 | .enable_mask = BIT(0), |
1725 | .hw.init = &(struct clk_init_data){ |
1726 | .name = "gcc_blsp1_uart6_apps_clk" , |
1727 | .parent_hws = (const struct clk_hw*[]){ |
1728 | &blsp1_uart6_apps_clk_src.clkr.hw, |
1729 | }, |
1730 | .num_parents = 1, |
1731 | .flags = CLK_SET_RATE_PARENT, |
1732 | .ops = &clk_branch2_ops, |
1733 | }, |
1734 | }, |
1735 | }; |
1736 | |
1737 | static struct clk_branch gcc_blsp2_ahb_clk = { |
1738 | .halt_reg = 0x0944, |
1739 | .halt_check = BRANCH_HALT_VOTED, |
1740 | .clkr = { |
1741 | .enable_reg = 0x1484, |
1742 | .enable_mask = BIT(15), |
1743 | .hw.init = &(struct clk_init_data){ |
1744 | .name = "gcc_blsp2_ahb_clk" , |
1745 | .parent_hws = (const struct clk_hw*[]){ |
1746 | &periph_noc_clk_src.clkr.hw, |
1747 | }, |
1748 | .num_parents = 1, |
1749 | .ops = &clk_branch2_ops, |
1750 | }, |
1751 | }, |
1752 | }; |
1753 | |
1754 | static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { |
1755 | .halt_reg = 0x0988, |
1756 | .clkr = { |
1757 | .enable_reg = 0x0988, |
1758 | .enable_mask = BIT(0), |
1759 | .hw.init = &(struct clk_init_data){ |
1760 | .name = "gcc_blsp2_qup1_i2c_apps_clk" , |
1761 | .parent_hws = (const struct clk_hw*[]){ |
1762 | &blsp2_qup1_i2c_apps_clk_src.clkr.hw, |
1763 | }, |
1764 | .num_parents = 1, |
1765 | .flags = CLK_SET_RATE_PARENT, |
1766 | .ops = &clk_branch2_ops, |
1767 | }, |
1768 | }, |
1769 | }; |
1770 | |
1771 | static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { |
1772 | .halt_reg = 0x0984, |
1773 | .clkr = { |
1774 | .enable_reg = 0x0984, |
1775 | .enable_mask = BIT(0), |
1776 | .hw.init = &(struct clk_init_data){ |
1777 | .name = "gcc_blsp2_qup1_spi_apps_clk" , |
1778 | .parent_hws = (const struct clk_hw*[]){ |
1779 | &blsp2_qup1_spi_apps_clk_src.clkr.hw, |
1780 | }, |
1781 | .num_parents = 1, |
1782 | .flags = CLK_SET_RATE_PARENT, |
1783 | .ops = &clk_branch2_ops, |
1784 | }, |
1785 | }, |
1786 | }; |
1787 | |
1788 | static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { |
1789 | .halt_reg = 0x0a08, |
1790 | .clkr = { |
1791 | .enable_reg = 0x0a08, |
1792 | .enable_mask = BIT(0), |
1793 | .hw.init = &(struct clk_init_data){ |
1794 | .name = "gcc_blsp2_qup2_i2c_apps_clk" , |
1795 | .parent_hws = (const struct clk_hw*[]){ |
1796 | &blsp2_qup2_i2c_apps_clk_src.clkr.hw, |
1797 | }, |
1798 | .num_parents = 1, |
1799 | .flags = CLK_SET_RATE_PARENT, |
1800 | .ops = &clk_branch2_ops, |
1801 | }, |
1802 | }, |
1803 | }; |
1804 | |
1805 | static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { |
1806 | .halt_reg = 0x0a04, |
1807 | .clkr = { |
1808 | .enable_reg = 0x0a04, |
1809 | .enable_mask = BIT(0), |
1810 | .hw.init = &(struct clk_init_data){ |
1811 | .name = "gcc_blsp2_qup2_spi_apps_clk" , |
1812 | .parent_hws = (const struct clk_hw*[]){ |
1813 | &blsp2_qup2_spi_apps_clk_src.clkr.hw, |
1814 | }, |
1815 | .num_parents = 1, |
1816 | .flags = CLK_SET_RATE_PARENT, |
1817 | .ops = &clk_branch2_ops, |
1818 | }, |
1819 | }, |
1820 | }; |
1821 | |
1822 | static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { |
1823 | .halt_reg = 0x0a88, |
1824 | .clkr = { |
1825 | .enable_reg = 0x0a88, |
1826 | .enable_mask = BIT(0), |
1827 | .hw.init = &(struct clk_init_data){ |
1828 | .name = "gcc_blsp2_qup3_i2c_apps_clk" , |
1829 | .parent_hws = (const struct clk_hw*[]){ |
1830 | &blsp2_qup3_i2c_apps_clk_src.clkr.hw, |
1831 | }, |
1832 | .num_parents = 1, |
1833 | .flags = CLK_SET_RATE_PARENT, |
1834 | .ops = &clk_branch2_ops, |
1835 | }, |
1836 | }, |
1837 | }; |
1838 | |
1839 | static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { |
1840 | .halt_reg = 0x0a84, |
1841 | .clkr = { |
1842 | .enable_reg = 0x0a84, |
1843 | .enable_mask = BIT(0), |
1844 | .hw.init = &(struct clk_init_data){ |
1845 | .name = "gcc_blsp2_qup3_spi_apps_clk" , |
1846 | .parent_hws = (const struct clk_hw*[]){ |
1847 | &blsp2_qup3_spi_apps_clk_src.clkr.hw, |
1848 | }, |
1849 | .num_parents = 1, |
1850 | .flags = CLK_SET_RATE_PARENT, |
1851 | .ops = &clk_branch2_ops, |
1852 | }, |
1853 | }, |
1854 | }; |
1855 | |
1856 | static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { |
1857 | .halt_reg = 0x0b08, |
1858 | .clkr = { |
1859 | .enable_reg = 0x0b08, |
1860 | .enable_mask = BIT(0), |
1861 | .hw.init = &(struct clk_init_data){ |
1862 | .name = "gcc_blsp2_qup4_i2c_apps_clk" , |
1863 | .parent_hws = (const struct clk_hw*[]){ |
1864 | &blsp2_qup4_i2c_apps_clk_src.clkr.hw, |
1865 | }, |
1866 | .num_parents = 1, |
1867 | .flags = CLK_SET_RATE_PARENT, |
1868 | .ops = &clk_branch2_ops, |
1869 | }, |
1870 | }, |
1871 | }; |
1872 | |
1873 | static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { |
1874 | .halt_reg = 0x0b04, |
1875 | .clkr = { |
1876 | .enable_reg = 0x0b04, |
1877 | .enable_mask = BIT(0), |
1878 | .hw.init = &(struct clk_init_data){ |
1879 | .name = "gcc_blsp2_qup4_spi_apps_clk" , |
1880 | .parent_hws = (const struct clk_hw*[]){ |
1881 | &blsp2_qup4_spi_apps_clk_src.clkr.hw, |
1882 | }, |
1883 | .num_parents = 1, |
1884 | .flags = CLK_SET_RATE_PARENT, |
1885 | .ops = &clk_branch2_ops, |
1886 | }, |
1887 | }, |
1888 | }; |
1889 | |
1890 | static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { |
1891 | .halt_reg = 0x0b88, |
1892 | .clkr = { |
1893 | .enable_reg = 0x0b88, |
1894 | .enable_mask = BIT(0), |
1895 | .hw.init = &(struct clk_init_data){ |
1896 | .name = "gcc_blsp2_qup5_i2c_apps_clk" , |
1897 | .parent_hws = (const struct clk_hw*[]){ |
1898 | &blsp2_qup5_i2c_apps_clk_src.clkr.hw, |
1899 | }, |
1900 | .num_parents = 1, |
1901 | .flags = CLK_SET_RATE_PARENT, |
1902 | .ops = &clk_branch2_ops, |
1903 | }, |
1904 | }, |
1905 | }; |
1906 | |
1907 | static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { |
1908 | .halt_reg = 0x0b84, |
1909 | .clkr = { |
1910 | .enable_reg = 0x0b84, |
1911 | .enable_mask = BIT(0), |
1912 | .hw.init = &(struct clk_init_data){ |
1913 | .name = "gcc_blsp2_qup5_spi_apps_clk" , |
1914 | .parent_hws = (const struct clk_hw*[]){ |
1915 | &blsp2_qup5_spi_apps_clk_src.clkr.hw, |
1916 | }, |
1917 | .num_parents = 1, |
1918 | .flags = CLK_SET_RATE_PARENT, |
1919 | .ops = &clk_branch2_ops, |
1920 | }, |
1921 | }, |
1922 | }; |
1923 | |
1924 | static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { |
1925 | .halt_reg = 0x0c08, |
1926 | .clkr = { |
1927 | .enable_reg = 0x0c08, |
1928 | .enable_mask = BIT(0), |
1929 | .hw.init = &(struct clk_init_data){ |
1930 | .name = "gcc_blsp2_qup6_i2c_apps_clk" , |
1931 | .parent_hws = (const struct clk_hw*[]){ |
1932 | &blsp2_qup6_i2c_apps_clk_src.clkr.hw, |
1933 | }, |
1934 | .num_parents = 1, |
1935 | .flags = CLK_SET_RATE_PARENT, |
1936 | .ops = &clk_branch2_ops, |
1937 | }, |
1938 | }, |
1939 | }; |
1940 | |
1941 | static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { |
1942 | .halt_reg = 0x0c04, |
1943 | .clkr = { |
1944 | .enable_reg = 0x0c04, |
1945 | .enable_mask = BIT(0), |
1946 | .hw.init = &(struct clk_init_data){ |
1947 | .name = "gcc_blsp2_qup6_spi_apps_clk" , |
1948 | .parent_hws = (const struct clk_hw*[]){ |
1949 | &blsp2_qup6_spi_apps_clk_src.clkr.hw, |
1950 | }, |
1951 | .num_parents = 1, |
1952 | .flags = CLK_SET_RATE_PARENT, |
1953 | .ops = &clk_branch2_ops, |
1954 | }, |
1955 | }, |
1956 | }; |
1957 | |
1958 | static struct clk_branch gcc_blsp2_uart1_apps_clk = { |
1959 | .halt_reg = 0x09c4, |
1960 | .clkr = { |
1961 | .enable_reg = 0x09c4, |
1962 | .enable_mask = BIT(0), |
1963 | .hw.init = &(struct clk_init_data){ |
1964 | .name = "gcc_blsp2_uart1_apps_clk" , |
1965 | .parent_hws = (const struct clk_hw*[]){ |
1966 | &blsp2_uart1_apps_clk_src.clkr.hw, |
1967 | }, |
1968 | .num_parents = 1, |
1969 | .flags = CLK_SET_RATE_PARENT, |
1970 | .ops = &clk_branch2_ops, |
1971 | }, |
1972 | }, |
1973 | }; |
1974 | |
1975 | static struct clk_branch gcc_blsp2_uart2_apps_clk = { |
1976 | .halt_reg = 0x0a44, |
1977 | .clkr = { |
1978 | .enable_reg = 0x0a44, |
1979 | .enable_mask = BIT(0), |
1980 | .hw.init = &(struct clk_init_data){ |
1981 | .name = "gcc_blsp2_uart2_apps_clk" , |
1982 | .parent_hws = (const struct clk_hw*[]){ |
1983 | &blsp2_uart2_apps_clk_src.clkr.hw, |
1984 | }, |
1985 | .num_parents = 1, |
1986 | .flags = CLK_SET_RATE_PARENT, |
1987 | .ops = &clk_branch2_ops, |
1988 | }, |
1989 | }, |
1990 | }; |
1991 | |
1992 | static struct clk_branch gcc_blsp2_uart3_apps_clk = { |
1993 | .halt_reg = 0x0ac4, |
1994 | .clkr = { |
1995 | .enable_reg = 0x0ac4, |
1996 | .enable_mask = BIT(0), |
1997 | .hw.init = &(struct clk_init_data){ |
1998 | .name = "gcc_blsp2_uart3_apps_clk" , |
1999 | .parent_hws = (const struct clk_hw*[]){ |
2000 | &blsp2_uart3_apps_clk_src.clkr.hw, |
2001 | }, |
2002 | .num_parents = 1, |
2003 | .flags = CLK_SET_RATE_PARENT, |
2004 | .ops = &clk_branch2_ops, |
2005 | }, |
2006 | }, |
2007 | }; |
2008 | |
2009 | static struct clk_branch gcc_blsp2_uart4_apps_clk = { |
2010 | .halt_reg = 0x0b44, |
2011 | .clkr = { |
2012 | .enable_reg = 0x0b44, |
2013 | .enable_mask = BIT(0), |
2014 | .hw.init = &(struct clk_init_data){ |
2015 | .name = "gcc_blsp2_uart4_apps_clk" , |
2016 | .parent_hws = (const struct clk_hw*[]){ |
2017 | &blsp2_uart4_apps_clk_src.clkr.hw, |
2018 | }, |
2019 | .num_parents = 1, |
2020 | .flags = CLK_SET_RATE_PARENT, |
2021 | .ops = &clk_branch2_ops, |
2022 | }, |
2023 | }, |
2024 | }; |
2025 | |
2026 | static struct clk_branch gcc_blsp2_uart5_apps_clk = { |
2027 | .halt_reg = 0x0bc4, |
2028 | .clkr = { |
2029 | .enable_reg = 0x0bc4, |
2030 | .enable_mask = BIT(0), |
2031 | .hw.init = &(struct clk_init_data){ |
2032 | .name = "gcc_blsp2_uart5_apps_clk" , |
2033 | .parent_hws = (const struct clk_hw*[]){ |
2034 | &blsp2_uart5_apps_clk_src.clkr.hw, |
2035 | }, |
2036 | .num_parents = 1, |
2037 | .flags = CLK_SET_RATE_PARENT, |
2038 | .ops = &clk_branch2_ops, |
2039 | }, |
2040 | }, |
2041 | }; |
2042 | |
2043 | static struct clk_branch gcc_blsp2_uart6_apps_clk = { |
2044 | .halt_reg = 0x0c44, |
2045 | .clkr = { |
2046 | .enable_reg = 0x0c44, |
2047 | .enable_mask = BIT(0), |
2048 | .hw.init = &(struct clk_init_data){ |
2049 | .name = "gcc_blsp2_uart6_apps_clk" , |
2050 | .parent_hws = (const struct clk_hw*[]){ |
2051 | &blsp2_uart6_apps_clk_src.clkr.hw, |
2052 | }, |
2053 | .num_parents = 1, |
2054 | .flags = CLK_SET_RATE_PARENT, |
2055 | .ops = &clk_branch2_ops, |
2056 | }, |
2057 | }, |
2058 | }; |
2059 | |
2060 | static struct clk_branch gcc_boot_rom_ahb_clk = { |
2061 | .halt_reg = 0x0e04, |
2062 | .halt_check = BRANCH_HALT_VOTED, |
2063 | .clkr = { |
2064 | .enable_reg = 0x1484, |
2065 | .enable_mask = BIT(10), |
2066 | .hw.init = &(struct clk_init_data){ |
2067 | .name = "gcc_boot_rom_ahb_clk" , |
2068 | .parent_hws = (const struct clk_hw*[]){ |
2069 | &config_noc_clk_src.clkr.hw, |
2070 | }, |
2071 | .num_parents = 1, |
2072 | .ops = &clk_branch2_ops, |
2073 | }, |
2074 | }, |
2075 | }; |
2076 | |
2077 | static struct clk_branch gcc_ce1_ahb_clk = { |
2078 | .halt_reg = 0x104c, |
2079 | .halt_check = BRANCH_HALT_VOTED, |
2080 | .clkr = { |
2081 | .enable_reg = 0x1484, |
2082 | .enable_mask = BIT(3), |
2083 | .hw.init = &(struct clk_init_data){ |
2084 | .name = "gcc_ce1_ahb_clk" , |
2085 | .parent_hws = (const struct clk_hw*[]){ |
2086 | &config_noc_clk_src.clkr.hw, |
2087 | }, |
2088 | .num_parents = 1, |
2089 | .ops = &clk_branch2_ops, |
2090 | }, |
2091 | }, |
2092 | }; |
2093 | |
2094 | static struct clk_branch gcc_ce1_axi_clk = { |
2095 | .halt_reg = 0x1048, |
2096 | .halt_check = BRANCH_HALT_VOTED, |
2097 | .clkr = { |
2098 | .enable_reg = 0x1484, |
2099 | .enable_mask = BIT(4), |
2100 | .hw.init = &(struct clk_init_data){ |
2101 | .name = "gcc_ce1_axi_clk" , |
2102 | .parent_hws = (const struct clk_hw*[]){ |
2103 | &system_noc_clk_src.clkr.hw, |
2104 | }, |
2105 | .num_parents = 1, |
2106 | .ops = &clk_branch2_ops, |
2107 | }, |
2108 | }, |
2109 | }; |
2110 | |
2111 | static struct clk_branch gcc_ce1_clk = { |
2112 | .halt_reg = 0x1050, |
2113 | .halt_check = BRANCH_HALT_VOTED, |
2114 | .clkr = { |
2115 | .enable_reg = 0x1484, |
2116 | .enable_mask = BIT(5), |
2117 | .hw.init = &(struct clk_init_data){ |
2118 | .name = "gcc_ce1_clk" , |
2119 | .parent_hws = (const struct clk_hw*[]){ |
2120 | &ce1_clk_src.clkr.hw, |
2121 | }, |
2122 | .num_parents = 1, |
2123 | .flags = CLK_SET_RATE_PARENT, |
2124 | .ops = &clk_branch2_ops, |
2125 | }, |
2126 | }, |
2127 | }; |
2128 | |
2129 | static struct clk_branch gcc_ce2_ahb_clk = { |
2130 | .halt_reg = 0x108c, |
2131 | .halt_check = BRANCH_HALT_VOTED, |
2132 | .clkr = { |
2133 | .enable_reg = 0x1484, |
2134 | .enable_mask = BIT(0), |
2135 | .hw.init = &(struct clk_init_data){ |
2136 | .name = "gcc_ce2_ahb_clk" , |
2137 | .parent_hws = (const struct clk_hw*[]){ |
2138 | &config_noc_clk_src.clkr.hw, |
2139 | }, |
2140 | .num_parents = 1, |
2141 | .ops = &clk_branch2_ops, |
2142 | }, |
2143 | }, |
2144 | }; |
2145 | |
2146 | static struct clk_branch gcc_ce2_axi_clk = { |
2147 | .halt_reg = 0x1088, |
2148 | .halt_check = BRANCH_HALT_VOTED, |
2149 | .clkr = { |
2150 | .enable_reg = 0x1484, |
2151 | .enable_mask = BIT(1), |
2152 | .hw.init = &(struct clk_init_data){ |
2153 | .name = "gcc_ce2_axi_clk" , |
2154 | .parent_hws = (const struct clk_hw*[]){ |
2155 | &system_noc_clk_src.clkr.hw, |
2156 | }, |
2157 | .num_parents = 1, |
2158 | .ops = &clk_branch2_ops, |
2159 | }, |
2160 | }, |
2161 | }; |
2162 | |
2163 | static struct clk_branch gcc_ce2_clk = { |
2164 | .halt_reg = 0x1090, |
2165 | .halt_check = BRANCH_HALT_VOTED, |
2166 | .clkr = { |
2167 | .enable_reg = 0x1484, |
2168 | .enable_mask = BIT(2), |
2169 | .hw.init = &(struct clk_init_data){ |
2170 | .name = "gcc_ce2_clk" , |
2171 | .parent_hws = (const struct clk_hw*[]){ |
2172 | &ce2_clk_src.clkr.hw, |
2173 | }, |
2174 | .num_parents = 1, |
2175 | .flags = CLK_SET_RATE_PARENT, |
2176 | .ops = &clk_branch2_ops, |
2177 | }, |
2178 | }, |
2179 | }; |
2180 | |
2181 | static struct clk_branch gcc_ce3_ahb_clk = { |
2182 | .halt_reg = 0x1d0c, |
2183 | .halt_check = BRANCH_HALT_VOTED, |
2184 | .clkr = { |
2185 | .enable_reg = 0x1d0c, |
2186 | .enable_mask = BIT(0), |
2187 | .hw.init = &(struct clk_init_data){ |
2188 | .name = "gcc_ce3_ahb_clk" , |
2189 | .parent_hws = (const struct clk_hw*[]){ |
2190 | &config_noc_clk_src.clkr.hw, |
2191 | }, |
2192 | .num_parents = 1, |
2193 | .ops = &clk_branch2_ops, |
2194 | }, |
2195 | }, |
2196 | }; |
2197 | |
2198 | static struct clk_branch gcc_ce3_axi_clk = { |
2199 | .halt_reg = 0x1088, |
2200 | .halt_check = BRANCH_HALT_VOTED, |
2201 | .clkr = { |
2202 | .enable_reg = 0x1d08, |
2203 | .enable_mask = BIT(0), |
2204 | .hw.init = &(struct clk_init_data){ |
2205 | .name = "gcc_ce3_axi_clk" , |
2206 | .parent_hws = (const struct clk_hw*[]){ |
2207 | &system_noc_clk_src.clkr.hw, |
2208 | }, |
2209 | .num_parents = 1, |
2210 | .ops = &clk_branch2_ops, |
2211 | }, |
2212 | }, |
2213 | }; |
2214 | |
2215 | static struct clk_branch gcc_ce3_clk = { |
2216 | .halt_reg = 0x1090, |
2217 | .halt_check = BRANCH_HALT_VOTED, |
2218 | .clkr = { |
2219 | .enable_reg = 0x1d04, |
2220 | .enable_mask = BIT(0), |
2221 | .hw.init = &(struct clk_init_data){ |
2222 | .name = "gcc_ce3_clk" , |
2223 | .parent_hws = (const struct clk_hw*[]){ |
2224 | &ce3_clk_src.clkr.hw, |
2225 | }, |
2226 | .num_parents = 1, |
2227 | .flags = CLK_SET_RATE_PARENT, |
2228 | .ops = &clk_branch2_ops, |
2229 | }, |
2230 | }, |
2231 | }; |
2232 | |
2233 | static struct clk_branch gcc_gp1_clk = { |
2234 | .halt_reg = 0x1900, |
2235 | .clkr = { |
2236 | .enable_reg = 0x1900, |
2237 | .enable_mask = BIT(0), |
2238 | .hw.init = &(struct clk_init_data){ |
2239 | .name = "gcc_gp1_clk" , |
2240 | .parent_hws = (const struct clk_hw*[]){ |
2241 | &gp1_clk_src.clkr.hw, |
2242 | }, |
2243 | .num_parents = 1, |
2244 | .flags = CLK_SET_RATE_PARENT, |
2245 | .ops = &clk_branch2_ops, |
2246 | }, |
2247 | }, |
2248 | }; |
2249 | |
2250 | static struct clk_branch gcc_gp2_clk = { |
2251 | .halt_reg = 0x1940, |
2252 | .clkr = { |
2253 | .enable_reg = 0x1940, |
2254 | .enable_mask = BIT(0), |
2255 | .hw.init = &(struct clk_init_data){ |
2256 | .name = "gcc_gp2_clk" , |
2257 | .parent_hws = (const struct clk_hw*[]){ |
2258 | &gp2_clk_src.clkr.hw, |
2259 | }, |
2260 | .num_parents = 1, |
2261 | .flags = CLK_SET_RATE_PARENT, |
2262 | .ops = &clk_branch2_ops, |
2263 | }, |
2264 | }, |
2265 | }; |
2266 | |
2267 | static struct clk_branch gcc_gp3_clk = { |
2268 | .halt_reg = 0x1980, |
2269 | .clkr = { |
2270 | .enable_reg = 0x1980, |
2271 | .enable_mask = BIT(0), |
2272 | .hw.init = &(struct clk_init_data){ |
2273 | .name = "gcc_gp3_clk" , |
2274 | .parent_hws = (const struct clk_hw*[]){ |
2275 | &gp3_clk_src.clkr.hw, |
2276 | }, |
2277 | .num_parents = 1, |
2278 | .flags = CLK_SET_RATE_PARENT, |
2279 | .ops = &clk_branch2_ops, |
2280 | }, |
2281 | }, |
2282 | }; |
2283 | |
2284 | static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = { |
2285 | .halt_reg = 0x0248, |
2286 | .clkr = { |
2287 | .enable_reg = 0x0248, |
2288 | .enable_mask = BIT(0), |
2289 | .hw.init = &(struct clk_init_data){ |
2290 | .name = "gcc_ocmem_noc_cfg_ahb_clk" , |
2291 | .parent_hws = (const struct clk_hw*[]){ |
2292 | &config_noc_clk_src.clkr.hw, |
2293 | }, |
2294 | .num_parents = 1, |
2295 | .ops = &clk_branch2_ops, |
2296 | }, |
2297 | }, |
2298 | }; |
2299 | |
2300 | static struct clk_branch gcc_pcie_0_aux_clk = { |
2301 | .halt_reg = 0x1b10, |
2302 | .clkr = { |
2303 | .enable_reg = 0x1b10, |
2304 | .enable_mask = BIT(0), |
2305 | .hw.init = &(struct clk_init_data){ |
2306 | .name = "gcc_pcie_0_aux_clk" , |
2307 | .parent_hws = (const struct clk_hw*[]){ |
2308 | &pcie_0_aux_clk_src.clkr.hw, |
2309 | }, |
2310 | .num_parents = 1, |
2311 | .flags = CLK_SET_RATE_PARENT, |
2312 | .ops = &clk_branch2_ops, |
2313 | }, |
2314 | }, |
2315 | }; |
2316 | |
2317 | static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { |
2318 | .halt_reg = 0x1b0c, |
2319 | .clkr = { |
2320 | .enable_reg = 0x1b0c, |
2321 | .enable_mask = BIT(0), |
2322 | .hw.init = &(struct clk_init_data){ |
2323 | .name = "gcc_pcie_0_cfg_ahb_clk" , |
2324 | .parent_hws = (const struct clk_hw*[]){ |
2325 | &config_noc_clk_src.clkr.hw, |
2326 | }, |
2327 | .num_parents = 1, |
2328 | .flags = CLK_SET_RATE_PARENT, |
2329 | .ops = &clk_branch2_ops, |
2330 | }, |
2331 | }, |
2332 | }; |
2333 | |
2334 | static struct clk_branch gcc_pcie_0_mstr_axi_clk = { |
2335 | .halt_reg = 0x1b08, |
2336 | .clkr = { |
2337 | .enable_reg = 0x1b08, |
2338 | .enable_mask = BIT(0), |
2339 | .hw.init = &(struct clk_init_data){ |
2340 | .name = "gcc_pcie_0_mstr_axi_clk" , |
2341 | .parent_hws = (const struct clk_hw*[]){ |
2342 | &config_noc_clk_src.clkr.hw, |
2343 | }, |
2344 | .num_parents = 1, |
2345 | .flags = CLK_SET_RATE_PARENT, |
2346 | .ops = &clk_branch2_ops, |
2347 | }, |
2348 | }, |
2349 | }; |
2350 | |
2351 | static struct clk_branch gcc_pcie_0_pipe_clk = { |
2352 | .halt_reg = 0x1b14, |
2353 | .clkr = { |
2354 | .enable_reg = 0x1b14, |
2355 | .enable_mask = BIT(0), |
2356 | .hw.init = &(struct clk_init_data){ |
2357 | .name = "gcc_pcie_0_pipe_clk" , |
2358 | .parent_data = &(const struct clk_parent_data){ |
2359 | .hw = &pcie_0_pipe_clk_src.clkr.hw, |
2360 | }, |
2361 | .num_parents = 1, |
2362 | .flags = CLK_SET_RATE_PARENT, |
2363 | .ops = &clk_branch2_ops, |
2364 | }, |
2365 | }, |
2366 | }; |
2367 | |
2368 | static struct clk_branch gcc_pcie_0_slv_axi_clk = { |
2369 | .halt_reg = 0x1b04, |
2370 | .clkr = { |
2371 | .enable_reg = 0x1b04, |
2372 | .enable_mask = BIT(0), |
2373 | .hw.init = &(struct clk_init_data){ |
2374 | .name = "gcc_pcie_0_slv_axi_clk" , |
2375 | .parent_hws = (const struct clk_hw*[]){ |
2376 | &config_noc_clk_src.clkr.hw, |
2377 | }, |
2378 | .num_parents = 1, |
2379 | .flags = CLK_SET_RATE_PARENT, |
2380 | .ops = &clk_branch2_ops, |
2381 | }, |
2382 | }, |
2383 | }; |
2384 | |
2385 | static struct clk_branch gcc_pcie_1_aux_clk = { |
2386 | .halt_reg = 0x1b90, |
2387 | .clkr = { |
2388 | .enable_reg = 0x1b90, |
2389 | .enable_mask = BIT(0), |
2390 | .hw.init = &(struct clk_init_data){ |
2391 | .name = "gcc_pcie_1_aux_clk" , |
2392 | .parent_hws = (const struct clk_hw*[]){ |
2393 | &pcie_1_aux_clk_src.clkr.hw, |
2394 | }, |
2395 | .num_parents = 1, |
2396 | .flags = CLK_SET_RATE_PARENT, |
2397 | .ops = &clk_branch2_ops, |
2398 | }, |
2399 | }, |
2400 | }; |
2401 | |
2402 | static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { |
2403 | .halt_reg = 0x1b8c, |
2404 | .clkr = { |
2405 | .enable_reg = 0x1b8c, |
2406 | .enable_mask = BIT(0), |
2407 | .hw.init = &(struct clk_init_data){ |
2408 | .name = "gcc_pcie_1_cfg_ahb_clk" , |
2409 | .parent_hws = (const struct clk_hw*[]){ |
2410 | &config_noc_clk_src.clkr.hw, |
2411 | }, |
2412 | .num_parents = 1, |
2413 | .flags = CLK_SET_RATE_PARENT, |
2414 | .ops = &clk_branch2_ops, |
2415 | }, |
2416 | }, |
2417 | }; |
2418 | |
2419 | static struct clk_branch gcc_pcie_1_mstr_axi_clk = { |
2420 | .halt_reg = 0x1b88, |
2421 | .clkr = { |
2422 | .enable_reg = 0x1b88, |
2423 | .enable_mask = BIT(0), |
2424 | .hw.init = &(struct clk_init_data){ |
2425 | .name = "gcc_pcie_1_mstr_axi_clk" , |
2426 | .parent_hws = (const struct clk_hw*[]){ |
2427 | &config_noc_clk_src.clkr.hw, |
2428 | }, |
2429 | .num_parents = 1, |
2430 | .flags = CLK_SET_RATE_PARENT, |
2431 | .ops = &clk_branch2_ops, |
2432 | }, |
2433 | }, |
2434 | }; |
2435 | |
2436 | static struct clk_branch gcc_pcie_1_pipe_clk = { |
2437 | .halt_reg = 0x1b94, |
2438 | .clkr = { |
2439 | .enable_reg = 0x1b94, |
2440 | .enable_mask = BIT(0), |
2441 | .hw.init = &(struct clk_init_data){ |
2442 | .name = "gcc_pcie_1_pipe_clk" , |
2443 | .parent_data = &(const struct clk_parent_data){ |
2444 | .hw = &pcie_1_pipe_clk_src.clkr.hw, |
2445 | }, |
2446 | .num_parents = 1, |
2447 | .flags = CLK_SET_RATE_PARENT, |
2448 | .ops = &clk_branch2_ops, |
2449 | }, |
2450 | }, |
2451 | }; |
2452 | |
2453 | static struct clk_branch gcc_pcie_1_slv_axi_clk = { |
2454 | .halt_reg = 0x1b84, |
2455 | .clkr = { |
2456 | .enable_reg = 0x1b84, |
2457 | .enable_mask = BIT(0), |
2458 | .hw.init = &(struct clk_init_data){ |
2459 | .name = "gcc_pcie_1_slv_axi_clk" , |
2460 | .parent_hws = (const struct clk_hw*[]){ |
2461 | &config_noc_clk_src.clkr.hw, |
2462 | }, |
2463 | .num_parents = 1, |
2464 | .flags = CLK_SET_RATE_PARENT, |
2465 | .ops = &clk_branch2_ops, |
2466 | }, |
2467 | }, |
2468 | }; |
2469 | |
2470 | static struct clk_branch gcc_pdm2_clk = { |
2471 | .halt_reg = 0x0ccc, |
2472 | .clkr = { |
2473 | .enable_reg = 0x0ccc, |
2474 | .enable_mask = BIT(0), |
2475 | .hw.init = &(struct clk_init_data){ |
2476 | .name = "gcc_pdm2_clk" , |
2477 | .parent_hws = (const struct clk_hw*[]){ |
2478 | &pdm2_clk_src.clkr.hw, |
2479 | }, |
2480 | .num_parents = 1, |
2481 | .flags = CLK_SET_RATE_PARENT, |
2482 | .ops = &clk_branch2_ops, |
2483 | }, |
2484 | }, |
2485 | }; |
2486 | |
2487 | static struct clk_branch gcc_pdm_ahb_clk = { |
2488 | .halt_reg = 0x0cc4, |
2489 | .clkr = { |
2490 | .enable_reg = 0x0cc4, |
2491 | .enable_mask = BIT(0), |
2492 | .hw.init = &(struct clk_init_data){ |
2493 | .name = "gcc_pdm_ahb_clk" , |
2494 | .parent_hws = (const struct clk_hw*[]){ |
2495 | &periph_noc_clk_src.clkr.hw, |
2496 | }, |
2497 | .num_parents = 1, |
2498 | .ops = &clk_branch2_ops, |
2499 | }, |
2500 | }, |
2501 | }; |
2502 | |
2503 | static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = { |
2504 | .halt_reg = 0x01a4, |
2505 | .clkr = { |
2506 | .enable_reg = 0x01a4, |
2507 | .enable_mask = BIT(0), |
2508 | .hw.init = &(struct clk_init_data){ |
2509 | .name = "gcc_periph_noc_usb_hsic_ahb_clk" , |
2510 | .parent_hws = (const struct clk_hw*[]){ |
2511 | &usb_hsic_ahb_clk_src.clkr.hw, |
2512 | }, |
2513 | .num_parents = 1, |
2514 | .flags = CLK_SET_RATE_PARENT, |
2515 | .ops = &clk_branch2_ops, |
2516 | }, |
2517 | }, |
2518 | }; |
2519 | |
2520 | static struct clk_branch gcc_prng_ahb_clk = { |
2521 | .halt_reg = 0x0d04, |
2522 | .halt_check = BRANCH_HALT_VOTED, |
2523 | .clkr = { |
2524 | .enable_reg = 0x1484, |
2525 | .enable_mask = BIT(13), |
2526 | .hw.init = &(struct clk_init_data){ |
2527 | .name = "gcc_prng_ahb_clk" , |
2528 | .parent_hws = (const struct clk_hw*[]){ |
2529 | &periph_noc_clk_src.clkr.hw, |
2530 | }, |
2531 | .num_parents = 1, |
2532 | .ops = &clk_branch2_ops, |
2533 | }, |
2534 | }, |
2535 | }; |
2536 | |
2537 | static struct clk_branch gcc_sata_asic0_clk = { |
2538 | .halt_reg = 0x1c54, |
2539 | .clkr = { |
2540 | .enable_reg = 0x1c54, |
2541 | .enable_mask = BIT(0), |
2542 | .hw.init = &(struct clk_init_data){ |
2543 | .name = "gcc_sata_asic0_clk" , |
2544 | .parent_hws = (const struct clk_hw*[]){ |
2545 | &sata_asic0_clk_src.clkr.hw, |
2546 | }, |
2547 | .num_parents = 1, |
2548 | .flags = CLK_SET_RATE_PARENT, |
2549 | .ops = &clk_branch2_ops, |
2550 | }, |
2551 | }, |
2552 | }; |
2553 | |
2554 | static struct clk_branch gcc_sata_axi_clk = { |
2555 | .halt_reg = 0x1c44, |
2556 | .clkr = { |
2557 | .enable_reg = 0x1c44, |
2558 | .enable_mask = BIT(0), |
2559 | .hw.init = &(struct clk_init_data){ |
2560 | .name = "gcc_sata_axi_clk" , |
2561 | .parent_hws = (const struct clk_hw*[]){ |
2562 | &config_noc_clk_src.clkr.hw, |
2563 | }, |
2564 | .num_parents = 1, |
2565 | .flags = CLK_SET_RATE_PARENT, |
2566 | .ops = &clk_branch2_ops, |
2567 | }, |
2568 | }, |
2569 | }; |
2570 | |
2571 | static struct clk_branch gcc_sata_cfg_ahb_clk = { |
2572 | .halt_reg = 0x1c48, |
2573 | .clkr = { |
2574 | .enable_reg = 0x1c48, |
2575 | .enable_mask = BIT(0), |
2576 | .hw.init = &(struct clk_init_data){ |
2577 | .name = "gcc_sata_cfg_ahb_clk" , |
2578 | .parent_hws = (const struct clk_hw*[]){ |
2579 | &config_noc_clk_src.clkr.hw, |
2580 | }, |
2581 | .num_parents = 1, |
2582 | .flags = CLK_SET_RATE_PARENT, |
2583 | .ops = &clk_branch2_ops, |
2584 | }, |
2585 | }, |
2586 | }; |
2587 | |
2588 | static struct clk_branch gcc_sata_pmalive_clk = { |
2589 | .halt_reg = 0x1c50, |
2590 | .clkr = { |
2591 | .enable_reg = 0x1c50, |
2592 | .enable_mask = BIT(0), |
2593 | .hw.init = &(struct clk_init_data){ |
2594 | .name = "gcc_sata_pmalive_clk" , |
2595 | .parent_hws = (const struct clk_hw*[]){ |
2596 | &sata_pmalive_clk_src.clkr.hw, |
2597 | }, |
2598 | .num_parents = 1, |
2599 | .flags = CLK_SET_RATE_PARENT, |
2600 | .ops = &clk_branch2_ops, |
2601 | }, |
2602 | }, |
2603 | }; |
2604 | |
2605 | static struct clk_branch gcc_sata_rx_clk = { |
2606 | .halt_reg = 0x1c58, |
2607 | .clkr = { |
2608 | .enable_reg = 0x1c58, |
2609 | .enable_mask = BIT(0), |
2610 | .hw.init = &(struct clk_init_data){ |
2611 | .name = "gcc_sata_rx_clk" , |
2612 | .parent_hws = (const struct clk_hw*[]){ |
2613 | &sata_rx_clk_src.clkr.hw, |
2614 | }, |
2615 | .num_parents = 1, |
2616 | .flags = CLK_SET_RATE_PARENT, |
2617 | .ops = &clk_branch2_ops, |
2618 | }, |
2619 | }, |
2620 | }; |
2621 | |
2622 | static struct clk_branch gcc_sata_rx_oob_clk = { |
2623 | .halt_reg = 0x1c4c, |
2624 | .clkr = { |
2625 | .enable_reg = 0x1c4c, |
2626 | .enable_mask = BIT(0), |
2627 | .hw.init = &(struct clk_init_data){ |
2628 | .name = "gcc_sata_rx_oob_clk" , |
2629 | .parent_hws = (const struct clk_hw*[]){ |
2630 | &sata_rx_oob_clk_src.clkr.hw, |
2631 | }, |
2632 | .num_parents = 1, |
2633 | .flags = CLK_SET_RATE_PARENT, |
2634 | .ops = &clk_branch2_ops, |
2635 | }, |
2636 | }, |
2637 | }; |
2638 | |
2639 | static struct clk_branch gcc_sdcc1_ahb_clk = { |
2640 | .halt_reg = 0x04c8, |
2641 | .clkr = { |
2642 | .enable_reg = 0x04c8, |
2643 | .enable_mask = BIT(0), |
2644 | .hw.init = &(struct clk_init_data){ |
2645 | .name = "gcc_sdcc1_ahb_clk" , |
2646 | .parent_hws = (const struct clk_hw*[]){ |
2647 | &periph_noc_clk_src.clkr.hw, |
2648 | }, |
2649 | .num_parents = 1, |
2650 | .ops = &clk_branch2_ops, |
2651 | }, |
2652 | }, |
2653 | }; |
2654 | |
2655 | static struct clk_branch gcc_sdcc1_apps_clk = { |
2656 | .halt_reg = 0x04c4, |
2657 | .clkr = { |
2658 | .enable_reg = 0x04c4, |
2659 | .enable_mask = BIT(0), |
2660 | .hw.init = &(struct clk_init_data){ |
2661 | .name = "gcc_sdcc1_apps_clk" , |
2662 | .parent_hws = (const struct clk_hw*[]){ |
2663 | &sdcc1_apps_clk_src.clkr.hw, |
2664 | }, |
2665 | .num_parents = 1, |
2666 | .flags = CLK_SET_RATE_PARENT, |
2667 | .ops = &clk_branch2_ops, |
2668 | }, |
2669 | }, |
2670 | }; |
2671 | |
2672 | static struct clk_branch gcc_sdcc1_cdccal_ff_clk = { |
2673 | .halt_reg = 0x04e8, |
2674 | .clkr = { |
2675 | .enable_reg = 0x04e8, |
2676 | .enable_mask = BIT(0), |
2677 | .hw.init = &(struct clk_init_data){ |
2678 | .name = "gcc_sdcc1_cdccal_ff_clk" , |
2679 | .parent_data = (const struct clk_parent_data[]){ |
2680 | { .fw_name = "xo" , .name = "xo_board" } |
2681 | }, |
2682 | .num_parents = 1, |
2683 | .ops = &clk_branch2_ops, |
2684 | }, |
2685 | }, |
2686 | }; |
2687 | |
2688 | static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = { |
2689 | .halt_reg = 0x04e4, |
2690 | .clkr = { |
2691 | .enable_reg = 0x04e4, |
2692 | .enable_mask = BIT(0), |
2693 | .hw.init = &(struct clk_init_data){ |
2694 | .name = "gcc_sdcc1_cdccal_sleep_clk" , |
2695 | .parent_data = (const struct clk_parent_data[]){ |
2696 | { .fw_name = "sleep_clk" , .name = "sleep_clk" } |
2697 | }, |
2698 | .num_parents = 1, |
2699 | .ops = &clk_branch2_ops, |
2700 | }, |
2701 | }, |
2702 | }; |
2703 | |
2704 | static struct clk_branch gcc_sdcc2_ahb_clk = { |
2705 | .halt_reg = 0x0508, |
2706 | .clkr = { |
2707 | .enable_reg = 0x0508, |
2708 | .enable_mask = BIT(0), |
2709 | .hw.init = &(struct clk_init_data){ |
2710 | .name = "gcc_sdcc2_ahb_clk" , |
2711 | .parent_hws = (const struct clk_hw*[]){ |
2712 | &periph_noc_clk_src.clkr.hw, |
2713 | }, |
2714 | .num_parents = 1, |
2715 | .ops = &clk_branch2_ops, |
2716 | }, |
2717 | }, |
2718 | }; |
2719 | |
2720 | static struct clk_branch gcc_sdcc2_apps_clk = { |
2721 | .halt_reg = 0x0504, |
2722 | .clkr = { |
2723 | .enable_reg = 0x0504, |
2724 | .enable_mask = BIT(0), |
2725 | .hw.init = &(struct clk_init_data){ |
2726 | .name = "gcc_sdcc2_apps_clk" , |
2727 | .parent_hws = (const struct clk_hw*[]){ |
2728 | &sdcc2_apps_clk_src.clkr.hw, |
2729 | }, |
2730 | .num_parents = 1, |
2731 | .flags = CLK_SET_RATE_PARENT, |
2732 | .ops = &clk_branch2_ops, |
2733 | }, |
2734 | }, |
2735 | }; |
2736 | |
2737 | static struct clk_branch gcc_sdcc3_ahb_clk = { |
2738 | .halt_reg = 0x0548, |
2739 | .clkr = { |
2740 | .enable_reg = 0x0548, |
2741 | .enable_mask = BIT(0), |
2742 | .hw.init = &(struct clk_init_data){ |
2743 | .name = "gcc_sdcc3_ahb_clk" , |
2744 | .parent_hws = (const struct clk_hw*[]){ |
2745 | &periph_noc_clk_src.clkr.hw, |
2746 | }, |
2747 | .num_parents = 1, |
2748 | .ops = &clk_branch2_ops, |
2749 | }, |
2750 | }, |
2751 | }; |
2752 | |
2753 | static struct clk_branch gcc_sdcc3_apps_clk = { |
2754 | .halt_reg = 0x0544, |
2755 | .clkr = { |
2756 | .enable_reg = 0x0544, |
2757 | .enable_mask = BIT(0), |
2758 | .hw.init = &(struct clk_init_data){ |
2759 | .name = "gcc_sdcc3_apps_clk" , |
2760 | .parent_hws = (const struct clk_hw*[]){ |
2761 | &sdcc3_apps_clk_src.clkr.hw, |
2762 | }, |
2763 | .num_parents = 1, |
2764 | .flags = CLK_SET_RATE_PARENT, |
2765 | .ops = &clk_branch2_ops, |
2766 | }, |
2767 | }, |
2768 | }; |
2769 | |
2770 | static struct clk_branch gcc_sdcc4_ahb_clk = { |
2771 | .halt_reg = 0x0588, |
2772 | .clkr = { |
2773 | .enable_reg = 0x0588, |
2774 | .enable_mask = BIT(0), |
2775 | .hw.init = &(struct clk_init_data){ |
2776 | .name = "gcc_sdcc4_ahb_clk" , |
2777 | .parent_hws = (const struct clk_hw*[]){ |
2778 | &periph_noc_clk_src.clkr.hw, |
2779 | }, |
2780 | .num_parents = 1, |
2781 | .ops = &clk_branch2_ops, |
2782 | }, |
2783 | }, |
2784 | }; |
2785 | |
2786 | static struct clk_branch gcc_sdcc4_apps_clk = { |
2787 | .halt_reg = 0x0584, |
2788 | .clkr = { |
2789 | .enable_reg = 0x0584, |
2790 | .enable_mask = BIT(0), |
2791 | .hw.init = &(struct clk_init_data){ |
2792 | .name = "gcc_sdcc4_apps_clk" , |
2793 | .parent_hws = (const struct clk_hw*[]){ |
2794 | &sdcc4_apps_clk_src.clkr.hw, |
2795 | }, |
2796 | .num_parents = 1, |
2797 | .flags = CLK_SET_RATE_PARENT, |
2798 | .ops = &clk_branch2_ops, |
2799 | }, |
2800 | }, |
2801 | }; |
2802 | |
2803 | static struct clk_branch gcc_sys_noc_ufs_axi_clk = { |
2804 | .halt_reg = 0x013c, |
2805 | .clkr = { |
2806 | .enable_reg = 0x013c, |
2807 | .enable_mask = BIT(0), |
2808 | .hw.init = &(struct clk_init_data){ |
2809 | .name = "gcc_sys_noc_ufs_axi_clk" , |
2810 | .parent_hws = (const struct clk_hw*[]){ |
2811 | &ufs_axi_clk_src.clkr.hw, |
2812 | }, |
2813 | .num_parents = 1, |
2814 | .flags = CLK_SET_RATE_PARENT, |
2815 | .ops = &clk_branch2_ops, |
2816 | }, |
2817 | }, |
2818 | }; |
2819 | |
2820 | static struct clk_branch gcc_sys_noc_usb3_axi_clk = { |
2821 | .halt_reg = 0x0108, |
2822 | .clkr = { |
2823 | .enable_reg = 0x0108, |
2824 | .enable_mask = BIT(0), |
2825 | .hw.init = &(struct clk_init_data){ |
2826 | .name = "gcc_sys_noc_usb3_axi_clk" , |
2827 | .parent_hws = (const struct clk_hw*[]){ |
2828 | &usb30_master_clk_src.clkr.hw, |
2829 | }, |
2830 | .num_parents = 1, |
2831 | .flags = CLK_SET_RATE_PARENT, |
2832 | .ops = &clk_branch2_ops, |
2833 | }, |
2834 | }, |
2835 | }; |
2836 | |
2837 | static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = { |
2838 | .halt_reg = 0x0138, |
2839 | .clkr = { |
2840 | .enable_reg = 0x0138, |
2841 | .enable_mask = BIT(0), |
2842 | .hw.init = &(struct clk_init_data){ |
2843 | .name = "gcc_sys_noc_usb3_sec_axi_clk" , |
2844 | .parent_hws = (const struct clk_hw*[]){ |
2845 | &usb30_sec_master_clk_src.clkr.hw, |
2846 | }, |
2847 | .num_parents = 1, |
2848 | .flags = CLK_SET_RATE_PARENT, |
2849 | .ops = &clk_branch2_ops, |
2850 | }, |
2851 | }, |
2852 | }; |
2853 | |
2854 | static struct clk_branch gcc_tsif_ahb_clk = { |
2855 | .halt_reg = 0x0d84, |
2856 | .clkr = { |
2857 | .enable_reg = 0x0d84, |
2858 | .enable_mask = BIT(0), |
2859 | .hw.init = &(struct clk_init_data){ |
2860 | .name = "gcc_tsif_ahb_clk" , |
2861 | .parent_hws = (const struct clk_hw*[]){ |
2862 | &periph_noc_clk_src.clkr.hw, |
2863 | }, |
2864 | .num_parents = 1, |
2865 | .ops = &clk_branch2_ops, |
2866 | }, |
2867 | }, |
2868 | }; |
2869 | |
2870 | static struct clk_branch gcc_tsif_inactivity_timers_clk = { |
2871 | .halt_reg = 0x0d8c, |
2872 | .clkr = { |
2873 | .enable_reg = 0x0d8c, |
2874 | .enable_mask = BIT(0), |
2875 | .hw.init = &(struct clk_init_data){ |
2876 | .name = "gcc_tsif_inactivity_timers_clk" , |
2877 | .parent_data = &(const struct clk_parent_data){ |
2878 | .fw_name = "sleep_clk" , .name = "sleep_clk" , |
2879 | }, |
2880 | .num_parents = 1, |
2881 | .flags = CLK_SET_RATE_PARENT, |
2882 | .ops = &clk_branch2_ops, |
2883 | }, |
2884 | }, |
2885 | }; |
2886 | |
2887 | static struct clk_branch gcc_tsif_ref_clk = { |
2888 | .halt_reg = 0x0d88, |
2889 | .clkr = { |
2890 | .enable_reg = 0x0d88, |
2891 | .enable_mask = BIT(0), |
2892 | .hw.init = &(struct clk_init_data){ |
2893 | .name = "gcc_tsif_ref_clk" , |
2894 | .parent_hws = (const struct clk_hw*[]){ |
2895 | &tsif_ref_clk_src.clkr.hw, |
2896 | }, |
2897 | .num_parents = 1, |
2898 | .flags = CLK_SET_RATE_PARENT, |
2899 | .ops = &clk_branch2_ops, |
2900 | }, |
2901 | }, |
2902 | }; |
2903 | |
2904 | static struct clk_branch gcc_ufs_ahb_clk = { |
2905 | .halt_reg = 0x1d48, |
2906 | .clkr = { |
2907 | .enable_reg = 0x1d48, |
2908 | .enable_mask = BIT(0), |
2909 | .hw.init = &(struct clk_init_data){ |
2910 | .name = "gcc_ufs_ahb_clk" , |
2911 | .parent_hws = (const struct clk_hw*[]){ |
2912 | &config_noc_clk_src.clkr.hw, |
2913 | }, |
2914 | .num_parents = 1, |
2915 | .flags = CLK_SET_RATE_PARENT, |
2916 | .ops = &clk_branch2_ops, |
2917 | }, |
2918 | }, |
2919 | }; |
2920 | |
2921 | static struct clk_branch gcc_ufs_axi_clk = { |
2922 | .halt_reg = 0x1d44, |
2923 | .clkr = { |
2924 | .enable_reg = 0x1d44, |
2925 | .enable_mask = BIT(0), |
2926 | .hw.init = &(struct clk_init_data){ |
2927 | .name = "gcc_ufs_axi_clk" , |
2928 | .parent_hws = (const struct clk_hw*[]){ |
2929 | &ufs_axi_clk_src.clkr.hw, |
2930 | }, |
2931 | .num_parents = 1, |
2932 | .flags = CLK_SET_RATE_PARENT, |
2933 | .ops = &clk_branch2_ops, |
2934 | }, |
2935 | }, |
2936 | }; |
2937 | |
2938 | static struct clk_branch gcc_ufs_rx_cfg_clk = { |
2939 | .halt_reg = 0x1d50, |
2940 | .clkr = { |
2941 | .enable_reg = 0x1d50, |
2942 | .enable_mask = BIT(0), |
2943 | .hw.init = &(struct clk_init_data){ |
2944 | .name = "gcc_ufs_rx_cfg_clk" , |
2945 | .parent_hws = (const struct clk_hw*[]){ |
2946 | &ufs_axi_clk_src.clkr.hw, |
2947 | }, |
2948 | .num_parents = 1, |
2949 | .flags = CLK_SET_RATE_PARENT, |
2950 | .ops = &clk_branch2_ops, |
2951 | }, |
2952 | }, |
2953 | }; |
2954 | |
2955 | static struct clk_branch gcc_ufs_rx_symbol_0_clk = { |
2956 | .halt_reg = 0x1d5c, |
2957 | .clkr = { |
2958 | .enable_reg = 0x1d5c, |
2959 | .enable_mask = BIT(0), |
2960 | .hw.init = &(struct clk_init_data){ |
2961 | .name = "gcc_ufs_rx_symbol_0_clk" , |
2962 | .parent_data = &(const struct clk_parent_data){ |
2963 | .fw_name = "ufs_rx_symbol_0_clk_src" , .name = "ufs_rx_symbol_0_clk_src" , |
2964 | }, |
2965 | .num_parents = 1, |
2966 | .flags = CLK_SET_RATE_PARENT, |
2967 | .ops = &clk_branch2_ops, |
2968 | }, |
2969 | }, |
2970 | }; |
2971 | |
2972 | static struct clk_branch gcc_ufs_rx_symbol_1_clk = { |
2973 | .halt_reg = 0x1d60, |
2974 | .clkr = { |
2975 | .enable_reg = 0x1d60, |
2976 | .enable_mask = BIT(0), |
2977 | .hw.init = &(struct clk_init_data){ |
2978 | .name = "gcc_ufs_rx_symbol_1_clk" , |
2979 | .parent_data = &(const struct clk_parent_data){ |
2980 | .fw_name = "ufs_rx_symbol_1_clk_src" , .name = "ufs_rx_symbol_1_clk_src" , |
2981 | }, |
2982 | .num_parents = 1, |
2983 | .flags = CLK_SET_RATE_PARENT, |
2984 | .ops = &clk_branch2_ops, |
2985 | }, |
2986 | }, |
2987 | }; |
2988 | |
2989 | static struct clk_branch gcc_ufs_tx_cfg_clk = { |
2990 | .halt_reg = 0x1d4c, |
2991 | .clkr = { |
2992 | .enable_reg = 0x1d4c, |
2993 | .enable_mask = BIT(0), |
2994 | .hw.init = &(struct clk_init_data){ |
2995 | .name = "gcc_ufs_tx_cfg_clk" , |
2996 | .parent_hws = (const struct clk_hw*[]){ |
2997 | &ufs_axi_clk_src.clkr.hw, |
2998 | }, |
2999 | .num_parents = 1, |
3000 | .flags = CLK_SET_RATE_PARENT, |
3001 | .ops = &clk_branch2_ops, |
3002 | }, |
3003 | }, |
3004 | }; |
3005 | |
3006 | static struct clk_branch gcc_ufs_tx_symbol_0_clk = { |
3007 | .halt_reg = 0x1d54, |
3008 | .clkr = { |
3009 | .enable_reg = 0x1d54, |
3010 | .enable_mask = BIT(0), |
3011 | .hw.init = &(struct clk_init_data){ |
3012 | .name = "gcc_ufs_tx_symbol_0_clk" , |
3013 | .parent_data = &(const struct clk_parent_data){ |
3014 | .fw_name = "ufs_tx_symbol_0_clk_src" , .name = "ufs_tx_symbol_0_clk_src" , |
3015 | }, |
3016 | .num_parents = 1, |
3017 | .flags = CLK_SET_RATE_PARENT, |
3018 | .ops = &clk_branch2_ops, |
3019 | }, |
3020 | }, |
3021 | }; |
3022 | |
3023 | static struct clk_branch gcc_ufs_tx_symbol_1_clk = { |
3024 | .halt_reg = 0x1d58, |
3025 | .clkr = { |
3026 | .enable_reg = 0x1d58, |
3027 | .enable_mask = BIT(0), |
3028 | .hw.init = &(struct clk_init_data){ |
3029 | .name = "gcc_ufs_tx_symbol_1_clk" , |
3030 | .parent_data = &(const struct clk_parent_data){ |
3031 | .fw_name = "ufs_tx_symbol_1_clk_src" , .name = "ufs_tx_symbol_1_clk_src" , |
3032 | }, |
3033 | .num_parents = 1, |
3034 | .flags = CLK_SET_RATE_PARENT, |
3035 | .ops = &clk_branch2_ops, |
3036 | }, |
3037 | }, |
3038 | }; |
3039 | |
3040 | static struct clk_branch gcc_usb2a_phy_sleep_clk = { |
3041 | .halt_reg = 0x04ac, |
3042 | .clkr = { |
3043 | .enable_reg = 0x04ac, |
3044 | .enable_mask = BIT(0), |
3045 | .hw.init = &(struct clk_init_data){ |
3046 | .name = "gcc_usb2a_phy_sleep_clk" , |
3047 | .parent_data = &(const struct clk_parent_data){ |
3048 | .fw_name = "sleep_clk" , .name = "sleep_clk" , |
3049 | }, |
3050 | .num_parents = 1, |
3051 | .ops = &clk_branch2_ops, |
3052 | }, |
3053 | }, |
3054 | }; |
3055 | |
3056 | static struct clk_branch gcc_usb2b_phy_sleep_clk = { |
3057 | .halt_reg = 0x04b4, |
3058 | .clkr = { |
3059 | .enable_reg = 0x04b4, |
3060 | .enable_mask = BIT(0), |
3061 | .hw.init = &(struct clk_init_data){ |
3062 | .name = "gcc_usb2b_phy_sleep_clk" , |
3063 | .parent_data = &(const struct clk_parent_data){ |
3064 | .fw_name = "sleep_clk" , .name = "sleep_clk" , |
3065 | }, |
3066 | .num_parents = 1, |
3067 | .ops = &clk_branch2_ops, |
3068 | }, |
3069 | }, |
3070 | }; |
3071 | |
3072 | static struct clk_branch gcc_usb30_master_clk = { |
3073 | .halt_reg = 0x03c8, |
3074 | .clkr = { |
3075 | .enable_reg = 0x03c8, |
3076 | .enable_mask = BIT(0), |
3077 | .hw.init = &(struct clk_init_data){ |
3078 | .name = "gcc_usb30_master_clk" , |
3079 | .parent_hws = (const struct clk_hw*[]){ |
3080 | &usb30_master_clk_src.clkr.hw, |
3081 | }, |
3082 | .num_parents = 1, |
3083 | .flags = CLK_SET_RATE_PARENT, |
3084 | .ops = &clk_branch2_ops, |
3085 | }, |
3086 | }, |
3087 | }; |
3088 | |
3089 | static struct clk_branch gcc_usb30_sec_master_clk = { |
3090 | .halt_reg = 0x1bc8, |
3091 | .clkr = { |
3092 | .enable_reg = 0x1bc8, |
3093 | .enable_mask = BIT(0), |
3094 | .hw.init = &(struct clk_init_data){ |
3095 | .name = "gcc_usb30_sec_master_clk" , |
3096 | .parent_hws = (const struct clk_hw*[]){ |
3097 | &usb30_sec_master_clk_src.clkr.hw, |
3098 | }, |
3099 | .num_parents = 1, |
3100 | .flags = CLK_SET_RATE_PARENT, |
3101 | .ops = &clk_branch2_ops, |
3102 | }, |
3103 | }, |
3104 | }; |
3105 | |
3106 | static struct clk_branch gcc_usb30_mock_utmi_clk = { |
3107 | .halt_reg = 0x03d0, |
3108 | .clkr = { |
3109 | .enable_reg = 0x03d0, |
3110 | .enable_mask = BIT(0), |
3111 | .hw.init = &(struct clk_init_data){ |
3112 | .name = "gcc_usb30_mock_utmi_clk" , |
3113 | .parent_hws = (const struct clk_hw*[]){ |
3114 | &usb30_mock_utmi_clk_src.clkr.hw, |
3115 | }, |
3116 | .num_parents = 1, |
3117 | .flags = CLK_SET_RATE_PARENT, |
3118 | .ops = &clk_branch2_ops, |
3119 | }, |
3120 | }, |
3121 | }; |
3122 | |
3123 | static struct clk_branch gcc_usb30_sleep_clk = { |
3124 | .halt_reg = 0x03cc, |
3125 | .clkr = { |
3126 | .enable_reg = 0x03cc, |
3127 | .enable_mask = BIT(0), |
3128 | .hw.init = &(struct clk_init_data){ |
3129 | .name = "gcc_usb30_sleep_clk" , |
3130 | .parent_data = &(const struct clk_parent_data){ |
3131 | .fw_name = "sleep_clk" , .name = "sleep_clk" , |
3132 | }, |
3133 | .num_parents = 1, |
3134 | .ops = &clk_branch2_ops, |
3135 | }, |
3136 | }, |
3137 | }; |
3138 | |
3139 | static struct clk_branch gcc_usb_hs_ahb_clk = { |
3140 | .halt_reg = 0x0488, |
3141 | .clkr = { |
3142 | .enable_reg = 0x0488, |
3143 | .enable_mask = BIT(0), |
3144 | .hw.init = &(struct clk_init_data){ |
3145 | .name = "gcc_usb_hs_ahb_clk" , |
3146 | .parent_hws = (const struct clk_hw*[]){ |
3147 | &periph_noc_clk_src.clkr.hw, |
3148 | }, |
3149 | .num_parents = 1, |
3150 | .ops = &clk_branch2_ops, |
3151 | }, |
3152 | }, |
3153 | }; |
3154 | |
3155 | static struct clk_branch gcc_usb_hs_inactivity_timers_clk = { |
3156 | .halt_reg = 0x048c, |
3157 | .clkr = { |
3158 | .enable_reg = 0x048c, |
3159 | .enable_mask = BIT(0), |
3160 | .hw.init = &(struct clk_init_data){ |
3161 | .name = "gcc_usb_hs_inactivity_timers_clk" , |
3162 | .parent_data = &(const struct clk_parent_data){ |
3163 | .fw_name = "sleep_clk" , .name = "sleep_clk" , |
3164 | }, |
3165 | .num_parents = 1, |
3166 | .flags = CLK_SET_RATE_PARENT, |
3167 | .ops = &clk_branch2_ops, |
3168 | }, |
3169 | }, |
3170 | }; |
3171 | |
3172 | static struct clk_branch gcc_usb_hs_system_clk = { |
3173 | .halt_reg = 0x0484, |
3174 | .clkr = { |
3175 | .enable_reg = 0x0484, |
3176 | .enable_mask = BIT(0), |
3177 | .hw.init = &(struct clk_init_data){ |
3178 | .name = "gcc_usb_hs_system_clk" , |
3179 | .parent_hws = (const struct clk_hw*[]){ |
3180 | &usb_hs_system_clk_src.clkr.hw, |
3181 | }, |
3182 | .num_parents = 1, |
3183 | .flags = CLK_SET_RATE_PARENT, |
3184 | .ops = &clk_branch2_ops, |
3185 | }, |
3186 | }, |
3187 | }; |
3188 | |
3189 | static struct clk_branch gcc_usb_hsic_ahb_clk = { |
3190 | .halt_reg = 0x0408, |
3191 | .clkr = { |
3192 | .enable_reg = 0x0408, |
3193 | .enable_mask = BIT(0), |
3194 | .hw.init = &(struct clk_init_data){ |
3195 | .name = "gcc_usb_hsic_ahb_clk" , |
3196 | .parent_hws = (const struct clk_hw*[]) { |
3197 | &periph_noc_clk_src.clkr.hw, |
3198 | }, |
3199 | .num_parents = 1, |
3200 | .ops = &clk_branch2_ops, |
3201 | }, |
3202 | }, |
3203 | }; |
3204 | |
3205 | static struct clk_branch gcc_usb_hsic_clk = { |
3206 | .halt_reg = 0x0410, |
3207 | .clkr = { |
3208 | .enable_reg = 0x0410, |
3209 | .enable_mask = BIT(0), |
3210 | .hw.init = &(struct clk_init_data){ |
3211 | .name = "gcc_usb_hsic_clk" , |
3212 | .parent_hws = (const struct clk_hw*[]){ |
3213 | &usb_hsic_clk_src.clkr.hw, |
3214 | }, |
3215 | .num_parents = 1, |
3216 | .flags = CLK_SET_RATE_PARENT, |
3217 | .ops = &clk_branch2_ops, |
3218 | }, |
3219 | }, |
3220 | }; |
3221 | |
3222 | static struct clk_branch gcc_usb_hsic_io_cal_clk = { |
3223 | .halt_reg = 0x0414, |
3224 | .clkr = { |
3225 | .enable_reg = 0x0414, |
3226 | .enable_mask = BIT(0), |
3227 | .hw.init = &(struct clk_init_data){ |
3228 | .name = "gcc_usb_hsic_io_cal_clk" , |
3229 | .parent_hws = (const struct clk_hw*[]){ |
3230 | &usb_hsic_io_cal_clk_src.clkr.hw, |
3231 | }, |
3232 | .num_parents = 1, |
3233 | .flags = CLK_SET_RATE_PARENT, |
3234 | .ops = &clk_branch2_ops, |
3235 | }, |
3236 | }, |
3237 | }; |
3238 | |
3239 | static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = { |
3240 | .halt_reg = 0x0418, |
3241 | .clkr = { |
3242 | .enable_reg = 0x0418, |
3243 | .enable_mask = BIT(0), |
3244 | .hw.init = &(struct clk_init_data){ |
3245 | .name = "gcc_usb_hsic_io_cal_sleep_clk" , |
3246 | .parent_data = &(const struct clk_parent_data){ |
3247 | .fw_name = "sleep_clk" , .name = "sleep_clk" , |
3248 | }, |
3249 | .num_parents = 1, |
3250 | .ops = &clk_branch2_ops, |
3251 | }, |
3252 | }, |
3253 | }; |
3254 | |
3255 | static struct clk_branch gcc_usb_hsic_system_clk = { |
3256 | .halt_reg = 0x040c, |
3257 | .clkr = { |
3258 | .enable_reg = 0x040c, |
3259 | .enable_mask = BIT(0), |
3260 | .hw.init = &(struct clk_init_data){ |
3261 | .name = "gcc_usb_hsic_system_clk" , |
3262 | .parent_hws = (const struct clk_hw*[]){ |
3263 | &usb_hsic_system_clk_src.clkr.hw, |
3264 | }, |
3265 | .num_parents = 1, |
3266 | .flags = CLK_SET_RATE_PARENT, |
3267 | .ops = &clk_branch2_ops, |
3268 | }, |
3269 | }, |
3270 | }; |
3271 | |
3272 | static struct gdsc usb_hs_hsic_gdsc = { |
3273 | .gdscr = 0x404, |
3274 | .pd = { |
3275 | .name = "usb_hs_hsic" , |
3276 | }, |
3277 | .pwrsts = PWRSTS_OFF_ON, |
3278 | }; |
3279 | |
3280 | static struct gdsc pcie0_gdsc = { |
3281 | .gdscr = 0x1ac4, |
3282 | .pd = { |
3283 | .name = "pcie0" , |
3284 | }, |
3285 | .pwrsts = PWRSTS_OFF_ON, |
3286 | }; |
3287 | |
3288 | static struct gdsc pcie1_gdsc = { |
3289 | .gdscr = 0x1b44, |
3290 | .pd = { |
3291 | .name = "pcie1" , |
3292 | }, |
3293 | .pwrsts = PWRSTS_OFF_ON, |
3294 | }; |
3295 | |
3296 | static struct gdsc usb30_gdsc = { |
3297 | .gdscr = 0x1e84, |
3298 | .pd = { |
3299 | .name = "usb30" , |
3300 | }, |
3301 | .pwrsts = PWRSTS_OFF_ON, |
3302 | }; |
3303 | |
3304 | static struct clk_regmap *gcc_apq8084_clocks[] = { |
3305 | [GPLL0] = &gpll0.clkr, |
3306 | [GPLL0_VOTE] = &gpll0_vote, |
3307 | [GPLL1] = &gpll1.clkr, |
3308 | [GPLL1_VOTE] = &gpll1_vote, |
3309 | [GPLL4] = &gpll4.clkr, |
3310 | [GPLL4_VOTE] = &gpll4_vote, |
3311 | [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, |
3312 | [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, |
3313 | [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, |
3314 | [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, |
3315 | [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, |
3316 | [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr, |
3317 | [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr, |
3318 | [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, |
3319 | [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, |
3320 | [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, |
3321 | [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, |
3322 | [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, |
3323 | [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, |
3324 | [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, |
3325 | [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, |
3326 | [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, |
3327 | [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, |
3328 | [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, |
3329 | [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, |
3330 | [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, |
3331 | [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, |
3332 | [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, |
3333 | [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, |
3334 | [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, |
3335 | [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, |
3336 | [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, |
3337 | [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, |
3338 | [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, |
3339 | [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, |
3340 | [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, |
3341 | [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, |
3342 | [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, |
3343 | [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, |
3344 | [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, |
3345 | [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, |
3346 | [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, |
3347 | [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, |
3348 | [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, |
3349 | [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, |
3350 | [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, |
3351 | [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, |
3352 | [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, |
3353 | [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, |
3354 | [CE1_CLK_SRC] = &ce1_clk_src.clkr, |
3355 | [CE2_CLK_SRC] = &ce2_clk_src.clkr, |
3356 | [CE3_CLK_SRC] = &ce3_clk_src.clkr, |
3357 | [GP1_CLK_SRC] = &gp1_clk_src.clkr, |
3358 | [GP2_CLK_SRC] = &gp2_clk_src.clkr, |
3359 | [GP3_CLK_SRC] = &gp3_clk_src.clkr, |
3360 | [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, |
3361 | [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, |
3362 | [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr, |
3363 | [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr, |
3364 | [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, |
3365 | [SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr, |
3366 | [SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr, |
3367 | [SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr, |
3368 | [SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr, |
3369 | [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, |
3370 | [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, |
3371 | [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, |
3372 | [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, |
3373 | [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, |
3374 | [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, |
3375 | [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr, |
3376 | [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, |
3377 | [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, |
3378 | [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, |
3379 | [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr, |
3380 | [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, |
3381 | [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, |
3382 | [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, |
3383 | [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, |
3384 | [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, |
3385 | [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, |
3386 | [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, |
3387 | [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, |
3388 | [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, |
3389 | [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, |
3390 | [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, |
3391 | [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, |
3392 | [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, |
3393 | [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, |
3394 | [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, |
3395 | [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, |
3396 | [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, |
3397 | [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, |
3398 | [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, |
3399 | [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, |
3400 | [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, |
3401 | [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, |
3402 | [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, |
3403 | [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, |
3404 | [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, |
3405 | [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, |
3406 | [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, |
3407 | [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, |
3408 | [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, |
3409 | [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, |
3410 | [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, |
3411 | [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, |
3412 | [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, |
3413 | [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, |
3414 | [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, |
3415 | [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, |
3416 | [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, |
3417 | [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, |
3418 | [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, |
3419 | [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, |
3420 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, |
3421 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, |
3422 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, |
3423 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, |
3424 | [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr, |
3425 | [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr, |
3426 | [GCC_CE2_CLK] = &gcc_ce2_clk.clkr, |
3427 | [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr, |
3428 | [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr, |
3429 | [GCC_CE3_CLK] = &gcc_ce3_clk.clkr, |
3430 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, |
3431 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, |
3432 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, |
3433 | [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr, |
3434 | [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, |
3435 | [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, |
3436 | [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, |
3437 | [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, |
3438 | [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, |
3439 | [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, |
3440 | [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, |
3441 | [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, |
3442 | [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, |
3443 | [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, |
3444 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, |
3445 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, |
3446 | [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr, |
3447 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, |
3448 | [GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr, |
3449 | [GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr, |
3450 | [GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr, |
3451 | [GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr, |
3452 | [GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr, |
3453 | [GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr, |
3454 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, |
3455 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, |
3456 | [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr, |
3457 | [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr, |
3458 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, |
3459 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, |
3460 | [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, |
3461 | [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, |
3462 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, |
3463 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, |
3464 | [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, |
3465 | [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, |
3466 | [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr, |
3467 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, |
3468 | [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, |
3469 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, |
3470 | [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, |
3471 | [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, |
3472 | [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, |
3473 | [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, |
3474 | [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, |
3475 | [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, |
3476 | [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, |
3477 | [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, |
3478 | [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, |
3479 | [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr, |
3480 | [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, |
3481 | [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, |
3482 | [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, |
3483 | [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, |
3484 | [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, |
3485 | [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, |
3486 | [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, |
3487 | [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr, |
3488 | [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, |
3489 | [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, |
3490 | [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, |
3491 | [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, |
3492 | [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr, |
3493 | [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr, |
3494 | [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, |
3495 | [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src, |
3496 | }; |
3497 | |
3498 | static struct gdsc *gcc_apq8084_gdscs[] = { |
3499 | [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, |
3500 | [PCIE0_GDSC] = &pcie0_gdsc, |
3501 | [PCIE1_GDSC] = &pcie1_gdsc, |
3502 | [USB30_GDSC] = &usb30_gdsc, |
3503 | }; |
3504 | |
3505 | static const struct qcom_reset_map gcc_apq8084_resets[] = { |
3506 | [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, |
3507 | [GCC_CONFIG_NOC_BCR] = { 0x0140 }, |
3508 | [GCC_PERIPH_NOC_BCR] = { 0x0180 }, |
3509 | [GCC_IMEM_BCR] = { 0x0200 }, |
3510 | [GCC_MMSS_BCR] = { 0x0240 }, |
3511 | [GCC_QDSS_BCR] = { 0x0300 }, |
3512 | [GCC_USB_30_BCR] = { 0x03c0 }, |
3513 | [GCC_USB3_PHY_BCR] = { 0x03fc }, |
3514 | [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, |
3515 | [GCC_USB_HS_BCR] = { 0x0480 }, |
3516 | [GCC_USB2A_PHY_BCR] = { 0x04a8 }, |
3517 | [GCC_USB2B_PHY_BCR] = { 0x04b0 }, |
3518 | [GCC_SDCC1_BCR] = { 0x04c0 }, |
3519 | [GCC_SDCC2_BCR] = { 0x0500 }, |
3520 | [GCC_SDCC3_BCR] = { 0x0540 }, |
3521 | [GCC_SDCC4_BCR] = { 0x0580 }, |
3522 | [GCC_BLSP1_BCR] = { 0x05c0 }, |
3523 | [GCC_BLSP1_QUP1_BCR] = { 0x0640 }, |
3524 | [GCC_BLSP1_UART1_BCR] = { 0x0680 }, |
3525 | [GCC_BLSP1_QUP2_BCR] = { 0x06c0 }, |
3526 | [GCC_BLSP1_UART2_BCR] = { 0x0700 }, |
3527 | [GCC_BLSP1_QUP3_BCR] = { 0x0740 }, |
3528 | [GCC_BLSP1_UART3_BCR] = { 0x0780 }, |
3529 | [GCC_BLSP1_QUP4_BCR] = { 0x07c0 }, |
3530 | [GCC_BLSP1_UART4_BCR] = { 0x0800 }, |
3531 | [GCC_BLSP1_QUP5_BCR] = { 0x0840 }, |
3532 | [GCC_BLSP1_UART5_BCR] = { 0x0880 }, |
3533 | [GCC_BLSP1_QUP6_BCR] = { 0x08c0 }, |
3534 | [GCC_BLSP1_UART6_BCR] = { 0x0900 }, |
3535 | [GCC_BLSP2_BCR] = { 0x0940 }, |
3536 | [GCC_BLSP2_QUP1_BCR] = { 0x0980 }, |
3537 | [GCC_BLSP2_UART1_BCR] = { 0x09c0 }, |
3538 | [GCC_BLSP2_QUP2_BCR] = { 0x0a00 }, |
3539 | [GCC_BLSP2_UART2_BCR] = { 0x0a40 }, |
3540 | [GCC_BLSP2_QUP3_BCR] = { 0x0a80 }, |
3541 | [GCC_BLSP2_UART3_BCR] = { 0x0ac0 }, |
3542 | [GCC_BLSP2_QUP4_BCR] = { 0x0b00 }, |
3543 | [GCC_BLSP2_UART4_BCR] = { 0x0b40 }, |
3544 | [GCC_BLSP2_QUP5_BCR] = { 0x0b80 }, |
3545 | [GCC_BLSP2_UART5_BCR] = { 0x0bc0 }, |
3546 | [GCC_BLSP2_QUP6_BCR] = { 0x0c00 }, |
3547 | [GCC_BLSP2_UART6_BCR] = { 0x0c40 }, |
3548 | [GCC_PDM_BCR] = { 0x0cc0 }, |
3549 | [GCC_PRNG_BCR] = { 0x0d00 }, |
3550 | [GCC_BAM_DMA_BCR] = { 0x0d40 }, |
3551 | [GCC_TSIF_BCR] = { 0x0d80 }, |
3552 | [GCC_TCSR_BCR] = { 0x0dc0 }, |
3553 | [GCC_BOOT_ROM_BCR] = { 0x0e00 }, |
3554 | [GCC_MSG_RAM_BCR] = { 0x0e40 }, |
3555 | [GCC_TLMM_BCR] = { 0x0e80 }, |
3556 | [GCC_MPM_BCR] = { 0x0ec0 }, |
3557 | [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 }, |
3558 | [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 }, |
3559 | [GCC_SEC_CTRL_BCR] = { 0x0f40 }, |
3560 | [GCC_SPMI_BCR] = { 0x0fc0 }, |
3561 | [GCC_SPDM_BCR] = { 0x1000 }, |
3562 | [GCC_CE1_BCR] = { 0x1040 }, |
3563 | [GCC_CE2_BCR] = { 0x1080 }, |
3564 | [GCC_BIMC_BCR] = { 0x1100 }, |
3565 | [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 }, |
3566 | [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 }, |
3567 | [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 }, |
3568 | [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 }, |
3569 | [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 }, |
3570 | [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 }, |
3571 | [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 }, |
3572 | [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 }, |
3573 | [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 }, |
3574 | [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 }, |
3575 | [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 }, |
3576 | [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 }, |
3577 | [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 }, |
3578 | [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 }, |
3579 | [GCC_DEHR_BCR] = { 0x1300 }, |
3580 | [GCC_RBCPR_BCR] = { 0x1380 }, |
3581 | [GCC_MSS_RESTART] = { 0x1680 }, |
3582 | [GCC_LPASS_RESTART] = { 0x16c0 }, |
3583 | [GCC_WCSS_RESTART] = { 0x1700 }, |
3584 | [GCC_VENUS_RESTART] = { 0x1740 }, |
3585 | [GCC_COPSS_SMMU_BCR] = { 0x1a40 }, |
3586 | [GCC_SPSS_BCR] = { 0x1a80 }, |
3587 | [GCC_PCIE_0_BCR] = { 0x1ac0 }, |
3588 | [GCC_PCIE_0_PHY_BCR] = { 0x1b00 }, |
3589 | [GCC_PCIE_1_BCR] = { 0x1b40 }, |
3590 | [GCC_PCIE_1_PHY_BCR] = { 0x1b80 }, |
3591 | [GCC_USB_30_SEC_BCR] = { 0x1bc0 }, |
3592 | [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc }, |
3593 | [GCC_SATA_BCR] = { 0x1c40 }, |
3594 | [GCC_CE3_BCR] = { 0x1d00 }, |
3595 | [GCC_UFS_BCR] = { 0x1d40 }, |
3596 | [GCC_USB30_PHY_COM_BCR] = { 0x1e80 }, |
3597 | }; |
3598 | |
3599 | static const struct regmap_config gcc_apq8084_regmap_config = { |
3600 | .reg_bits = 32, |
3601 | .reg_stride = 4, |
3602 | .val_bits = 32, |
3603 | .max_register = 0x1fc0, |
3604 | .fast_io = true, |
3605 | }; |
3606 | |
3607 | static const struct qcom_cc_desc gcc_apq8084_desc = { |
3608 | .config = &gcc_apq8084_regmap_config, |
3609 | .clks = gcc_apq8084_clocks, |
3610 | .num_clks = ARRAY_SIZE(gcc_apq8084_clocks), |
3611 | .resets = gcc_apq8084_resets, |
3612 | .num_resets = ARRAY_SIZE(gcc_apq8084_resets), |
3613 | .gdscs = gcc_apq8084_gdscs, |
3614 | .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs), |
3615 | }; |
3616 | |
3617 | static const struct of_device_id gcc_apq8084_match_table[] = { |
3618 | { .compatible = "qcom,gcc-apq8084" }, |
3619 | { } |
3620 | }; |
3621 | MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table); |
3622 | |
3623 | static int gcc_apq8084_probe(struct platform_device *pdev) |
3624 | { |
3625 | int ret; |
3626 | struct device *dev = &pdev->dev; |
3627 | |
3628 | ret = qcom_cc_register_board_clk(dev, path: "xo_board" , name: "xo" , rate: 19200000); |
3629 | if (ret) |
3630 | return ret; |
3631 | |
3632 | ret = qcom_cc_register_sleep_clk(dev); |
3633 | if (ret) |
3634 | return ret; |
3635 | |
3636 | return qcom_cc_probe(pdev, desc: &gcc_apq8084_desc); |
3637 | } |
3638 | |
3639 | static struct platform_driver gcc_apq8084_driver = { |
3640 | .probe = gcc_apq8084_probe, |
3641 | .driver = { |
3642 | .name = "gcc-apq8084" , |
3643 | .of_match_table = gcc_apq8084_match_table, |
3644 | }, |
3645 | }; |
3646 | |
3647 | static int __init gcc_apq8084_init(void) |
3648 | { |
3649 | return platform_driver_register(&gcc_apq8084_driver); |
3650 | } |
3651 | core_initcall(gcc_apq8084_init); |
3652 | |
3653 | static void __exit gcc_apq8084_exit(void) |
3654 | { |
3655 | platform_driver_unregister(&gcc_apq8084_driver); |
3656 | } |
3657 | module_exit(gcc_apq8084_exit); |
3658 | |
3659 | MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver" ); |
3660 | MODULE_LICENSE("GPL v2" ); |
3661 | MODULE_ALIAS("platform:gcc-apq8084" ); |
3662 | |