1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_platform.h>
13#include <linux/clk-provider.h>
14#include <linux/regmap.h>
15#include <linux/reset-controller.h>
16
17#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
18#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
19
20#include "common.h"
21#include "clk-regmap.h"
22#include "clk-pll.h"
23#include "clk-rcg.h"
24#include "clk-branch.h"
25#include "clk-hfpll.h"
26#include "reset.h"
27
28static const struct clk_parent_data gcc_pxo[] = {
29 { .fw_name = "pxo", .name = "pxo" },
30};
31
32static struct clk_pll pll0 = {
33 .l_reg = 0x30c4,
34 .m_reg = 0x30c8,
35 .n_reg = 0x30cc,
36 .config_reg = 0x30d4,
37 .mode_reg = 0x30c0,
38 .status_reg = 0x30d8,
39 .status_bit = 16,
40 .clkr.hw.init = &(struct clk_init_data){
41 .name = "pll0",
42 .parent_data = gcc_pxo,
43 .num_parents = 1,
44 .ops = &clk_pll_ops,
45 },
46};
47
48static struct clk_regmap pll0_vote = {
49 .enable_reg = 0x34c0,
50 .enable_mask = BIT(0),
51 .hw.init = &(struct clk_init_data){
52 .name = "pll0_vote",
53 .parent_hws = (const struct clk_hw*[]){
54 &pll0.clkr.hw,
55 },
56 .num_parents = 1,
57 .ops = &clk_pll_vote_ops,
58 },
59};
60
61static struct clk_pll pll3 = {
62 .l_reg = 0x3164,
63 .m_reg = 0x3168,
64 .n_reg = 0x316c,
65 .config_reg = 0x3174,
66 .mode_reg = 0x3160,
67 .status_reg = 0x3178,
68 .status_bit = 16,
69 .clkr.hw.init = &(struct clk_init_data){
70 .name = "pll3",
71 .parent_data = gcc_pxo,
72 .num_parents = 1,
73 .ops = &clk_pll_ops,
74 },
75};
76
77static struct clk_regmap pll4_vote = {
78 .enable_reg = 0x34c0,
79 .enable_mask = BIT(4),
80 .hw.init = &(struct clk_init_data){
81 .name = "pll4_vote",
82 .parent_data = &(const struct clk_parent_data){
83 .fw_name = "pll4", .name = "pll4",
84 },
85 .num_parents = 1,
86 .ops = &clk_pll_vote_ops,
87 },
88};
89
90static struct clk_pll pll8 = {
91 .l_reg = 0x3144,
92 .m_reg = 0x3148,
93 .n_reg = 0x314c,
94 .config_reg = 0x3154,
95 .mode_reg = 0x3140,
96 .status_reg = 0x3158,
97 .status_bit = 16,
98 .clkr.hw.init = &(struct clk_init_data){
99 .name = "pll8",
100 .parent_data = gcc_pxo,
101 .num_parents = 1,
102 .ops = &clk_pll_ops,
103 },
104};
105
106static struct clk_regmap pll8_vote = {
107 .enable_reg = 0x34c0,
108 .enable_mask = BIT(8),
109 .hw.init = &(struct clk_init_data){
110 .name = "pll8_vote",
111 .parent_hws = (const struct clk_hw*[]){
112 &pll8.clkr.hw,
113 },
114 .num_parents = 1,
115 .ops = &clk_pll_vote_ops,
116 },
117};
118
119static struct hfpll_data hfpll0_data = {
120 .mode_reg = 0x3200,
121 .l_reg = 0x3208,
122 .m_reg = 0x320c,
123 .n_reg = 0x3210,
124 .config_reg = 0x3204,
125 .status_reg = 0x321c,
126 .config_val = 0x7845c665,
127 .droop_reg = 0x3214,
128 .droop_val = 0x0108c000,
129 .min_rate = 600000000UL,
130 .max_rate = 1800000000UL,
131};
132
133static struct clk_hfpll hfpll0 = {
134 .d = &hfpll0_data,
135 .clkr.hw.init = &(struct clk_init_data){
136 .parent_data = gcc_pxo,
137 .num_parents = 1,
138 .name = "hfpll0",
139 .ops = &clk_ops_hfpll,
140 .flags = CLK_IGNORE_UNUSED,
141 },
142 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
143};
144
145static struct hfpll_data hfpll1_data = {
146 .mode_reg = 0x3240,
147 .l_reg = 0x3248,
148 .m_reg = 0x324c,
149 .n_reg = 0x3250,
150 .config_reg = 0x3244,
151 .status_reg = 0x325c,
152 .config_val = 0x7845c665,
153 .droop_reg = 0x3314,
154 .droop_val = 0x0108c000,
155 .min_rate = 600000000UL,
156 .max_rate = 1800000000UL,
157};
158
159static struct clk_hfpll hfpll1 = {
160 .d = &hfpll1_data,
161 .clkr.hw.init = &(struct clk_init_data){
162 .parent_data = gcc_pxo,
163 .num_parents = 1,
164 .name = "hfpll1",
165 .ops = &clk_ops_hfpll,
166 .flags = CLK_IGNORE_UNUSED,
167 },
168 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
169};
170
171static struct hfpll_data hfpll_l2_data = {
172 .mode_reg = 0x3300,
173 .l_reg = 0x3308,
174 .m_reg = 0x330c,
175 .n_reg = 0x3310,
176 .config_reg = 0x3304,
177 .status_reg = 0x331c,
178 .config_val = 0x7845c665,
179 .droop_reg = 0x3314,
180 .droop_val = 0x0108c000,
181 .min_rate = 600000000UL,
182 .max_rate = 1800000000UL,
183};
184
185static struct clk_hfpll hfpll_l2 = {
186 .d = &hfpll_l2_data,
187 .clkr.hw.init = &(struct clk_init_data){
188 .parent_data = gcc_pxo,
189 .num_parents = 1,
190 .name = "hfpll_l2",
191 .ops = &clk_ops_hfpll,
192 .flags = CLK_IGNORE_UNUSED,
193 },
194 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
195};
196
197static struct clk_pll pll14 = {
198 .l_reg = 0x31c4,
199 .m_reg = 0x31c8,
200 .n_reg = 0x31cc,
201 .config_reg = 0x31d4,
202 .mode_reg = 0x31c0,
203 .status_reg = 0x31d8,
204 .status_bit = 16,
205 .clkr.hw.init = &(struct clk_init_data){
206 .name = "pll14",
207 .parent_data = gcc_pxo,
208 .num_parents = 1,
209 .ops = &clk_pll_ops,
210 },
211};
212
213static struct clk_regmap pll14_vote = {
214 .enable_reg = 0x34c0,
215 .enable_mask = BIT(14),
216 .hw.init = &(struct clk_init_data){
217 .name = "pll14_vote",
218 .parent_hws = (const struct clk_hw*[]){
219 &pll14.clkr.hw,
220 },
221 .num_parents = 1,
222 .ops = &clk_pll_vote_ops,
223 },
224};
225
226#define NSS_PLL_RATE(f, _l, _m, _n, i) \
227 { \
228 .freq = f, \
229 .l = _l, \
230 .m = _m, \
231 .n = _n, \
232 .ibits = i, \
233 }
234
235static struct pll_freq_tbl pll18_freq_tbl[] = {
236 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
237 NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
238 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
239 NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
240};
241
242static struct clk_pll pll18 = {
243 .l_reg = 0x31a4,
244 .m_reg = 0x31a8,
245 .n_reg = 0x31ac,
246 .config_reg = 0x31b4,
247 .mode_reg = 0x31a0,
248 .status_reg = 0x31b8,
249 .status_bit = 16,
250 .post_div_shift = 16,
251 .post_div_width = 1,
252 .freq_tbl = pll18_freq_tbl,
253 .clkr.hw.init = &(struct clk_init_data){
254 .name = "pll18",
255 .parent_data = gcc_pxo,
256 .num_parents = 1,
257 .ops = &clk_pll_ops,
258 },
259};
260
261static struct clk_pll pll11 = {
262 .l_reg = 0x3184,
263 .m_reg = 0x3188,
264 .n_reg = 0x318c,
265 .config_reg = 0x3194,
266 .mode_reg = 0x3180,
267 .status_reg = 0x3198,
268 .status_bit = 16,
269 .clkr.hw.init = &(struct clk_init_data){
270 .name = "pll11",
271 .parent_data = &(const struct clk_parent_data){
272 .fw_name = "pxo",
273 },
274 .num_parents = 1,
275 .ops = &clk_pll_ops,
276 },
277};
278
279enum {
280 P_PXO,
281 P_PLL8,
282 P_PLL3,
283 P_PLL0,
284 P_CXO,
285 P_PLL14,
286 P_PLL18,
287 P_PLL11,
288};
289
290static const struct parent_map gcc_pxo_pll8_map[] = {
291 { P_PXO, 0 },
292 { P_PLL8, 3 }
293};
294
295static const struct clk_parent_data gcc_pxo_pll8[] = {
296 { .fw_name = "pxo", .name = "pxo" },
297 { .hw = &pll8_vote.hw },
298};
299
300static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
301 { P_PXO, 0 },
302 { P_PLL8, 3 },
303 { P_CXO, 5 }
304};
305
306static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
307 { .fw_name = "pxo", .name = "pxo" },
308 { .hw = &pll8_vote.hw },
309 { .fw_name = "cxo", .name = "cxo" },
310};
311
312static const struct parent_map gcc_pxo_pll3_map[] = {
313 { P_PXO, 0 },
314 { P_PLL3, 1 }
315};
316
317static const struct parent_map gcc_pxo_pll3_sata_map[] = {
318 { P_PXO, 0 },
319 { P_PLL3, 6 }
320};
321
322static const struct clk_parent_data gcc_pxo_pll3[] = {
323 { .fw_name = "pxo", .name = "pxo" },
324 { .hw = &pll3.clkr.hw },
325};
326
327static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
328 { P_PXO, 0 },
329 { P_PLL8, 3 },
330 { P_PLL0, 2 }
331};
332
333static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
334 { .fw_name = "pxo", .name = "pxo" },
335 { .hw = &pll8_vote.hw },
336 { .hw = &pll0_vote.hw },
337};
338
339static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
340 { P_PXO, 0 },
341 { P_PLL8, 4 },
342 { P_PLL0, 2 },
343 { P_PLL14, 5 },
344 { P_PLL18, 1 }
345};
346
347static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
348 { .fw_name = "pxo", .name = "pxo" },
349 { .hw = &pll8_vote.hw },
350 { .hw = &pll0_vote.hw },
351 { .hw = &pll14.clkr.hw },
352 { .hw = &pll18.clkr.hw },
353};
354
355static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
356 { P_PXO, 0 },
357 { P_PLL8, 4 },
358 { P_PLL0, 2 },
359 { P_PLL14, 5 },
360 { P_PLL18, 1 },
361 { P_PLL11, 3 },
362};
363
364static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
365 { .fw_name = "pxo" },
366 { .hw = &pll8_vote.hw },
367 { .hw = &pll0_vote.hw },
368 { .hw = &pll14.clkr.hw },
369 { .hw = &pll18.clkr.hw },
370 { .hw = &pll11.clkr.hw },
371
372};
373
374static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
375 { P_PXO, 0 },
376 { P_PLL3, 6 },
377 { P_PLL0, 2 },
378 { P_PLL14, 5 },
379 { P_PLL18, 1 },
380 { P_PLL11, 3 },
381};
382
383static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
384 { .fw_name = "pxo" },
385 { .hw = &pll3.clkr.hw },
386 { .hw = &pll0_vote.hw },
387 { .hw = &pll14.clkr.hw },
388 { .hw = &pll18.clkr.hw },
389 { .hw = &pll11.clkr.hw },
390
391};
392
393static struct freq_tbl clk_tbl_gsbi_uart[] = {
394 { 1843200, P_PLL8, 2, 6, 625 },
395 { 3686400, P_PLL8, 2, 12, 625 },
396 { 7372800, P_PLL8, 2, 24, 625 },
397 { 14745600, P_PLL8, 2, 48, 625 },
398 { 16000000, P_PLL8, 4, 1, 6 },
399 { 24000000, P_PLL8, 4, 1, 4 },
400 { 32000000, P_PLL8, 4, 1, 3 },
401 { 40000000, P_PLL8, 1, 5, 48 },
402 { 46400000, P_PLL8, 1, 29, 240 },
403 { 48000000, P_PLL8, 4, 1, 2 },
404 { 51200000, P_PLL8, 1, 2, 15 },
405 { 56000000, P_PLL8, 1, 7, 48 },
406 { 58982400, P_PLL8, 1, 96, 625 },
407 { 64000000, P_PLL8, 2, 1, 3 },
408 { }
409};
410
411static struct clk_rcg gsbi1_uart_src = {
412 .ns_reg = 0x29d4,
413 .md_reg = 0x29d0,
414 .mn = {
415 .mnctr_en_bit = 8,
416 .mnctr_reset_bit = 7,
417 .mnctr_mode_shift = 5,
418 .n_val_shift = 16,
419 .m_val_shift = 16,
420 .width = 16,
421 },
422 .p = {
423 .pre_div_shift = 3,
424 .pre_div_width = 2,
425 },
426 .s = {
427 .src_sel_shift = 0,
428 .parent_map = gcc_pxo_pll8_map,
429 },
430 .freq_tbl = clk_tbl_gsbi_uart,
431 .clkr = {
432 .enable_reg = 0x29d4,
433 .enable_mask = BIT(11),
434 .hw.init = &(struct clk_init_data){
435 .name = "gsbi1_uart_src",
436 .parent_data = gcc_pxo_pll8,
437 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
438 .ops = &clk_rcg_ops,
439 .flags = CLK_SET_PARENT_GATE,
440 },
441 },
442};
443
444static struct clk_branch gsbi1_uart_clk = {
445 .halt_reg = 0x2fcc,
446 .halt_bit = 12,
447 .clkr = {
448 .enable_reg = 0x29d4,
449 .enable_mask = BIT(9),
450 .hw.init = &(struct clk_init_data){
451 .name = "gsbi1_uart_clk",
452 .parent_hws = (const struct clk_hw*[]){
453 &gsbi1_uart_src.clkr.hw,
454 },
455 .num_parents = 1,
456 .ops = &clk_branch_ops,
457 .flags = CLK_SET_RATE_PARENT,
458 },
459 },
460};
461
462static struct clk_rcg gsbi2_uart_src = {
463 .ns_reg = 0x29f4,
464 .md_reg = 0x29f0,
465 .mn = {
466 .mnctr_en_bit = 8,
467 .mnctr_reset_bit = 7,
468 .mnctr_mode_shift = 5,
469 .n_val_shift = 16,
470 .m_val_shift = 16,
471 .width = 16,
472 },
473 .p = {
474 .pre_div_shift = 3,
475 .pre_div_width = 2,
476 },
477 .s = {
478 .src_sel_shift = 0,
479 .parent_map = gcc_pxo_pll8_map,
480 },
481 .freq_tbl = clk_tbl_gsbi_uart,
482 .clkr = {
483 .enable_reg = 0x29f4,
484 .enable_mask = BIT(11),
485 .hw.init = &(struct clk_init_data){
486 .name = "gsbi2_uart_src",
487 .parent_data = gcc_pxo_pll8,
488 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
489 .ops = &clk_rcg_ops,
490 .flags = CLK_SET_PARENT_GATE,
491 },
492 },
493};
494
495static struct clk_branch gsbi2_uart_clk = {
496 .halt_reg = 0x2fcc,
497 .halt_bit = 8,
498 .clkr = {
499 .enable_reg = 0x29f4,
500 .enable_mask = BIT(9),
501 .hw.init = &(struct clk_init_data){
502 .name = "gsbi2_uart_clk",
503 .parent_hws = (const struct clk_hw*[]){
504 &gsbi2_uart_src.clkr.hw,
505 },
506 .num_parents = 1,
507 .ops = &clk_branch_ops,
508 .flags = CLK_SET_RATE_PARENT,
509 },
510 },
511};
512
513static struct clk_rcg gsbi4_uart_src = {
514 .ns_reg = 0x2a34,
515 .md_reg = 0x2a30,
516 .mn = {
517 .mnctr_en_bit = 8,
518 .mnctr_reset_bit = 7,
519 .mnctr_mode_shift = 5,
520 .n_val_shift = 16,
521 .m_val_shift = 16,
522 .width = 16,
523 },
524 .p = {
525 .pre_div_shift = 3,
526 .pre_div_width = 2,
527 },
528 .s = {
529 .src_sel_shift = 0,
530 .parent_map = gcc_pxo_pll8_map,
531 },
532 .freq_tbl = clk_tbl_gsbi_uart,
533 .clkr = {
534 .enable_reg = 0x2a34,
535 .enable_mask = BIT(11),
536 .hw.init = &(struct clk_init_data){
537 .name = "gsbi4_uart_src",
538 .parent_data = gcc_pxo_pll8,
539 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
540 .ops = &clk_rcg_ops,
541 .flags = CLK_SET_PARENT_GATE,
542 },
543 },
544};
545
546static struct clk_branch gsbi4_uart_clk = {
547 .halt_reg = 0x2fd0,
548 .halt_bit = 26,
549 .clkr = {
550 .enable_reg = 0x2a34,
551 .enable_mask = BIT(9),
552 .hw.init = &(struct clk_init_data){
553 .name = "gsbi4_uart_clk",
554 .parent_hws = (const struct clk_hw*[]){
555 &gsbi4_uart_src.clkr.hw,
556 },
557 .num_parents = 1,
558 .ops = &clk_branch_ops,
559 .flags = CLK_SET_RATE_PARENT,
560 },
561 },
562};
563
564static struct clk_rcg gsbi5_uart_src = {
565 .ns_reg = 0x2a54,
566 .md_reg = 0x2a50,
567 .mn = {
568 .mnctr_en_bit = 8,
569 .mnctr_reset_bit = 7,
570 .mnctr_mode_shift = 5,
571 .n_val_shift = 16,
572 .m_val_shift = 16,
573 .width = 16,
574 },
575 .p = {
576 .pre_div_shift = 3,
577 .pre_div_width = 2,
578 },
579 .s = {
580 .src_sel_shift = 0,
581 .parent_map = gcc_pxo_pll8_map,
582 },
583 .freq_tbl = clk_tbl_gsbi_uart,
584 .clkr = {
585 .enable_reg = 0x2a54,
586 .enable_mask = BIT(11),
587 .hw.init = &(struct clk_init_data){
588 .name = "gsbi5_uart_src",
589 .parent_data = gcc_pxo_pll8,
590 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
591 .ops = &clk_rcg_ops,
592 .flags = CLK_SET_PARENT_GATE,
593 },
594 },
595};
596
597static struct clk_branch gsbi5_uart_clk = {
598 .halt_reg = 0x2fd0,
599 .halt_bit = 22,
600 .clkr = {
601 .enable_reg = 0x2a54,
602 .enable_mask = BIT(9),
603 .hw.init = &(struct clk_init_data){
604 .name = "gsbi5_uart_clk",
605 .parent_hws = (const struct clk_hw*[]){
606 &gsbi5_uart_src.clkr.hw,
607 },
608 .num_parents = 1,
609 .ops = &clk_branch_ops,
610 .flags = CLK_SET_RATE_PARENT,
611 },
612 },
613};
614
615static struct clk_rcg gsbi6_uart_src = {
616 .ns_reg = 0x2a74,
617 .md_reg = 0x2a70,
618 .mn = {
619 .mnctr_en_bit = 8,
620 .mnctr_reset_bit = 7,
621 .mnctr_mode_shift = 5,
622 .n_val_shift = 16,
623 .m_val_shift = 16,
624 .width = 16,
625 },
626 .p = {
627 .pre_div_shift = 3,
628 .pre_div_width = 2,
629 },
630 .s = {
631 .src_sel_shift = 0,
632 .parent_map = gcc_pxo_pll8_map,
633 },
634 .freq_tbl = clk_tbl_gsbi_uart,
635 .clkr = {
636 .enable_reg = 0x2a74,
637 .enable_mask = BIT(11),
638 .hw.init = &(struct clk_init_data){
639 .name = "gsbi6_uart_src",
640 .parent_data = gcc_pxo_pll8,
641 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
642 .ops = &clk_rcg_ops,
643 .flags = CLK_SET_PARENT_GATE,
644 },
645 },
646};
647
648static struct clk_branch gsbi6_uart_clk = {
649 .halt_reg = 0x2fd0,
650 .halt_bit = 18,
651 .clkr = {
652 .enable_reg = 0x2a74,
653 .enable_mask = BIT(9),
654 .hw.init = &(struct clk_init_data){
655 .name = "gsbi6_uart_clk",
656 .parent_hws = (const struct clk_hw*[]){
657 &gsbi6_uart_src.clkr.hw,
658 },
659 .num_parents = 1,
660 .ops = &clk_branch_ops,
661 .flags = CLK_SET_RATE_PARENT,
662 },
663 },
664};
665
666static struct clk_rcg gsbi7_uart_src = {
667 .ns_reg = 0x2a94,
668 .md_reg = 0x2a90,
669 .mn = {
670 .mnctr_en_bit = 8,
671 .mnctr_reset_bit = 7,
672 .mnctr_mode_shift = 5,
673 .n_val_shift = 16,
674 .m_val_shift = 16,
675 .width = 16,
676 },
677 .p = {
678 .pre_div_shift = 3,
679 .pre_div_width = 2,
680 },
681 .s = {
682 .src_sel_shift = 0,
683 .parent_map = gcc_pxo_pll8_map,
684 },
685 .freq_tbl = clk_tbl_gsbi_uart,
686 .clkr = {
687 .enable_reg = 0x2a94,
688 .enable_mask = BIT(11),
689 .hw.init = &(struct clk_init_data){
690 .name = "gsbi7_uart_src",
691 .parent_data = gcc_pxo_pll8,
692 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
693 .ops = &clk_rcg_ops,
694 .flags = CLK_SET_PARENT_GATE,
695 },
696 },
697};
698
699static struct clk_branch gsbi7_uart_clk = {
700 .halt_reg = 0x2fd0,
701 .halt_bit = 14,
702 .clkr = {
703 .enable_reg = 0x2a94,
704 .enable_mask = BIT(9),
705 .hw.init = &(struct clk_init_data){
706 .name = "gsbi7_uart_clk",
707 .parent_hws = (const struct clk_hw*[]){
708 &gsbi7_uart_src.clkr.hw,
709 },
710 .num_parents = 1,
711 .ops = &clk_branch_ops,
712 .flags = CLK_SET_RATE_PARENT,
713 },
714 },
715};
716
717static struct freq_tbl clk_tbl_gsbi_qup[] = {
718 { 1100000, P_PXO, 1, 2, 49 },
719 { 5400000, P_PXO, 1, 1, 5 },
720 { 10800000, P_PXO, 1, 2, 5 },
721 { 15060000, P_PLL8, 1, 2, 51 },
722 { 24000000, P_PLL8, 4, 1, 4 },
723 { 25000000, P_PXO, 1, 0, 0 },
724 { 25600000, P_PLL8, 1, 1, 15 },
725 { 48000000, P_PLL8, 4, 1, 2 },
726 { 51200000, P_PLL8, 1, 2, 15 },
727 { }
728};
729
730static struct clk_rcg gsbi1_qup_src = {
731 .ns_reg = 0x29cc,
732 .md_reg = 0x29c8,
733 .mn = {
734 .mnctr_en_bit = 8,
735 .mnctr_reset_bit = 7,
736 .mnctr_mode_shift = 5,
737 .n_val_shift = 16,
738 .m_val_shift = 16,
739 .width = 8,
740 },
741 .p = {
742 .pre_div_shift = 3,
743 .pre_div_width = 2,
744 },
745 .s = {
746 .src_sel_shift = 0,
747 .parent_map = gcc_pxo_pll8_map,
748 },
749 .freq_tbl = clk_tbl_gsbi_qup,
750 .clkr = {
751 .enable_reg = 0x29cc,
752 .enable_mask = BIT(11),
753 .hw.init = &(struct clk_init_data){
754 .name = "gsbi1_qup_src",
755 .parent_data = gcc_pxo_pll8,
756 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
757 .ops = &clk_rcg_ops,
758 .flags = CLK_SET_PARENT_GATE,
759 },
760 },
761};
762
763static struct clk_branch gsbi1_qup_clk = {
764 .halt_reg = 0x2fcc,
765 .halt_bit = 11,
766 .clkr = {
767 .enable_reg = 0x29cc,
768 .enable_mask = BIT(9),
769 .hw.init = &(struct clk_init_data){
770 .name = "gsbi1_qup_clk",
771 .parent_hws = (const struct clk_hw*[]){
772 &gsbi1_qup_src.clkr.hw,
773 },
774 .num_parents = 1,
775 .ops = &clk_branch_ops,
776 .flags = CLK_SET_RATE_PARENT,
777 },
778 },
779};
780
781static struct clk_rcg gsbi2_qup_src = {
782 .ns_reg = 0x29ec,
783 .md_reg = 0x29e8,
784 .mn = {
785 .mnctr_en_bit = 8,
786 .mnctr_reset_bit = 7,
787 .mnctr_mode_shift = 5,
788 .n_val_shift = 16,
789 .m_val_shift = 16,
790 .width = 8,
791 },
792 .p = {
793 .pre_div_shift = 3,
794 .pre_div_width = 2,
795 },
796 .s = {
797 .src_sel_shift = 0,
798 .parent_map = gcc_pxo_pll8_map,
799 },
800 .freq_tbl = clk_tbl_gsbi_qup,
801 .clkr = {
802 .enable_reg = 0x29ec,
803 .enable_mask = BIT(11),
804 .hw.init = &(struct clk_init_data){
805 .name = "gsbi2_qup_src",
806 .parent_data = gcc_pxo_pll8,
807 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
808 .ops = &clk_rcg_ops,
809 .flags = CLK_SET_PARENT_GATE,
810 },
811 },
812};
813
814static struct clk_branch gsbi2_qup_clk = {
815 .halt_reg = 0x2fcc,
816 .halt_bit = 6,
817 .clkr = {
818 .enable_reg = 0x29ec,
819 .enable_mask = BIT(9),
820 .hw.init = &(struct clk_init_data){
821 .name = "gsbi2_qup_clk",
822 .parent_hws = (const struct clk_hw*[]){
823 &gsbi2_qup_src.clkr.hw,
824 },
825 .num_parents = 1,
826 .ops = &clk_branch_ops,
827 .flags = CLK_SET_RATE_PARENT,
828 },
829 },
830};
831
832static struct clk_rcg gsbi4_qup_src = {
833 .ns_reg = 0x2a2c,
834 .md_reg = 0x2a28,
835 .mn = {
836 .mnctr_en_bit = 8,
837 .mnctr_reset_bit = 7,
838 .mnctr_mode_shift = 5,
839 .n_val_shift = 16,
840 .m_val_shift = 16,
841 .width = 8,
842 },
843 .p = {
844 .pre_div_shift = 3,
845 .pre_div_width = 2,
846 },
847 .s = {
848 .src_sel_shift = 0,
849 .parent_map = gcc_pxo_pll8_map,
850 },
851 .freq_tbl = clk_tbl_gsbi_qup,
852 .clkr = {
853 .enable_reg = 0x2a2c,
854 .enable_mask = BIT(11),
855 .hw.init = &(struct clk_init_data){
856 .name = "gsbi4_qup_src",
857 .parent_data = gcc_pxo_pll8,
858 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
859 .ops = &clk_rcg_ops,
860 .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
861 },
862 },
863};
864
865static struct clk_branch gsbi4_qup_clk = {
866 .halt_reg = 0x2fd0,
867 .halt_bit = 24,
868 .clkr = {
869 .enable_reg = 0x2a2c,
870 .enable_mask = BIT(9),
871 .hw.init = &(struct clk_init_data){
872 .name = "gsbi4_qup_clk",
873 .parent_hws = (const struct clk_hw*[]){
874 &gsbi4_qup_src.clkr.hw,
875 },
876 .num_parents = 1,
877 .ops = &clk_branch_ops,
878 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
879 },
880 },
881};
882
883static struct clk_rcg gsbi5_qup_src = {
884 .ns_reg = 0x2a4c,
885 .md_reg = 0x2a48,
886 .mn = {
887 .mnctr_en_bit = 8,
888 .mnctr_reset_bit = 7,
889 .mnctr_mode_shift = 5,
890 .n_val_shift = 16,
891 .m_val_shift = 16,
892 .width = 8,
893 },
894 .p = {
895 .pre_div_shift = 3,
896 .pre_div_width = 2,
897 },
898 .s = {
899 .src_sel_shift = 0,
900 .parent_map = gcc_pxo_pll8_map,
901 },
902 .freq_tbl = clk_tbl_gsbi_qup,
903 .clkr = {
904 .enable_reg = 0x2a4c,
905 .enable_mask = BIT(11),
906 .hw.init = &(struct clk_init_data){
907 .name = "gsbi5_qup_src",
908 .parent_data = gcc_pxo_pll8,
909 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
910 .ops = &clk_rcg_ops,
911 .flags = CLK_SET_PARENT_GATE,
912 },
913 },
914};
915
916static struct clk_branch gsbi5_qup_clk = {
917 .halt_reg = 0x2fd0,
918 .halt_bit = 20,
919 .clkr = {
920 .enable_reg = 0x2a4c,
921 .enable_mask = BIT(9),
922 .hw.init = &(struct clk_init_data){
923 .name = "gsbi5_qup_clk",
924 .parent_hws = (const struct clk_hw*[]){
925 &gsbi5_qup_src.clkr.hw,
926 },
927 .num_parents = 1,
928 .ops = &clk_branch_ops,
929 .flags = CLK_SET_RATE_PARENT,
930 },
931 },
932};
933
934static struct clk_rcg gsbi6_qup_src = {
935 .ns_reg = 0x2a6c,
936 .md_reg = 0x2a68,
937 .mn = {
938 .mnctr_en_bit = 8,
939 .mnctr_reset_bit = 7,
940 .mnctr_mode_shift = 5,
941 .n_val_shift = 16,
942 .m_val_shift = 16,
943 .width = 8,
944 },
945 .p = {
946 .pre_div_shift = 3,
947 .pre_div_width = 2,
948 },
949 .s = {
950 .src_sel_shift = 0,
951 .parent_map = gcc_pxo_pll8_map,
952 },
953 .freq_tbl = clk_tbl_gsbi_qup,
954 .clkr = {
955 .enable_reg = 0x2a6c,
956 .enable_mask = BIT(11),
957 .hw.init = &(struct clk_init_data){
958 .name = "gsbi6_qup_src",
959 .parent_data = gcc_pxo_pll8,
960 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
961 .ops = &clk_rcg_ops,
962 .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
963 },
964 },
965};
966
967static struct clk_branch gsbi6_qup_clk = {
968 .halt_reg = 0x2fd0,
969 .halt_bit = 16,
970 .clkr = {
971 .enable_reg = 0x2a6c,
972 .enable_mask = BIT(9),
973 .hw.init = &(struct clk_init_data){
974 .name = "gsbi6_qup_clk",
975 .parent_hws = (const struct clk_hw*[]){
976 &gsbi6_qup_src.clkr.hw,
977 },
978 .num_parents = 1,
979 .ops = &clk_branch_ops,
980 .flags = CLK_SET_RATE_PARENT,
981 },
982 },
983};
984
985static struct clk_rcg gsbi7_qup_src = {
986 .ns_reg = 0x2a8c,
987 .md_reg = 0x2a88,
988 .mn = {
989 .mnctr_en_bit = 8,
990 .mnctr_reset_bit = 7,
991 .mnctr_mode_shift = 5,
992 .n_val_shift = 16,
993 .m_val_shift = 16,
994 .width = 8,
995 },
996 .p = {
997 .pre_div_shift = 3,
998 .pre_div_width = 2,
999 },
1000 .s = {
1001 .src_sel_shift = 0,
1002 .parent_map = gcc_pxo_pll8_map,
1003 },
1004 .freq_tbl = clk_tbl_gsbi_qup,
1005 .clkr = {
1006 .enable_reg = 0x2a8c,
1007 .enable_mask = BIT(11),
1008 .hw.init = &(struct clk_init_data){
1009 .name = "gsbi7_qup_src",
1010 .parent_data = gcc_pxo_pll8,
1011 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1012 .ops = &clk_rcg_ops,
1013 .flags = CLK_SET_PARENT_GATE,
1014 },
1015 },
1016};
1017
1018static struct clk_branch gsbi7_qup_clk = {
1019 .halt_reg = 0x2fd0,
1020 .halt_bit = 12,
1021 .clkr = {
1022 .enable_reg = 0x2a8c,
1023 .enable_mask = BIT(9),
1024 .hw.init = &(struct clk_init_data){
1025 .name = "gsbi7_qup_clk",
1026 .parent_hws = (const struct clk_hw*[]){
1027 &gsbi7_qup_src.clkr.hw,
1028 },
1029 .num_parents = 1,
1030 .ops = &clk_branch_ops,
1031 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1032 },
1033 },
1034};
1035
1036static struct clk_branch gsbi1_h_clk = {
1037 .hwcg_reg = 0x29c0,
1038 .hwcg_bit = 6,
1039 .halt_reg = 0x2fcc,
1040 .halt_bit = 13,
1041 .clkr = {
1042 .enable_reg = 0x29c0,
1043 .enable_mask = BIT(4),
1044 .hw.init = &(struct clk_init_data){
1045 .name = "gsbi1_h_clk",
1046 .ops = &clk_branch_ops,
1047 },
1048 },
1049};
1050
1051static struct clk_branch gsbi2_h_clk = {
1052 .hwcg_reg = 0x29e0,
1053 .hwcg_bit = 6,
1054 .halt_reg = 0x2fcc,
1055 .halt_bit = 9,
1056 .clkr = {
1057 .enable_reg = 0x29e0,
1058 .enable_mask = BIT(4),
1059 .hw.init = &(struct clk_init_data){
1060 .name = "gsbi2_h_clk",
1061 .ops = &clk_branch_ops,
1062 },
1063 },
1064};
1065
1066static struct clk_branch gsbi4_h_clk = {
1067 .hwcg_reg = 0x2a20,
1068 .hwcg_bit = 6,
1069 .halt_reg = 0x2fd0,
1070 .halt_bit = 27,
1071 .clkr = {
1072 .enable_reg = 0x2a20,
1073 .enable_mask = BIT(4),
1074 .hw.init = &(struct clk_init_data){
1075 .name = "gsbi4_h_clk",
1076 .ops = &clk_branch_ops,
1077 .flags = CLK_IGNORE_UNUSED,
1078 },
1079 },
1080};
1081
1082static struct clk_branch gsbi5_h_clk = {
1083 .hwcg_reg = 0x2a40,
1084 .hwcg_bit = 6,
1085 .halt_reg = 0x2fd0,
1086 .halt_bit = 23,
1087 .clkr = {
1088 .enable_reg = 0x2a40,
1089 .enable_mask = BIT(4),
1090 .hw.init = &(struct clk_init_data){
1091 .name = "gsbi5_h_clk",
1092 .ops = &clk_branch_ops,
1093 },
1094 },
1095};
1096
1097static struct clk_branch gsbi6_h_clk = {
1098 .hwcg_reg = 0x2a60,
1099 .hwcg_bit = 6,
1100 .halt_reg = 0x2fd0,
1101 .halt_bit = 19,
1102 .clkr = {
1103 .enable_reg = 0x2a60,
1104 .enable_mask = BIT(4),
1105 .hw.init = &(struct clk_init_data){
1106 .name = "gsbi6_h_clk",
1107 .ops = &clk_branch_ops,
1108 },
1109 },
1110};
1111
1112static struct clk_branch gsbi7_h_clk = {
1113 .hwcg_reg = 0x2a80,
1114 .hwcg_bit = 6,
1115 .halt_reg = 0x2fd0,
1116 .halt_bit = 15,
1117 .clkr = {
1118 .enable_reg = 0x2a80,
1119 .enable_mask = BIT(4),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "gsbi7_h_clk",
1122 .ops = &clk_branch_ops,
1123 },
1124 },
1125};
1126
1127static const struct freq_tbl clk_tbl_gp[] = {
1128 { 12500000, P_PXO, 2, 0, 0 },
1129 { 25000000, P_PXO, 1, 0, 0 },
1130 { 64000000, P_PLL8, 2, 1, 3 },
1131 { 76800000, P_PLL8, 1, 1, 5 },
1132 { 96000000, P_PLL8, 4, 0, 0 },
1133 { 128000000, P_PLL8, 3, 0, 0 },
1134 { 192000000, P_PLL8, 2, 0, 0 },
1135 { }
1136};
1137
1138static struct clk_rcg gp0_src = {
1139 .ns_reg = 0x2d24,
1140 .md_reg = 0x2d00,
1141 .mn = {
1142 .mnctr_en_bit = 8,
1143 .mnctr_reset_bit = 7,
1144 .mnctr_mode_shift = 5,
1145 .n_val_shift = 16,
1146 .m_val_shift = 16,
1147 .width = 8,
1148 },
1149 .p = {
1150 .pre_div_shift = 3,
1151 .pre_div_width = 2,
1152 },
1153 .s = {
1154 .src_sel_shift = 0,
1155 .parent_map = gcc_pxo_pll8_cxo_map,
1156 },
1157 .freq_tbl = clk_tbl_gp,
1158 .clkr = {
1159 .enable_reg = 0x2d24,
1160 .enable_mask = BIT(11),
1161 .hw.init = &(struct clk_init_data){
1162 .name = "gp0_src",
1163 .parent_data = gcc_pxo_pll8_cxo,
1164 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1165 .ops = &clk_rcg_ops,
1166 .flags = CLK_SET_PARENT_GATE,
1167 },
1168 }
1169};
1170
1171static struct clk_branch gp0_clk = {
1172 .halt_reg = 0x2fd8,
1173 .halt_bit = 7,
1174 .clkr = {
1175 .enable_reg = 0x2d24,
1176 .enable_mask = BIT(9),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "gp0_clk",
1179 .parent_hws = (const struct clk_hw*[]){
1180 &gp0_src.clkr.hw,
1181 },
1182 .num_parents = 1,
1183 .ops = &clk_branch_ops,
1184 .flags = CLK_SET_RATE_PARENT,
1185 },
1186 },
1187};
1188
1189static struct clk_rcg gp1_src = {
1190 .ns_reg = 0x2d44,
1191 .md_reg = 0x2d40,
1192 .mn = {
1193 .mnctr_en_bit = 8,
1194 .mnctr_reset_bit = 7,
1195 .mnctr_mode_shift = 5,
1196 .n_val_shift = 16,
1197 .m_val_shift = 16,
1198 .width = 8,
1199 },
1200 .p = {
1201 .pre_div_shift = 3,
1202 .pre_div_width = 2,
1203 },
1204 .s = {
1205 .src_sel_shift = 0,
1206 .parent_map = gcc_pxo_pll8_cxo_map,
1207 },
1208 .freq_tbl = clk_tbl_gp,
1209 .clkr = {
1210 .enable_reg = 0x2d44,
1211 .enable_mask = BIT(11),
1212 .hw.init = &(struct clk_init_data){
1213 .name = "gp1_src",
1214 .parent_data = gcc_pxo_pll8_cxo,
1215 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1216 .ops = &clk_rcg_ops,
1217 .flags = CLK_SET_RATE_GATE,
1218 },
1219 }
1220};
1221
1222static struct clk_branch gp1_clk = {
1223 .halt_reg = 0x2fd8,
1224 .halt_bit = 6,
1225 .clkr = {
1226 .enable_reg = 0x2d44,
1227 .enable_mask = BIT(9),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gp1_clk",
1230 .parent_hws = (const struct clk_hw*[]){
1231 &gp1_src.clkr.hw,
1232 },
1233 .num_parents = 1,
1234 .ops = &clk_branch_ops,
1235 .flags = CLK_SET_RATE_PARENT,
1236 },
1237 },
1238};
1239
1240static struct clk_rcg gp2_src = {
1241 .ns_reg = 0x2d64,
1242 .md_reg = 0x2d60,
1243 .mn = {
1244 .mnctr_en_bit = 8,
1245 .mnctr_reset_bit = 7,
1246 .mnctr_mode_shift = 5,
1247 .n_val_shift = 16,
1248 .m_val_shift = 16,
1249 .width = 8,
1250 },
1251 .p = {
1252 .pre_div_shift = 3,
1253 .pre_div_width = 2,
1254 },
1255 .s = {
1256 .src_sel_shift = 0,
1257 .parent_map = gcc_pxo_pll8_cxo_map,
1258 },
1259 .freq_tbl = clk_tbl_gp,
1260 .clkr = {
1261 .enable_reg = 0x2d64,
1262 .enable_mask = BIT(11),
1263 .hw.init = &(struct clk_init_data){
1264 .name = "gp2_src",
1265 .parent_data = gcc_pxo_pll8_cxo,
1266 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1267 .ops = &clk_rcg_ops,
1268 .flags = CLK_SET_RATE_GATE,
1269 },
1270 }
1271};
1272
1273static struct clk_branch gp2_clk = {
1274 .halt_reg = 0x2fd8,
1275 .halt_bit = 5,
1276 .clkr = {
1277 .enable_reg = 0x2d64,
1278 .enable_mask = BIT(9),
1279 .hw.init = &(struct clk_init_data){
1280 .name = "gp2_clk",
1281 .parent_hws = (const struct clk_hw*[]){
1282 &gp2_src.clkr.hw,
1283 },
1284 .num_parents = 1,
1285 .ops = &clk_branch_ops,
1286 .flags = CLK_SET_RATE_PARENT,
1287 },
1288 },
1289};
1290
1291static struct clk_branch pmem_clk = {
1292 .hwcg_reg = 0x25a0,
1293 .hwcg_bit = 6,
1294 .halt_reg = 0x2fc8,
1295 .halt_bit = 20,
1296 .clkr = {
1297 .enable_reg = 0x25a0,
1298 .enable_mask = BIT(4),
1299 .hw.init = &(struct clk_init_data){
1300 .name = "pmem_clk",
1301 .ops = &clk_branch_ops,
1302 },
1303 },
1304};
1305
1306static struct clk_rcg prng_src = {
1307 .ns_reg = 0x2e80,
1308 .p = {
1309 .pre_div_shift = 3,
1310 .pre_div_width = 4,
1311 },
1312 .s = {
1313 .src_sel_shift = 0,
1314 .parent_map = gcc_pxo_pll8_map,
1315 },
1316 .clkr = {
1317 .enable_reg = 0x2e80,
1318 .enable_mask = BIT(11),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "prng_src",
1321 .parent_data = gcc_pxo_pll8,
1322 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1323 .ops = &clk_rcg_ops,
1324 },
1325 },
1326};
1327
1328static struct clk_branch prng_clk = {
1329 .halt_reg = 0x2fd8,
1330 .halt_check = BRANCH_HALT_VOTED,
1331 .halt_bit = 10,
1332 .clkr = {
1333 .enable_reg = 0x3080,
1334 .enable_mask = BIT(10),
1335 .hw.init = &(struct clk_init_data){
1336 .name = "prng_clk",
1337 .parent_hws = (const struct clk_hw*[]){
1338 &prng_src.clkr.hw,
1339 },
1340 .num_parents = 1,
1341 .ops = &clk_branch_ops,
1342 },
1343 },
1344};
1345
1346static const struct freq_tbl clk_tbl_sdc[] = {
1347 { 200000, P_PXO, 2, 2, 125 },
1348 { 400000, P_PLL8, 4, 1, 240 },
1349 { 16000000, P_PLL8, 4, 1, 6 },
1350 { 17070000, P_PLL8, 1, 2, 45 },
1351 { 20210000, P_PLL8, 1, 1, 19 },
1352 { 24000000, P_PLL8, 4, 1, 4 },
1353 { 48000000, P_PLL8, 4, 1, 2 },
1354 { 51200000, P_PLL8, 1, 2, 15 },
1355 { 64000000, P_PLL8, 3, 1, 2 },
1356 { 96000000, P_PLL8, 4, 0, 0 },
1357 { 192000000, P_PLL8, 2, 0, 0 },
1358 { }
1359};
1360
1361static struct clk_rcg sdc1_src = {
1362 .ns_reg = 0x282c,
1363 .md_reg = 0x2828,
1364 .mn = {
1365 .mnctr_en_bit = 8,
1366 .mnctr_reset_bit = 7,
1367 .mnctr_mode_shift = 5,
1368 .n_val_shift = 16,
1369 .m_val_shift = 16,
1370 .width = 8,
1371 },
1372 .p = {
1373 .pre_div_shift = 3,
1374 .pre_div_width = 2,
1375 },
1376 .s = {
1377 .src_sel_shift = 0,
1378 .parent_map = gcc_pxo_pll8_map,
1379 },
1380 .freq_tbl = clk_tbl_sdc,
1381 .clkr = {
1382 .enable_reg = 0x282c,
1383 .enable_mask = BIT(11),
1384 .hw.init = &(struct clk_init_data){
1385 .name = "sdc1_src",
1386 .parent_data = gcc_pxo_pll8,
1387 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1388 .ops = &clk_rcg_floor_ops,
1389 },
1390 }
1391};
1392
1393static struct clk_branch sdc1_clk = {
1394 .halt_reg = 0x2fc8,
1395 .halt_bit = 6,
1396 .clkr = {
1397 .enable_reg = 0x282c,
1398 .enable_mask = BIT(9),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "sdc1_clk",
1401 .parent_hws = (const struct clk_hw*[]){
1402 &sdc1_src.clkr.hw,
1403 },
1404 .num_parents = 1,
1405 .ops = &clk_branch_ops,
1406 .flags = CLK_SET_RATE_PARENT,
1407 },
1408 },
1409};
1410
1411static struct clk_rcg sdc3_src = {
1412 .ns_reg = 0x286c,
1413 .md_reg = 0x2868,
1414 .mn = {
1415 .mnctr_en_bit = 8,
1416 .mnctr_reset_bit = 7,
1417 .mnctr_mode_shift = 5,
1418 .n_val_shift = 16,
1419 .m_val_shift = 16,
1420 .width = 8,
1421 },
1422 .p = {
1423 .pre_div_shift = 3,
1424 .pre_div_width = 2,
1425 },
1426 .s = {
1427 .src_sel_shift = 0,
1428 .parent_map = gcc_pxo_pll8_map,
1429 },
1430 .freq_tbl = clk_tbl_sdc,
1431 .clkr = {
1432 .enable_reg = 0x286c,
1433 .enable_mask = BIT(11),
1434 .hw.init = &(struct clk_init_data){
1435 .name = "sdc3_src",
1436 .parent_data = gcc_pxo_pll8,
1437 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1438 .ops = &clk_rcg_ops,
1439 },
1440 }
1441};
1442
1443static struct clk_branch sdc3_clk = {
1444 .halt_reg = 0x2fc8,
1445 .halt_bit = 4,
1446 .clkr = {
1447 .enable_reg = 0x286c,
1448 .enable_mask = BIT(9),
1449 .hw.init = &(struct clk_init_data){
1450 .name = "sdc3_clk",
1451 .parent_hws = (const struct clk_hw*[]){
1452 &sdc3_src.clkr.hw,
1453 },
1454 .num_parents = 1,
1455 .ops = &clk_branch_ops,
1456 .flags = CLK_SET_RATE_PARENT,
1457 },
1458 },
1459};
1460
1461static struct clk_branch sdc1_h_clk = {
1462 .hwcg_reg = 0x2820,
1463 .hwcg_bit = 6,
1464 .halt_reg = 0x2fc8,
1465 .halt_bit = 11,
1466 .clkr = {
1467 .enable_reg = 0x2820,
1468 .enable_mask = BIT(4),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "sdc1_h_clk",
1471 .ops = &clk_branch_ops,
1472 },
1473 },
1474};
1475
1476static struct clk_branch sdc3_h_clk = {
1477 .hwcg_reg = 0x2860,
1478 .hwcg_bit = 6,
1479 .halt_reg = 0x2fc8,
1480 .halt_bit = 9,
1481 .clkr = {
1482 .enable_reg = 0x2860,
1483 .enable_mask = BIT(4),
1484 .hw.init = &(struct clk_init_data){
1485 .name = "sdc3_h_clk",
1486 .ops = &clk_branch_ops,
1487 },
1488 },
1489};
1490
1491static const struct freq_tbl clk_tbl_tsif_ref[] = {
1492 { 105000, P_PXO, 1, 1, 256 },
1493 { }
1494};
1495
1496static struct clk_rcg tsif_ref_src = {
1497 .ns_reg = 0x2710,
1498 .md_reg = 0x270c,
1499 .mn = {
1500 .mnctr_en_bit = 8,
1501 .mnctr_reset_bit = 7,
1502 .mnctr_mode_shift = 5,
1503 .n_val_shift = 16,
1504 .m_val_shift = 16,
1505 .width = 16,
1506 },
1507 .p = {
1508 .pre_div_shift = 3,
1509 .pre_div_width = 2,
1510 },
1511 .s = {
1512 .src_sel_shift = 0,
1513 .parent_map = gcc_pxo_pll8_map,
1514 },
1515 .freq_tbl = clk_tbl_tsif_ref,
1516 .clkr = {
1517 .enable_reg = 0x2710,
1518 .enable_mask = BIT(11),
1519 .hw.init = &(struct clk_init_data){
1520 .name = "tsif_ref_src",
1521 .parent_data = gcc_pxo_pll8,
1522 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1523 .ops = &clk_rcg_ops,
1524 },
1525 }
1526};
1527
1528static struct clk_branch tsif_ref_clk = {
1529 .halt_reg = 0x2fd4,
1530 .halt_bit = 5,
1531 .clkr = {
1532 .enable_reg = 0x2710,
1533 .enable_mask = BIT(9),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "tsif_ref_clk",
1536 .parent_hws = (const struct clk_hw*[]){
1537 &tsif_ref_src.clkr.hw,
1538 },
1539 .num_parents = 1,
1540 .ops = &clk_branch_ops,
1541 .flags = CLK_SET_RATE_PARENT,
1542 },
1543 },
1544};
1545
1546static struct clk_branch tsif_h_clk = {
1547 .hwcg_reg = 0x2700,
1548 .hwcg_bit = 6,
1549 .halt_reg = 0x2fd4,
1550 .halt_bit = 7,
1551 .clkr = {
1552 .enable_reg = 0x2700,
1553 .enable_mask = BIT(4),
1554 .hw.init = &(struct clk_init_data){
1555 .name = "tsif_h_clk",
1556 .ops = &clk_branch_ops,
1557 },
1558 },
1559};
1560
1561static struct clk_branch dma_bam_h_clk = {
1562 .hwcg_reg = 0x25c0,
1563 .hwcg_bit = 6,
1564 .halt_reg = 0x2fc8,
1565 .halt_bit = 12,
1566 .clkr = {
1567 .enable_reg = 0x25c0,
1568 .enable_mask = BIT(4),
1569 .hw.init = &(struct clk_init_data){
1570 .name = "dma_bam_h_clk",
1571 .ops = &clk_branch_ops,
1572 },
1573 },
1574};
1575
1576static struct clk_branch adm0_clk = {
1577 .halt_reg = 0x2fdc,
1578 .halt_check = BRANCH_HALT_VOTED,
1579 .halt_bit = 12,
1580 .clkr = {
1581 .enable_reg = 0x3080,
1582 .enable_mask = BIT(2),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "adm0_clk",
1585 .ops = &clk_branch_ops,
1586 },
1587 },
1588};
1589
1590static struct clk_branch adm0_pbus_clk = {
1591 .hwcg_reg = 0x2208,
1592 .hwcg_bit = 6,
1593 .halt_reg = 0x2fdc,
1594 .halt_check = BRANCH_HALT_VOTED,
1595 .halt_bit = 11,
1596 .clkr = {
1597 .enable_reg = 0x3080,
1598 .enable_mask = BIT(3),
1599 .hw.init = &(struct clk_init_data){
1600 .name = "adm0_pbus_clk",
1601 .ops = &clk_branch_ops,
1602 },
1603 },
1604};
1605
1606static struct clk_branch pmic_arb0_h_clk = {
1607 .halt_reg = 0x2fd8,
1608 .halt_check = BRANCH_HALT_VOTED,
1609 .halt_bit = 22,
1610 .clkr = {
1611 .enable_reg = 0x3080,
1612 .enable_mask = BIT(8),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "pmic_arb0_h_clk",
1615 .ops = &clk_branch_ops,
1616 },
1617 },
1618};
1619
1620static struct clk_branch pmic_arb1_h_clk = {
1621 .halt_reg = 0x2fd8,
1622 .halt_check = BRANCH_HALT_VOTED,
1623 .halt_bit = 21,
1624 .clkr = {
1625 .enable_reg = 0x3080,
1626 .enable_mask = BIT(9),
1627 .hw.init = &(struct clk_init_data){
1628 .name = "pmic_arb1_h_clk",
1629 .ops = &clk_branch_ops,
1630 },
1631 },
1632};
1633
1634static struct clk_branch pmic_ssbi2_clk = {
1635 .halt_reg = 0x2fd8,
1636 .halt_check = BRANCH_HALT_VOTED,
1637 .halt_bit = 23,
1638 .clkr = {
1639 .enable_reg = 0x3080,
1640 .enable_mask = BIT(7),
1641 .hw.init = &(struct clk_init_data){
1642 .name = "pmic_ssbi2_clk",
1643 .ops = &clk_branch_ops,
1644 },
1645 },
1646};
1647
1648static struct clk_branch rpm_msg_ram_h_clk = {
1649 .hwcg_reg = 0x27e0,
1650 .hwcg_bit = 6,
1651 .halt_reg = 0x2fd8,
1652 .halt_check = BRANCH_HALT_VOTED,
1653 .halt_bit = 12,
1654 .clkr = {
1655 .enable_reg = 0x3080,
1656 .enable_mask = BIT(6),
1657 .hw.init = &(struct clk_init_data){
1658 .name = "rpm_msg_ram_h_clk",
1659 .ops = &clk_branch_ops,
1660 },
1661 },
1662};
1663
1664static const struct freq_tbl clk_tbl_pcie_ref[] = {
1665 { 100000000, P_PLL3, 12, 0, 0 },
1666 { }
1667};
1668
1669static struct clk_rcg pcie_ref_src = {
1670 .ns_reg = 0x3860,
1671 .p = {
1672 .pre_div_shift = 3,
1673 .pre_div_width = 4,
1674 },
1675 .s = {
1676 .src_sel_shift = 0,
1677 .parent_map = gcc_pxo_pll3_map,
1678 },
1679 .freq_tbl = clk_tbl_pcie_ref,
1680 .clkr = {
1681 .enable_reg = 0x3860,
1682 .enable_mask = BIT(11),
1683 .hw.init = &(struct clk_init_data){
1684 .name = "pcie_ref_src",
1685 .parent_data = gcc_pxo_pll3,
1686 .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
1687 .ops = &clk_rcg_ops,
1688 .flags = CLK_SET_RATE_GATE,
1689 },
1690 },
1691};
1692
1693static struct clk_branch pcie_ref_src_clk = {
1694 .halt_reg = 0x2fdc,
1695 .halt_bit = 30,
1696 .clkr = {
1697 .enable_reg = 0x3860,
1698 .enable_mask = BIT(9),
1699 .hw.init = &(struct clk_init_data){
1700 .name = "pcie_ref_src_clk",
1701 .parent_hws = (const struct clk_hw*[]){
1702 &pcie_ref_src.clkr.hw,
1703 },
1704 .num_parents = 1,
1705 .ops = &clk_branch_ops,
1706 .flags = CLK_SET_RATE_PARENT,
1707 },
1708 },
1709};
1710
1711static struct clk_branch pcie_a_clk = {
1712 .halt_reg = 0x2fc0,
1713 .halt_bit = 13,
1714 .clkr = {
1715 .enable_reg = 0x22c0,
1716 .enable_mask = BIT(4),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "pcie_a_clk",
1719 .ops = &clk_branch_ops,
1720 },
1721 },
1722};
1723
1724static struct clk_branch pcie_aux_clk = {
1725 .halt_reg = 0x2fdc,
1726 .halt_bit = 31,
1727 .clkr = {
1728 .enable_reg = 0x22c8,
1729 .enable_mask = BIT(4),
1730 .hw.init = &(struct clk_init_data){
1731 .name = "pcie_aux_clk",
1732 .ops = &clk_branch_ops,
1733 },
1734 },
1735};
1736
1737static struct clk_branch pcie_h_clk = {
1738 .halt_reg = 0x2fd4,
1739 .halt_bit = 8,
1740 .clkr = {
1741 .enable_reg = 0x22cc,
1742 .enable_mask = BIT(4),
1743 .hw.init = &(struct clk_init_data){
1744 .name = "pcie_h_clk",
1745 .ops = &clk_branch_ops,
1746 },
1747 },
1748};
1749
1750static struct clk_branch pcie_phy_clk = {
1751 .halt_reg = 0x2fdc,
1752 .halt_bit = 29,
1753 .clkr = {
1754 .enable_reg = 0x22d0,
1755 .enable_mask = BIT(4),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "pcie_phy_clk",
1758 .ops = &clk_branch_ops,
1759 },
1760 },
1761};
1762
1763static struct clk_rcg pcie1_ref_src = {
1764 .ns_reg = 0x3aa0,
1765 .p = {
1766 .pre_div_shift = 3,
1767 .pre_div_width = 4,
1768 },
1769 .s = {
1770 .src_sel_shift = 0,
1771 .parent_map = gcc_pxo_pll3_map,
1772 },
1773 .freq_tbl = clk_tbl_pcie_ref,
1774 .clkr = {
1775 .enable_reg = 0x3aa0,
1776 .enable_mask = BIT(11),
1777 .hw.init = &(struct clk_init_data){
1778 .name = "pcie1_ref_src",
1779 .parent_data = gcc_pxo_pll3,
1780 .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
1781 .ops = &clk_rcg_ops,
1782 .flags = CLK_SET_RATE_GATE,
1783 },
1784 },
1785};
1786
1787static struct clk_branch pcie1_ref_src_clk = {
1788 .halt_reg = 0x2fdc,
1789 .halt_bit = 27,
1790 .clkr = {
1791 .enable_reg = 0x3aa0,
1792 .enable_mask = BIT(9),
1793 .hw.init = &(struct clk_init_data){
1794 .name = "pcie1_ref_src_clk",
1795 .parent_hws = (const struct clk_hw*[]){
1796 &pcie1_ref_src.clkr.hw,
1797 },
1798 .num_parents = 1,
1799 .ops = &clk_branch_ops,
1800 .flags = CLK_SET_RATE_PARENT,
1801 },
1802 },
1803};
1804
1805static struct clk_branch pcie1_a_clk = {
1806 .halt_reg = 0x2fc0,
1807 .halt_bit = 10,
1808 .clkr = {
1809 .enable_reg = 0x3a80,
1810 .enable_mask = BIT(4),
1811 .hw.init = &(struct clk_init_data){
1812 .name = "pcie1_a_clk",
1813 .ops = &clk_branch_ops,
1814 },
1815 },
1816};
1817
1818static struct clk_branch pcie1_aux_clk = {
1819 .halt_reg = 0x2fdc,
1820 .halt_bit = 28,
1821 .clkr = {
1822 .enable_reg = 0x3a88,
1823 .enable_mask = BIT(4),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "pcie1_aux_clk",
1826 .ops = &clk_branch_ops,
1827 },
1828 },
1829};
1830
1831static struct clk_branch pcie1_h_clk = {
1832 .halt_reg = 0x2fd4,
1833 .halt_bit = 9,
1834 .clkr = {
1835 .enable_reg = 0x3a8c,
1836 .enable_mask = BIT(4),
1837 .hw.init = &(struct clk_init_data){
1838 .name = "pcie1_h_clk",
1839 .ops = &clk_branch_ops,
1840 },
1841 },
1842};
1843
1844static struct clk_branch pcie1_phy_clk = {
1845 .halt_reg = 0x2fdc,
1846 .halt_bit = 26,
1847 .clkr = {
1848 .enable_reg = 0x3a90,
1849 .enable_mask = BIT(4),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "pcie1_phy_clk",
1852 .ops = &clk_branch_ops,
1853 },
1854 },
1855};
1856
1857static struct clk_rcg pcie2_ref_src = {
1858 .ns_reg = 0x3ae0,
1859 .p = {
1860 .pre_div_shift = 3,
1861 .pre_div_width = 4,
1862 },
1863 .s = {
1864 .src_sel_shift = 0,
1865 .parent_map = gcc_pxo_pll3_map,
1866 },
1867 .freq_tbl = clk_tbl_pcie_ref,
1868 .clkr = {
1869 .enable_reg = 0x3ae0,
1870 .enable_mask = BIT(11),
1871 .hw.init = &(struct clk_init_data){
1872 .name = "pcie2_ref_src",
1873 .parent_data = gcc_pxo_pll3,
1874 .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
1875 .ops = &clk_rcg_ops,
1876 .flags = CLK_SET_RATE_GATE,
1877 },
1878 },
1879};
1880
1881static struct clk_branch pcie2_ref_src_clk = {
1882 .halt_reg = 0x2fdc,
1883 .halt_bit = 24,
1884 .clkr = {
1885 .enable_reg = 0x3ae0,
1886 .enable_mask = BIT(9),
1887 .hw.init = &(struct clk_init_data){
1888 .name = "pcie2_ref_src_clk",
1889 .parent_hws = (const struct clk_hw*[]){
1890 &pcie2_ref_src.clkr.hw,
1891 },
1892 .num_parents = 1,
1893 .ops = &clk_branch_ops,
1894 .flags = CLK_SET_RATE_PARENT,
1895 },
1896 },
1897};
1898
1899static struct clk_branch pcie2_a_clk = {
1900 .halt_reg = 0x2fc0,
1901 .halt_bit = 9,
1902 .clkr = {
1903 .enable_reg = 0x3ac0,
1904 .enable_mask = BIT(4),
1905 .hw.init = &(struct clk_init_data){
1906 .name = "pcie2_a_clk",
1907 .ops = &clk_branch_ops,
1908 },
1909 },
1910};
1911
1912static struct clk_branch pcie2_aux_clk = {
1913 .halt_reg = 0x2fdc,
1914 .halt_bit = 25,
1915 .clkr = {
1916 .enable_reg = 0x3ac8,
1917 .enable_mask = BIT(4),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "pcie2_aux_clk",
1920 .ops = &clk_branch_ops,
1921 },
1922 },
1923};
1924
1925static struct clk_branch pcie2_h_clk = {
1926 .halt_reg = 0x2fd4,
1927 .halt_bit = 10,
1928 .clkr = {
1929 .enable_reg = 0x3acc,
1930 .enable_mask = BIT(4),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "pcie2_h_clk",
1933 .ops = &clk_branch_ops,
1934 },
1935 },
1936};
1937
1938static struct clk_branch pcie2_phy_clk = {
1939 .halt_reg = 0x2fdc,
1940 .halt_bit = 23,
1941 .clkr = {
1942 .enable_reg = 0x3ad0,
1943 .enable_mask = BIT(4),
1944 .hw.init = &(struct clk_init_data){
1945 .name = "pcie2_phy_clk",
1946 .ops = &clk_branch_ops,
1947 },
1948 },
1949};
1950
1951static const struct freq_tbl clk_tbl_sata_ref[] = {
1952 { 100000000, P_PLL3, 12, 0, 0 },
1953 { }
1954};
1955
1956static struct clk_rcg sata_ref_src = {
1957 .ns_reg = 0x2c08,
1958 .p = {
1959 .pre_div_shift = 3,
1960 .pre_div_width = 4,
1961 },
1962 .s = {
1963 .src_sel_shift = 0,
1964 .parent_map = gcc_pxo_pll3_sata_map,
1965 },
1966 .freq_tbl = clk_tbl_sata_ref,
1967 .clkr = {
1968 .enable_reg = 0x2c08,
1969 .enable_mask = BIT(7),
1970 .hw.init = &(struct clk_init_data){
1971 .name = "sata_ref_src",
1972 .parent_data = gcc_pxo_pll3,
1973 .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
1974 .ops = &clk_rcg_ops,
1975 .flags = CLK_SET_RATE_GATE,
1976 },
1977 },
1978};
1979
1980static struct clk_branch sata_rxoob_clk = {
1981 .halt_reg = 0x2fdc,
1982 .halt_bit = 20,
1983 .clkr = {
1984 .enable_reg = 0x2c0c,
1985 .enable_mask = BIT(4),
1986 .hw.init = &(struct clk_init_data){
1987 .name = "sata_rxoob_clk",
1988 .parent_hws = (const struct clk_hw*[]){
1989 &sata_ref_src.clkr.hw,
1990 },
1991 .num_parents = 1,
1992 .ops = &clk_branch_ops,
1993 .flags = CLK_SET_RATE_PARENT,
1994 },
1995 },
1996};
1997
1998static struct clk_branch sata_pmalive_clk = {
1999 .halt_reg = 0x2fdc,
2000 .halt_bit = 19,
2001 .clkr = {
2002 .enable_reg = 0x2c10,
2003 .enable_mask = BIT(4),
2004 .hw.init = &(struct clk_init_data){
2005 .name = "sata_pmalive_clk",
2006 .parent_hws = (const struct clk_hw*[]){
2007 &sata_ref_src.clkr.hw,
2008 },
2009 .num_parents = 1,
2010 .ops = &clk_branch_ops,
2011 .flags = CLK_SET_RATE_PARENT,
2012 },
2013 },
2014};
2015
2016static struct clk_branch sata_phy_ref_clk = {
2017 .halt_reg = 0x2fdc,
2018 .halt_bit = 18,
2019 .clkr = {
2020 .enable_reg = 0x2c14,
2021 .enable_mask = BIT(4),
2022 .hw.init = &(struct clk_init_data){
2023 .name = "sata_phy_ref_clk",
2024 .parent_data = gcc_pxo,
2025 .num_parents = 1,
2026 .ops = &clk_branch_ops,
2027 },
2028 },
2029};
2030
2031static struct clk_branch sata_a_clk = {
2032 .halt_reg = 0x2fc0,
2033 .halt_bit = 12,
2034 .clkr = {
2035 .enable_reg = 0x2c20,
2036 .enable_mask = BIT(4),
2037 .hw.init = &(struct clk_init_data){
2038 .name = "sata_a_clk",
2039 .ops = &clk_branch_ops,
2040 },
2041 },
2042};
2043
2044static struct clk_branch sata_h_clk = {
2045 .halt_reg = 0x2fdc,
2046 .halt_bit = 21,
2047 .clkr = {
2048 .enable_reg = 0x2c00,
2049 .enable_mask = BIT(4),
2050 .hw.init = &(struct clk_init_data){
2051 .name = "sata_h_clk",
2052 .ops = &clk_branch_ops,
2053 },
2054 },
2055};
2056
2057static struct clk_branch sfab_sata_s_h_clk = {
2058 .halt_reg = 0x2fc4,
2059 .halt_bit = 14,
2060 .clkr = {
2061 .enable_reg = 0x2480,
2062 .enable_mask = BIT(4),
2063 .hw.init = &(struct clk_init_data){
2064 .name = "sfab_sata_s_h_clk",
2065 .ops = &clk_branch_ops,
2066 },
2067 },
2068};
2069
2070static struct clk_branch sata_phy_cfg_clk = {
2071 .halt_reg = 0x2fcc,
2072 .halt_bit = 14,
2073 .clkr = {
2074 .enable_reg = 0x2c40,
2075 .enable_mask = BIT(4),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "sata_phy_cfg_clk",
2078 .ops = &clk_branch_ops,
2079 },
2080 },
2081};
2082
2083static const struct freq_tbl clk_tbl_usb30_master[] = {
2084 { 125000000, P_PLL0, 1, 5, 32 },
2085 { }
2086};
2087
2088static struct clk_rcg usb30_master_clk_src = {
2089 .ns_reg = 0x3b2c,
2090 .md_reg = 0x3b28,
2091 .mn = {
2092 .mnctr_en_bit = 8,
2093 .mnctr_reset_bit = 7,
2094 .mnctr_mode_shift = 5,
2095 .n_val_shift = 16,
2096 .m_val_shift = 16,
2097 .width = 8,
2098 },
2099 .p = {
2100 .pre_div_shift = 3,
2101 .pre_div_width = 2,
2102 },
2103 .s = {
2104 .src_sel_shift = 0,
2105 .parent_map = gcc_pxo_pll8_pll0_map,
2106 },
2107 .freq_tbl = clk_tbl_usb30_master,
2108 .clkr = {
2109 .enable_reg = 0x3b2c,
2110 .enable_mask = BIT(11),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "usb30_master_ref_src",
2113 .parent_data = gcc_pxo_pll8_pll0,
2114 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
2115 .ops = &clk_rcg_ops,
2116 .flags = CLK_SET_RATE_GATE,
2117 },
2118 },
2119};
2120
2121static struct clk_branch usb30_0_branch_clk = {
2122 .halt_reg = 0x2fc4,
2123 .halt_bit = 22,
2124 .clkr = {
2125 .enable_reg = 0x3b24,
2126 .enable_mask = BIT(4),
2127 .hw.init = &(struct clk_init_data){
2128 .name = "usb30_0_branch_clk",
2129 .parent_hws = (const struct clk_hw*[]){
2130 &usb30_master_clk_src.clkr.hw,
2131 },
2132 .num_parents = 1,
2133 .ops = &clk_branch_ops,
2134 .flags = CLK_SET_RATE_PARENT,
2135 },
2136 },
2137};
2138
2139static struct clk_branch usb30_1_branch_clk = {
2140 .halt_reg = 0x2fc4,
2141 .halt_bit = 17,
2142 .clkr = {
2143 .enable_reg = 0x3b34,
2144 .enable_mask = BIT(4),
2145 .hw.init = &(struct clk_init_data){
2146 .name = "usb30_1_branch_clk",
2147 .parent_hws = (const struct clk_hw*[]){
2148 &usb30_master_clk_src.clkr.hw,
2149 },
2150 .num_parents = 1,
2151 .ops = &clk_branch_ops,
2152 .flags = CLK_SET_RATE_PARENT,
2153 },
2154 },
2155};
2156
2157static const struct freq_tbl clk_tbl_usb30_utmi[] = {
2158 { 60000000, P_PLL8, 1, 5, 32 },
2159 { }
2160};
2161
2162static struct clk_rcg usb30_utmi_clk = {
2163 .ns_reg = 0x3b44,
2164 .md_reg = 0x3b40,
2165 .mn = {
2166 .mnctr_en_bit = 8,
2167 .mnctr_reset_bit = 7,
2168 .mnctr_mode_shift = 5,
2169 .n_val_shift = 16,
2170 .m_val_shift = 16,
2171 .width = 8,
2172 },
2173 .p = {
2174 .pre_div_shift = 3,
2175 .pre_div_width = 2,
2176 },
2177 .s = {
2178 .src_sel_shift = 0,
2179 .parent_map = gcc_pxo_pll8_pll0_map,
2180 },
2181 .freq_tbl = clk_tbl_usb30_utmi,
2182 .clkr = {
2183 .enable_reg = 0x3b44,
2184 .enable_mask = BIT(11),
2185 .hw.init = &(struct clk_init_data){
2186 .name = "usb30_utmi_clk",
2187 .parent_data = gcc_pxo_pll8_pll0,
2188 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
2189 .ops = &clk_rcg_ops,
2190 .flags = CLK_SET_RATE_GATE,
2191 },
2192 },
2193};
2194
2195static struct clk_branch usb30_0_utmi_clk_ctl = {
2196 .halt_reg = 0x2fc4,
2197 .halt_bit = 21,
2198 .clkr = {
2199 .enable_reg = 0x3b48,
2200 .enable_mask = BIT(4),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "usb30_0_utmi_clk_ctl",
2203 .parent_hws = (const struct clk_hw*[]){
2204 &usb30_utmi_clk.clkr.hw,
2205 },
2206 .num_parents = 1,
2207 .ops = &clk_branch_ops,
2208 .flags = CLK_SET_RATE_PARENT,
2209 },
2210 },
2211};
2212
2213static struct clk_branch usb30_1_utmi_clk_ctl = {
2214 .halt_reg = 0x2fc4,
2215 .halt_bit = 15,
2216 .clkr = {
2217 .enable_reg = 0x3b4c,
2218 .enable_mask = BIT(4),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "usb30_1_utmi_clk_ctl",
2221 .parent_hws = (const struct clk_hw*[]){
2222 &usb30_utmi_clk.clkr.hw,
2223 },
2224 .num_parents = 1,
2225 .ops = &clk_branch_ops,
2226 .flags = CLK_SET_RATE_PARENT,
2227 },
2228 },
2229};
2230
2231static const struct freq_tbl clk_tbl_usb[] = {
2232 { 60000000, P_PLL8, 1, 5, 32 },
2233 { }
2234};
2235
2236static struct clk_rcg usb_hs1_xcvr_clk_src = {
2237 .ns_reg = 0x290C,
2238 .md_reg = 0x2908,
2239 .mn = {
2240 .mnctr_en_bit = 8,
2241 .mnctr_reset_bit = 7,
2242 .mnctr_mode_shift = 5,
2243 .n_val_shift = 16,
2244 .m_val_shift = 16,
2245 .width = 8,
2246 },
2247 .p = {
2248 .pre_div_shift = 3,
2249 .pre_div_width = 2,
2250 },
2251 .s = {
2252 .src_sel_shift = 0,
2253 .parent_map = gcc_pxo_pll8_pll0_map,
2254 },
2255 .freq_tbl = clk_tbl_usb,
2256 .clkr = {
2257 .enable_reg = 0x2968,
2258 .enable_mask = BIT(11),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "usb_hs1_xcvr_src",
2261 .parent_data = gcc_pxo_pll8_pll0,
2262 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
2263 .ops = &clk_rcg_ops,
2264 .flags = CLK_SET_RATE_GATE,
2265 },
2266 },
2267};
2268
2269static struct clk_branch usb_hs1_xcvr_clk = {
2270 .halt_reg = 0x2fcc,
2271 .halt_bit = 17,
2272 .clkr = {
2273 .enable_reg = 0x290c,
2274 .enable_mask = BIT(9),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "usb_hs1_xcvr_clk",
2277 .parent_hws = (const struct clk_hw*[]){
2278 &usb_hs1_xcvr_clk_src.clkr.hw,
2279 },
2280 .num_parents = 1,
2281 .ops = &clk_branch_ops,
2282 .flags = CLK_SET_RATE_PARENT,
2283 },
2284 },
2285};
2286
2287static struct clk_branch usb_hs1_h_clk = {
2288 .hwcg_reg = 0x2900,
2289 .hwcg_bit = 6,
2290 .halt_reg = 0x2fc8,
2291 .halt_bit = 1,
2292 .clkr = {
2293 .enable_reg = 0x2900,
2294 .enable_mask = BIT(4),
2295 .hw.init = &(struct clk_init_data){
2296 .name = "usb_hs1_h_clk",
2297 .ops = &clk_branch_ops,
2298 },
2299 },
2300};
2301
2302static struct clk_rcg usb_fs1_xcvr_clk_src = {
2303 .ns_reg = 0x2968,
2304 .md_reg = 0x2964,
2305 .mn = {
2306 .mnctr_en_bit = 8,
2307 .mnctr_reset_bit = 7,
2308 .mnctr_mode_shift = 5,
2309 .n_val_shift = 16,
2310 .m_val_shift = 16,
2311 .width = 8,
2312 },
2313 .p = {
2314 .pre_div_shift = 3,
2315 .pre_div_width = 2,
2316 },
2317 .s = {
2318 .src_sel_shift = 0,
2319 .parent_map = gcc_pxo_pll8_pll0_map,
2320 },
2321 .freq_tbl = clk_tbl_usb,
2322 .clkr = {
2323 .enable_reg = 0x2968,
2324 .enable_mask = BIT(11),
2325 .hw.init = &(struct clk_init_data){
2326 .name = "usb_fs1_xcvr_src",
2327 .parent_data = gcc_pxo_pll8_pll0,
2328 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
2329 .ops = &clk_rcg_ops,
2330 .flags = CLK_SET_RATE_GATE,
2331 },
2332 },
2333};
2334
2335static struct clk_branch usb_fs1_xcvr_clk = {
2336 .halt_reg = 0x2fcc,
2337 .halt_bit = 17,
2338 .clkr = {
2339 .enable_reg = 0x2968,
2340 .enable_mask = BIT(9),
2341 .hw.init = &(struct clk_init_data){
2342 .name = "usb_fs1_xcvr_clk",
2343 .parent_hws = (const struct clk_hw*[]){
2344 &usb_fs1_xcvr_clk_src.clkr.hw,
2345 },
2346 .num_parents = 1,
2347 .ops = &clk_branch_ops,
2348 .flags = CLK_SET_RATE_PARENT,
2349 },
2350 },
2351};
2352
2353static struct clk_branch usb_fs1_sys_clk = {
2354 .halt_reg = 0x2fcc,
2355 .halt_bit = 18,
2356 .clkr = {
2357 .enable_reg = 0x296c,
2358 .enable_mask = BIT(4),
2359 .hw.init = &(struct clk_init_data){
2360 .name = "usb_fs1_sys_clk",
2361 .parent_hws = (const struct clk_hw*[]){
2362 &usb_fs1_xcvr_clk_src.clkr.hw,
2363 },
2364 .num_parents = 1,
2365 .ops = &clk_branch_ops,
2366 .flags = CLK_SET_RATE_PARENT,
2367 },
2368 },
2369};
2370
2371static struct clk_branch usb_fs1_h_clk = {
2372 .halt_reg = 0x2fcc,
2373 .halt_bit = 19,
2374 .clkr = {
2375 .enable_reg = 0x2960,
2376 .enable_mask = BIT(4),
2377 .hw.init = &(struct clk_init_data){
2378 .name = "usb_fs1_h_clk",
2379 .ops = &clk_branch_ops,
2380 },
2381 },
2382};
2383
2384static struct clk_branch ebi2_clk = {
2385 .hwcg_reg = 0x3b00,
2386 .hwcg_bit = 6,
2387 .halt_reg = 0x2fcc,
2388 .halt_bit = 1,
2389 .clkr = {
2390 .enable_reg = 0x3b00,
2391 .enable_mask = BIT(4),
2392 .hw.init = &(struct clk_init_data){
2393 .name = "ebi2_clk",
2394 .ops = &clk_branch_ops,
2395 },
2396 },
2397};
2398
2399static struct clk_branch ebi2_aon_clk = {
2400 .halt_reg = 0x2fcc,
2401 .halt_bit = 0,
2402 .clkr = {
2403 .enable_reg = 0x3b00,
2404 .enable_mask = BIT(8),
2405 .hw.init = &(struct clk_init_data){
2406 .name = "ebi2_always_on_clk",
2407 .ops = &clk_branch_ops,
2408 },
2409 },
2410};
2411
2412static const struct freq_tbl clk_tbl_gmac[] = {
2413 { 133000000, P_PLL0, 1, 50, 301 },
2414 { 266000000, P_PLL0, 1, 127, 382 },
2415 { }
2416};
2417
2418static struct clk_dyn_rcg gmac_core1_src = {
2419 .ns_reg[0] = 0x3cac,
2420 .ns_reg[1] = 0x3cb0,
2421 .md_reg[0] = 0x3ca4,
2422 .md_reg[1] = 0x3ca8,
2423 .bank_reg = 0x3ca0,
2424 .mn[0] = {
2425 .mnctr_en_bit = 8,
2426 .mnctr_reset_bit = 7,
2427 .mnctr_mode_shift = 5,
2428 .n_val_shift = 16,
2429 .m_val_shift = 16,
2430 .width = 8,
2431 },
2432 .mn[1] = {
2433 .mnctr_en_bit = 8,
2434 .mnctr_reset_bit = 7,
2435 .mnctr_mode_shift = 5,
2436 .n_val_shift = 16,
2437 .m_val_shift = 16,
2438 .width = 8,
2439 },
2440 .s[0] = {
2441 .src_sel_shift = 0,
2442 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2443 },
2444 .s[1] = {
2445 .src_sel_shift = 0,
2446 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2447 },
2448 .p[0] = {
2449 .pre_div_shift = 3,
2450 .pre_div_width = 2,
2451 },
2452 .p[1] = {
2453 .pre_div_shift = 3,
2454 .pre_div_width = 2,
2455 },
2456 .mux_sel_bit = 0,
2457 .freq_tbl = clk_tbl_gmac,
2458 .clkr = {
2459 .enable_reg = 0x3ca0,
2460 .enable_mask = BIT(1),
2461 .hw.init = &(struct clk_init_data){
2462 .name = "gmac_core1_src",
2463 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2464 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2465 .ops = &clk_dyn_rcg_ops,
2466 },
2467 },
2468};
2469
2470static struct clk_branch gmac_core1_clk = {
2471 .halt_reg = 0x3c20,
2472 .halt_bit = 4,
2473 .hwcg_reg = 0x3cb4,
2474 .hwcg_bit = 6,
2475 .clkr = {
2476 .enable_reg = 0x3cb4,
2477 .enable_mask = BIT(4),
2478 .hw.init = &(struct clk_init_data){
2479 .name = "gmac_core1_clk",
2480 .parent_hws = (const struct clk_hw*[]){
2481 &gmac_core1_src.clkr.hw,
2482 },
2483 .num_parents = 1,
2484 .ops = &clk_branch_ops,
2485 .flags = CLK_SET_RATE_PARENT,
2486 },
2487 },
2488};
2489
2490static struct clk_dyn_rcg gmac_core2_src = {
2491 .ns_reg[0] = 0x3ccc,
2492 .ns_reg[1] = 0x3cd0,
2493 .md_reg[0] = 0x3cc4,
2494 .md_reg[1] = 0x3cc8,
2495 .bank_reg = 0x3ca0,
2496 .mn[0] = {
2497 .mnctr_en_bit = 8,
2498 .mnctr_reset_bit = 7,
2499 .mnctr_mode_shift = 5,
2500 .n_val_shift = 16,
2501 .m_val_shift = 16,
2502 .width = 8,
2503 },
2504 .mn[1] = {
2505 .mnctr_en_bit = 8,
2506 .mnctr_reset_bit = 7,
2507 .mnctr_mode_shift = 5,
2508 .n_val_shift = 16,
2509 .m_val_shift = 16,
2510 .width = 8,
2511 },
2512 .s[0] = {
2513 .src_sel_shift = 0,
2514 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2515 },
2516 .s[1] = {
2517 .src_sel_shift = 0,
2518 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2519 },
2520 .p[0] = {
2521 .pre_div_shift = 3,
2522 .pre_div_width = 2,
2523 },
2524 .p[1] = {
2525 .pre_div_shift = 3,
2526 .pre_div_width = 2,
2527 },
2528 .mux_sel_bit = 0,
2529 .freq_tbl = clk_tbl_gmac,
2530 .clkr = {
2531 .enable_reg = 0x3cc0,
2532 .enable_mask = BIT(1),
2533 .hw.init = &(struct clk_init_data){
2534 .name = "gmac_core2_src",
2535 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2536 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2537 .ops = &clk_dyn_rcg_ops,
2538 },
2539 },
2540};
2541
2542static struct clk_branch gmac_core2_clk = {
2543 .halt_reg = 0x3c20,
2544 .halt_bit = 5,
2545 .hwcg_reg = 0x3cd4,
2546 .hwcg_bit = 6,
2547 .clkr = {
2548 .enable_reg = 0x3cd4,
2549 .enable_mask = BIT(4),
2550 .hw.init = &(struct clk_init_data){
2551 .name = "gmac_core2_clk",
2552 .parent_hws = (const struct clk_hw*[]){
2553 &gmac_core2_src.clkr.hw,
2554 },
2555 .num_parents = 1,
2556 .ops = &clk_branch_ops,
2557 .flags = CLK_SET_RATE_PARENT,
2558 },
2559 },
2560};
2561
2562static struct clk_dyn_rcg gmac_core3_src = {
2563 .ns_reg[0] = 0x3cec,
2564 .ns_reg[1] = 0x3cf0,
2565 .md_reg[0] = 0x3ce4,
2566 .md_reg[1] = 0x3ce8,
2567 .bank_reg = 0x3ce0,
2568 .mn[0] = {
2569 .mnctr_en_bit = 8,
2570 .mnctr_reset_bit = 7,
2571 .mnctr_mode_shift = 5,
2572 .n_val_shift = 16,
2573 .m_val_shift = 16,
2574 .width = 8,
2575 },
2576 .mn[1] = {
2577 .mnctr_en_bit = 8,
2578 .mnctr_reset_bit = 7,
2579 .mnctr_mode_shift = 5,
2580 .n_val_shift = 16,
2581 .m_val_shift = 16,
2582 .width = 8,
2583 },
2584 .s[0] = {
2585 .src_sel_shift = 0,
2586 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2587 },
2588 .s[1] = {
2589 .src_sel_shift = 0,
2590 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2591 },
2592 .p[0] = {
2593 .pre_div_shift = 3,
2594 .pre_div_width = 2,
2595 },
2596 .p[1] = {
2597 .pre_div_shift = 3,
2598 .pre_div_width = 2,
2599 },
2600 .mux_sel_bit = 0,
2601 .freq_tbl = clk_tbl_gmac,
2602 .clkr = {
2603 .enable_reg = 0x3ce0,
2604 .enable_mask = BIT(1),
2605 .hw.init = &(struct clk_init_data){
2606 .name = "gmac_core3_src",
2607 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2608 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2609 .ops = &clk_dyn_rcg_ops,
2610 },
2611 },
2612};
2613
2614static struct clk_branch gmac_core3_clk = {
2615 .halt_reg = 0x3c20,
2616 .halt_bit = 6,
2617 .hwcg_reg = 0x3cf4,
2618 .hwcg_bit = 6,
2619 .clkr = {
2620 .enable_reg = 0x3cf4,
2621 .enable_mask = BIT(4),
2622 .hw.init = &(struct clk_init_data){
2623 .name = "gmac_core3_clk",
2624 .parent_hws = (const struct clk_hw*[]){
2625 &gmac_core3_src.clkr.hw,
2626 },
2627 .num_parents = 1,
2628 .ops = &clk_branch_ops,
2629 .flags = CLK_SET_RATE_PARENT,
2630 },
2631 },
2632};
2633
2634static struct clk_dyn_rcg gmac_core4_src = {
2635 .ns_reg[0] = 0x3d0c,
2636 .ns_reg[1] = 0x3d10,
2637 .md_reg[0] = 0x3d04,
2638 .md_reg[1] = 0x3d08,
2639 .bank_reg = 0x3d00,
2640 .mn[0] = {
2641 .mnctr_en_bit = 8,
2642 .mnctr_reset_bit = 7,
2643 .mnctr_mode_shift = 5,
2644 .n_val_shift = 16,
2645 .m_val_shift = 16,
2646 .width = 8,
2647 },
2648 .mn[1] = {
2649 .mnctr_en_bit = 8,
2650 .mnctr_reset_bit = 7,
2651 .mnctr_mode_shift = 5,
2652 .n_val_shift = 16,
2653 .m_val_shift = 16,
2654 .width = 8,
2655 },
2656 .s[0] = {
2657 .src_sel_shift = 0,
2658 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2659 },
2660 .s[1] = {
2661 .src_sel_shift = 0,
2662 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2663 },
2664 .p[0] = {
2665 .pre_div_shift = 3,
2666 .pre_div_width = 2,
2667 },
2668 .p[1] = {
2669 .pre_div_shift = 3,
2670 .pre_div_width = 2,
2671 },
2672 .mux_sel_bit = 0,
2673 .freq_tbl = clk_tbl_gmac,
2674 .clkr = {
2675 .enable_reg = 0x3d00,
2676 .enable_mask = BIT(1),
2677 .hw.init = &(struct clk_init_data){
2678 .name = "gmac_core4_src",
2679 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2680 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2681 .ops = &clk_dyn_rcg_ops,
2682 },
2683 },
2684};
2685
2686static struct clk_branch gmac_core4_clk = {
2687 .halt_reg = 0x3c20,
2688 .halt_bit = 7,
2689 .hwcg_reg = 0x3d14,
2690 .hwcg_bit = 6,
2691 .clkr = {
2692 .enable_reg = 0x3d14,
2693 .enable_mask = BIT(4),
2694 .hw.init = &(struct clk_init_data){
2695 .name = "gmac_core4_clk",
2696 .parent_hws = (const struct clk_hw*[]){
2697 &gmac_core4_src.clkr.hw,
2698 },
2699 .num_parents = 1,
2700 .ops = &clk_branch_ops,
2701 .flags = CLK_SET_RATE_PARENT,
2702 },
2703 },
2704};
2705
2706static const struct freq_tbl clk_tbl_nss_tcm[] = {
2707 { 266000000, P_PLL0, 3, 0, 0 },
2708 { 400000000, P_PLL0, 2, 0, 0 },
2709 { }
2710};
2711
2712static struct clk_dyn_rcg nss_tcm_src = {
2713 .ns_reg[0] = 0x3dc4,
2714 .ns_reg[1] = 0x3dc8,
2715 .bank_reg = 0x3dc0,
2716 .s[0] = {
2717 .src_sel_shift = 0,
2718 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2719 },
2720 .s[1] = {
2721 .src_sel_shift = 0,
2722 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2723 },
2724 .p[0] = {
2725 .pre_div_shift = 3,
2726 .pre_div_width = 4,
2727 },
2728 .p[1] = {
2729 .pre_div_shift = 3,
2730 .pre_div_width = 4,
2731 },
2732 .mux_sel_bit = 0,
2733 .freq_tbl = clk_tbl_nss_tcm,
2734 .clkr = {
2735 .enable_reg = 0x3dc0,
2736 .enable_mask = BIT(1),
2737 .hw.init = &(struct clk_init_data){
2738 .name = "nss_tcm_src",
2739 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2740 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2741 .ops = &clk_dyn_rcg_ops,
2742 },
2743 },
2744};
2745
2746static struct clk_branch nss_tcm_clk = {
2747 .halt_reg = 0x3c20,
2748 .halt_bit = 14,
2749 .clkr = {
2750 .enable_reg = 0x3dd0,
2751 .enable_mask = BIT(6) | BIT(4),
2752 .hw.init = &(struct clk_init_data){
2753 .name = "nss_tcm_clk",
2754 .parent_hws = (const struct clk_hw*[]){
2755 &nss_tcm_src.clkr.hw,
2756 },
2757 .num_parents = 1,
2758 .ops = &clk_branch_ops,
2759 .flags = CLK_SET_RATE_PARENT,
2760 },
2761 },
2762};
2763
2764static const struct freq_tbl clk_tbl_nss_ipq8064[] = {
2765 { 110000000, P_PLL18, 1, 1, 5 },
2766 { 275000000, P_PLL18, 2, 0, 0 },
2767 { 550000000, P_PLL18, 1, 0, 0 },
2768 { 733000000, P_PLL18, 1, 0, 0 },
2769 { }
2770};
2771
2772static const struct freq_tbl clk_tbl_nss_ipq8065[] = {
2773 { 110000000, P_PLL18, 1, 1, 5 },
2774 { 275000000, P_PLL18, 2, 0, 0 },
2775 { 600000000, P_PLL18, 1, 0, 0 },
2776 { 800000000, P_PLL18, 1, 0, 0 },
2777 { }
2778};
2779
2780static struct clk_dyn_rcg ubi32_core1_src_clk = {
2781 .ns_reg[0] = 0x3d2c,
2782 .ns_reg[1] = 0x3d30,
2783 .md_reg[0] = 0x3d24,
2784 .md_reg[1] = 0x3d28,
2785 .bank_reg = 0x3d20,
2786 .mn[0] = {
2787 .mnctr_en_bit = 8,
2788 .mnctr_reset_bit = 7,
2789 .mnctr_mode_shift = 5,
2790 .n_val_shift = 16,
2791 .m_val_shift = 16,
2792 .width = 8,
2793 },
2794 .mn[1] = {
2795 .mnctr_en_bit = 8,
2796 .mnctr_reset_bit = 7,
2797 .mnctr_mode_shift = 5,
2798 .n_val_shift = 16,
2799 .m_val_shift = 16,
2800 .width = 8,
2801 },
2802 .s[0] = {
2803 .src_sel_shift = 0,
2804 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2805 },
2806 .s[1] = {
2807 .src_sel_shift = 0,
2808 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2809 },
2810 .p[0] = {
2811 .pre_div_shift = 3,
2812 .pre_div_width = 2,
2813 },
2814 .p[1] = {
2815 .pre_div_shift = 3,
2816 .pre_div_width = 2,
2817 },
2818 .mux_sel_bit = 0,
2819 /* nss freq table is selected based on the SoC compatible */
2820 .clkr = {
2821 .enable_reg = 0x3d20,
2822 .enable_mask = BIT(1),
2823 .hw.init = &(struct clk_init_data){
2824 .name = "ubi32_core1_src_clk",
2825 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2826 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2827 .ops = &clk_dyn_rcg_ops,
2828 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2829 },
2830 },
2831};
2832
2833static struct clk_dyn_rcg ubi32_core2_src_clk = {
2834 .ns_reg[0] = 0x3d4c,
2835 .ns_reg[1] = 0x3d50,
2836 .md_reg[0] = 0x3d44,
2837 .md_reg[1] = 0x3d48,
2838 .bank_reg = 0x3d40,
2839 .mn[0] = {
2840 .mnctr_en_bit = 8,
2841 .mnctr_reset_bit = 7,
2842 .mnctr_mode_shift = 5,
2843 .n_val_shift = 16,
2844 .m_val_shift = 16,
2845 .width = 8,
2846 },
2847 .mn[1] = {
2848 .mnctr_en_bit = 8,
2849 .mnctr_reset_bit = 7,
2850 .mnctr_mode_shift = 5,
2851 .n_val_shift = 16,
2852 .m_val_shift = 16,
2853 .width = 8,
2854 },
2855 .s[0] = {
2856 .src_sel_shift = 0,
2857 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2858 },
2859 .s[1] = {
2860 .src_sel_shift = 0,
2861 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2862 },
2863 .p[0] = {
2864 .pre_div_shift = 3,
2865 .pre_div_width = 2,
2866 },
2867 .p[1] = {
2868 .pre_div_shift = 3,
2869 .pre_div_width = 2,
2870 },
2871 .mux_sel_bit = 0,
2872 /* nss freq table is selected based on the SoC compatible */
2873 .clkr = {
2874 .enable_reg = 0x3d40,
2875 .enable_mask = BIT(1),
2876 .hw.init = &(struct clk_init_data){
2877 .name = "ubi32_core2_src_clk",
2878 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2879 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2880 .ops = &clk_dyn_rcg_ops,
2881 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2882 },
2883 },
2884};
2885
2886static const struct freq_tbl clk_tbl_ce5_core[] = {
2887 { 150000000, P_PLL3, 8, 1, 1 },
2888 { 213200000, P_PLL11, 5, 1, 1 },
2889 { }
2890};
2891
2892static struct clk_dyn_rcg ce5_core_src = {
2893 .ns_reg[0] = 0x36C4,
2894 .ns_reg[1] = 0x36C8,
2895 .bank_reg = 0x36C0,
2896 .s[0] = {
2897 .src_sel_shift = 0,
2898 .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
2899 },
2900 .s[1] = {
2901 .src_sel_shift = 0,
2902 .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
2903 },
2904 .p[0] = {
2905 .pre_div_shift = 3,
2906 .pre_div_width = 4,
2907 },
2908 .p[1] = {
2909 .pre_div_shift = 3,
2910 .pre_div_width = 4,
2911 },
2912 .mux_sel_bit = 0,
2913 .freq_tbl = clk_tbl_ce5_core,
2914 .clkr = {
2915 .enable_reg = 0x36C0,
2916 .enable_mask = BIT(1),
2917 .hw.init = &(struct clk_init_data){
2918 .name = "ce5_core_src",
2919 .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
2920 .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
2921 .ops = &clk_dyn_rcg_ops,
2922 },
2923 },
2924};
2925
2926static struct clk_branch ce5_core_clk = {
2927 .halt_reg = 0x2FDC,
2928 .halt_bit = 5,
2929 .hwcg_reg = 0x36CC,
2930 .hwcg_bit = 6,
2931 .clkr = {
2932 .enable_reg = 0x36CC,
2933 .enable_mask = BIT(4),
2934 .hw.init = &(struct clk_init_data){
2935 .name = "ce5_core_clk",
2936 .parent_hws = (const struct clk_hw*[]){
2937 &ce5_core_src.clkr.hw,
2938 },
2939 .num_parents = 1,
2940 .ops = &clk_branch_ops,
2941 .flags = CLK_SET_RATE_PARENT,
2942 },
2943 },
2944};
2945
2946static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
2947 { 160000000, P_PLL0, 5, 1, 1 },
2948 { 213200000, P_PLL11, 5, 1, 1 },
2949 { }
2950};
2951
2952static struct clk_dyn_rcg ce5_a_clk_src = {
2953 .ns_reg[0] = 0x3d84,
2954 .ns_reg[1] = 0x3d88,
2955 .bank_reg = 0x3d80,
2956 .s[0] = {
2957 .src_sel_shift = 0,
2958 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
2959 },
2960 .s[1] = {
2961 .src_sel_shift = 0,
2962 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
2963 },
2964 .p[0] = {
2965 .pre_div_shift = 3,
2966 .pre_div_width = 4,
2967 },
2968 .p[1] = {
2969 .pre_div_shift = 3,
2970 .pre_div_width = 4,
2971 },
2972 .mux_sel_bit = 0,
2973 .freq_tbl = clk_tbl_ce5_a_clk,
2974 .clkr = {
2975 .enable_reg = 0x3d80,
2976 .enable_mask = BIT(1),
2977 .hw.init = &(struct clk_init_data){
2978 .name = "ce5_a_clk_src",
2979 .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
2980 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
2981 .ops = &clk_dyn_rcg_ops,
2982 },
2983 },
2984};
2985
2986static struct clk_branch ce5_a_clk = {
2987 .halt_reg = 0x3c20,
2988 .halt_bit = 12,
2989 .hwcg_reg = 0x3d8c,
2990 .hwcg_bit = 6,
2991 .clkr = {
2992 .enable_reg = 0x3d8c,
2993 .enable_mask = BIT(4),
2994 .hw.init = &(struct clk_init_data){
2995 .name = "ce5_a_clk",
2996 .parent_hws = (const struct clk_hw*[]){
2997 &ce5_a_clk_src.clkr.hw,
2998 },
2999 .num_parents = 1,
3000 .ops = &clk_branch_ops,
3001 .flags = CLK_SET_RATE_PARENT,
3002 },
3003 },
3004};
3005
3006static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
3007 { 160000000, P_PLL0, 5, 1, 1 },
3008 { 213200000, P_PLL11, 5, 1, 1 },
3009 { }
3010};
3011
3012static struct clk_dyn_rcg ce5_h_clk_src = {
3013 .ns_reg[0] = 0x3c64,
3014 .ns_reg[1] = 0x3c68,
3015 .bank_reg = 0x3c60,
3016 .s[0] = {
3017 .src_sel_shift = 0,
3018 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
3019 },
3020 .s[1] = {
3021 .src_sel_shift = 0,
3022 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
3023 },
3024 .p[0] = {
3025 .pre_div_shift = 3,
3026 .pre_div_width = 4,
3027 },
3028 .p[1] = {
3029 .pre_div_shift = 3,
3030 .pre_div_width = 4,
3031 },
3032 .mux_sel_bit = 0,
3033 .freq_tbl = clk_tbl_ce5_h_clk,
3034 .clkr = {
3035 .enable_reg = 0x3c60,
3036 .enable_mask = BIT(1),
3037 .hw.init = &(struct clk_init_data){
3038 .name = "ce5_h_clk_src",
3039 .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
3040 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
3041 .ops = &clk_dyn_rcg_ops,
3042 },
3043 },
3044};
3045
3046static struct clk_branch ce5_h_clk = {
3047 .halt_reg = 0x3c20,
3048 .halt_bit = 11,
3049 .hwcg_reg = 0x3c6c,
3050 .hwcg_bit = 6,
3051 .clkr = {
3052 .enable_reg = 0x3c6c,
3053 .enable_mask = BIT(4),
3054 .hw.init = &(struct clk_init_data){
3055 .name = "ce5_h_clk",
3056 .parent_hws = (const struct clk_hw*[]){
3057 &ce5_h_clk_src.clkr.hw,
3058 },
3059 .num_parents = 1,
3060 .ops = &clk_branch_ops,
3061 .flags = CLK_SET_RATE_PARENT,
3062 },
3063 },
3064};
3065
3066static struct clk_regmap *gcc_ipq806x_clks[] = {
3067 [PLL0] = &pll0.clkr,
3068 [PLL0_VOTE] = &pll0_vote,
3069 [PLL3] = &pll3.clkr,
3070 [PLL4_VOTE] = &pll4_vote,
3071 [PLL8] = &pll8.clkr,
3072 [PLL8_VOTE] = &pll8_vote,
3073 [PLL11] = &pll11.clkr,
3074 [PLL14] = &pll14.clkr,
3075 [PLL14_VOTE] = &pll14_vote,
3076 [PLL18] = &pll18.clkr,
3077 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3078 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3079 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3080 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3081 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3082 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3083 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3084 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3085 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3086 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3087 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3088 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3089 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3090 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3091 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3092 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3093 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3094 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3095 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3096 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3097 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3098 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3099 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3100 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3101 [GP0_SRC] = &gp0_src.clkr,
3102 [GP0_CLK] = &gp0_clk.clkr,
3103 [GP1_SRC] = &gp1_src.clkr,
3104 [GP1_CLK] = &gp1_clk.clkr,
3105 [GP2_SRC] = &gp2_src.clkr,
3106 [GP2_CLK] = &gp2_clk.clkr,
3107 [PMEM_A_CLK] = &pmem_clk.clkr,
3108 [PRNG_SRC] = &prng_src.clkr,
3109 [PRNG_CLK] = &prng_clk.clkr,
3110 [SDC1_SRC] = &sdc1_src.clkr,
3111 [SDC1_CLK] = &sdc1_clk.clkr,
3112 [SDC3_SRC] = &sdc3_src.clkr,
3113 [SDC3_CLK] = &sdc3_clk.clkr,
3114 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3115 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3116 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3117 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3118 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3119 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3120 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3121 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3122 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3123 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3124 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3125 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3126 [ADM0_CLK] = &adm0_clk.clkr,
3127 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3128 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3129 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
3130 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3131 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
3132 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3133 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3134 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3135 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3136 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3137 [SATA_H_CLK] = &sata_h_clk.clkr,
3138 [SATA_CLK_SRC] = &sata_ref_src.clkr,
3139 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3140 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3141 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3142 [SATA_A_CLK] = &sata_a_clk.clkr,
3143 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3144 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
3145 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
3146 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
3147 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
3148 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
3149 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
3150 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
3151 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
3152 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
3153 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
3154 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
3155 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
3156 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
3157 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
3158 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
3159 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
3160 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
3161 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
3162 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
3163 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
3164 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3165 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
3166 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3167 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3168 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
3169 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
3170 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
3171 [EBI2_CLK] = &ebi2_clk.clkr,
3172 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
3173 [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
3174 [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
3175 [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
3176 [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
3177 [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
3178 [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
3179 [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
3180 [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
3181 [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
3182 [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
3183 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
3184 [NSSTCM_CLK] = &nss_tcm_clk.clkr,
3185 [PLL9] = &hfpll0.clkr,
3186 [PLL10] = &hfpll1.clkr,
3187 [PLL12] = &hfpll_l2.clkr,
3188 [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
3189 [CE5_A_CLK] = &ce5_a_clk.clkr,
3190 [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
3191 [CE5_H_CLK] = &ce5_h_clk.clkr,
3192 [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
3193 [CE5_CORE_CLK] = &ce5_core_clk.clkr,
3194};
3195
3196static const struct qcom_reset_map gcc_ipq806x_resets[] = {
3197 [QDSS_STM_RESET] = { 0x2060, 6 },
3198 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3199 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3200 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
3201 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3202 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
3203 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3204 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3205 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3206 [ADM0_C2_RESET] = { 0x220c, 4 },
3207 [ADM0_C1_RESET] = { 0x220c, 3 },
3208 [ADM0_C0_RESET] = { 0x220c, 2 },
3209 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3210 [ADM0_RESET] = { 0x220c, 0 },
3211 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3212 [QDSS_POR_RESET] = { 0x2260, 4 },
3213 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3214 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3215 [QDSS_AXI_RESET] = { 0x2260, 1 },
3216 [QDSS_DBG_RESET] = { 0x2260, 0 },
3217 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3218 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
3219 [PCIE_EXT_RESET] = { 0x22dc, 6 },
3220 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3221 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3222 [PCIE_POR_RESET] = { 0x22dc, 3 },
3223 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3224 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
3225 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3226 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3227 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3228 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3229 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3230 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3231 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3232 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3233 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3234 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3235 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3236 [PPSS_PROC_RESET] = { 0x2594, 1 },
3237 [PPSS_RESET] = { 0x2594, 0 },
3238 [DMA_BAM_RESET] = { 0x25c0, 7 },
3239 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3240 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3241 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3242 [TSIF_H_RESET] = { 0x2700, 7 },
3243 [CE1_H_RESET] = { 0x2720, 7 },
3244 [CE1_CORE_RESET] = { 0x2724, 7 },
3245 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3246 [CE2_H_RESET] = { 0x2740, 7 },
3247 [CE2_CORE_RESET] = { 0x2744, 7 },
3248 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3249 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3250 [RPM_PROC_RESET] = { 0x27c0, 7 },
3251 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3252 [SDC1_RESET] = { 0x2830, 0 },
3253 [SDC2_RESET] = { 0x2850, 0 },
3254 [SDC3_RESET] = { 0x2870, 0 },
3255 [SDC4_RESET] = { 0x2890, 0 },
3256 [USB_HS1_RESET] = { 0x2910, 0 },
3257 [USB_HSIC_RESET] = { 0x2934, 0 },
3258 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3259 [USB_FS1_RESET] = { 0x2974, 0 },
3260 [GSBI1_RESET] = { 0x29dc, 0 },
3261 [GSBI2_RESET] = { 0x29fc, 0 },
3262 [GSBI3_RESET] = { 0x2a1c, 0 },
3263 [GSBI4_RESET] = { 0x2a3c, 0 },
3264 [GSBI5_RESET] = { 0x2a5c, 0 },
3265 [GSBI6_RESET] = { 0x2a7c, 0 },
3266 [GSBI7_RESET] = { 0x2a9c, 0 },
3267 [SPDM_RESET] = { 0x2b6c, 0 },
3268 [SEC_CTRL_RESET] = { 0x2b80, 7 },
3269 [TLMM_H_RESET] = { 0x2ba0, 7 },
3270 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
3271 [SATA_RESET] = { 0x2c1c, 0 },
3272 [TSSC_RESET] = { 0x2ca0, 7 },
3273 [PDM_RESET] = { 0x2cc0, 12 },
3274 [MPM_H_RESET] = { 0x2da0, 7 },
3275 [MPM_RESET] = { 0x2da4, 0 },
3276 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3277 [PRNG_RESET] = { 0x2e80, 12 },
3278 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3279 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
3280 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3281 [PCIE_1_M_RESET] = { 0x3a98, 1 },
3282 [PCIE_1_S_RESET] = { 0x3a98, 0 },
3283 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
3284 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
3285 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
3286 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
3287 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
3288 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
3289 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
3290 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
3291 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
3292 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
3293 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
3294 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
3295 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
3296 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
3297 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
3298 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
3299 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
3300 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
3301 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
3302 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
3303 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
3304 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
3305 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
3306 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
3307 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
3308 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
3309 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
3310 [NSSFB0_RESET] = { 0x3b60, 6 },
3311 [NSSFB1_RESET] = { 0x3b60, 7 },
3312 [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
3313 [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
3314 [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
3315 [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
3316 [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
3317 [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
3318 [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
3319 [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
3320 [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
3321 [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
3322 [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
3323 [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
3324 [GMAC_AHB_RESET] = { 0x3e24, 0 },
3325 [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
3326 [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
3327 [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
3328 [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
3329 [CRYPTO_AHB_RESET] = { 0x3e10, 0},
3330 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
3331 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
3332 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
3333 [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
3334 [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
3335 [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
3336 [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
3337 [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
3338 [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
3339 [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
3340 [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
3341 [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
3342 [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
3343 [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
3344 [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
3345 [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
3346 [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
3347 [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
3348 [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
3349 [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
3350 [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
3351 [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
3352 [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
3353 [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
3354 [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
3355 [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
3356 [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
3357 [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
3358 [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
3359};
3360
3361static const struct regmap_config gcc_ipq806x_regmap_config = {
3362 .reg_bits = 32,
3363 .reg_stride = 4,
3364 .val_bits = 32,
3365 .max_register = 0x3e40,
3366 .fast_io = true,
3367};
3368
3369static const struct qcom_cc_desc gcc_ipq806x_desc = {
3370 .config = &gcc_ipq806x_regmap_config,
3371 .clks = gcc_ipq806x_clks,
3372 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
3373 .resets = gcc_ipq806x_resets,
3374 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
3375};
3376
3377static const struct of_device_id gcc_ipq806x_match_table[] = {
3378 { .compatible = "qcom,gcc-ipq8064" },
3379 { }
3380};
3381MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
3382
3383static int gcc_ipq806x_probe(struct platform_device *pdev)
3384{
3385 struct device *dev = &pdev->dev;
3386 struct regmap *regmap;
3387 int ret;
3388
3389 ret = qcom_cc_register_board_clk(dev, path: "cxo_board", name: "cxo", rate: 25000000);
3390 if (ret)
3391 return ret;
3392
3393 ret = qcom_cc_register_board_clk(dev, path: "pxo_board", name: "pxo", rate: 25000000);
3394 if (ret)
3395 return ret;
3396
3397 if (of_machine_is_compatible(compat: "qcom,ipq8065")) {
3398 ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
3399 ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
3400 } else {
3401 ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
3402 ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
3403 }
3404
3405 ret = qcom_cc_probe(pdev, desc: &gcc_ipq806x_desc);
3406 if (ret)
3407 return ret;
3408
3409 regmap = dev_get_regmap(dev, NULL);
3410 if (!regmap)
3411 return -ENODEV;
3412
3413 /* Setup PLL18 static bits */
3414 regmap_update_bits(map: regmap, reg: 0x31a4, mask: 0xffffffc0, val: 0x40000400);
3415 regmap_write(map: regmap, reg: 0x31b0, val: 0x3080);
3416
3417 /* Set GMAC footswitch sleep/wakeup values */
3418 regmap_write(map: regmap, reg: 0x3cb8, val: 8);
3419 regmap_write(map: regmap, reg: 0x3cd8, val: 8);
3420 regmap_write(map: regmap, reg: 0x3cf8, val: 8);
3421 regmap_write(map: regmap, reg: 0x3d18, val: 8);
3422
3423 return of_platform_populate(root: pdev->dev.of_node, NULL, NULL, parent: &pdev->dev);
3424}
3425
3426static struct platform_driver gcc_ipq806x_driver = {
3427 .probe = gcc_ipq806x_probe,
3428 .driver = {
3429 .name = "gcc-ipq806x",
3430 .of_match_table = gcc_ipq806x_match_table,
3431 },
3432};
3433
3434static int __init gcc_ipq806x_init(void)
3435{
3436 return platform_driver_register(&gcc_ipq806x_driver);
3437}
3438core_initcall(gcc_ipq806x_init);
3439
3440static void __exit gcc_ipq806x_exit(void)
3441{
3442 platform_driver_unregister(&gcc_ipq806x_driver);
3443}
3444module_exit(gcc_ipq806x_exit);
3445
3446MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
3447MODULE_LICENSE("GPL v2");
3448MODULE_ALIAS("platform:gcc-ipq806x");
3449

source code of linux/drivers/clk/qcom/gcc-ipq806x.c