1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2013, The Linux Foundation. All rights reserved.
4	*/
5
6	#include <linux/kernel.h>
7	#include <linux/bitops.h>
8	#include <linux/err.h>
9	#include <linux/platform_device.h>
10	#include <linux/module.h>
11	#include <linux/of.h>
12	#include <linux/clk-provider.h>
13	#include <linux/regmap.h>
14	#include <linux/reset-controller.h>
15
16	#include <dt-bindings/clock/qcom,gcc-msm8660.h>
17	#include <dt-bindings/reset/qcom,gcc-msm8660.h>
18
19	#include "common.h"
20	#include "clk-regmap.h"
21	#include "clk-pll.h"
22	#include "clk-rcg.h"
23	#include "clk-branch.h"
24	#include "reset.h"
25
26	static struct clk_pll pll8 = {
27	.l_reg = 0x3144,
28	.m_reg = 0x3148,
29	.n_reg = 0x314c,
30	.config_reg = 0x3154,
31	.mode_reg = 0x3140,
32	.status_reg = 0x3158,
33	.status_bit = 16,
34	.clkr.hw.init = &(struct clk_init_data){
35	.name = "pll8",
36	.parent_data = &(const struct clk_parent_data){
37	.fw_name = "pxo", .name = "pxo_board",
38	},
39	.num_parents = 1,
40	.ops = &clk_pll_ops,
41	},
42	};
43
44	static struct clk_regmap pll8_vote = {
45	.enable_reg = 0x34c0,
46	.enable_mask = BIT(8),
47	.hw.init = &(struct clk_init_data){
48	.name = "pll8_vote",
49	.parent_hws = (const struct clk_hw*[]){
50	&pll8.clkr.hw
51	},
52	.num_parents = 1,
53	.ops = &clk_pll_vote_ops,
54	},
55	};
56
57	enum {
58	P_PXO,
59	P_PLL8,
60	P_CXO,
61	};
62
63	static const struct parent_map gcc_pxo_pll8_map[] = {
64	{ P_PXO, 0 },
65	{ P_PLL8, 3 }
66	};
67
68	static const struct clk_parent_data gcc_pxo_pll8[] = {
69	{ .fw_name = "pxo", .name = "pxo_board" },
70	{ .hw = &pll8_vote.hw },
71	};
72
73	static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
74	{ P_PXO, 0 },
75	{ P_PLL8, 3 },
76	{ P_CXO, 5 }
77	};
78
79	static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
80	{ .fw_name = "pxo", .name = "pxo_board" },
81	{ .hw = &pll8_vote.hw },
82	{ .fw_name = "cxo", .name = "cxo_board" },
83	};
84
85	static struct freq_tbl clk_tbl_gsbi_uart[] = {
86	{ 1843200, P_PLL8, 2, 6, 625 },
87	{ 3686400, P_PLL8, 2, 12, 625 },
88	{ 7372800, P_PLL8, 2, 24, 625 },
89	{ 14745600, P_PLL8, 2, 48, 625 },
90	{ 16000000, P_PLL8, 4, 1, 6 },
91	{ 24000000, P_PLL8, 4, 1, 4 },
92	{ 32000000, P_PLL8, 4, 1, 3 },
93	{ 40000000, P_PLL8, 1, 5, 48 },
94	{ 46400000, P_PLL8, 1, 29, 240 },
95	{ 48000000, P_PLL8, 4, 1, 2 },
96	{ 51200000, P_PLL8, 1, 2, 15 },
97	{ 56000000, P_PLL8, 1, 7, 48 },
98	{ 58982400, P_PLL8, 1, 96, 625 },
99	{ 64000000, P_PLL8, 2, 1, 3 },
100	{ }
101	};
102
103	static struct clk_rcg gsbi1_uart_src = {
104	.ns_reg = 0x29d4,
105	.md_reg = 0x29d0,
106	.mn = {
107	.mnctr_en_bit = 8,
108	.mnctr_reset_bit = 7,
109	.mnctr_mode_shift = 5,
110	.n_val_shift = 16,
111	.m_val_shift = 16,
112	.width = 16,
113	},
114	.p = {
115	.pre_div_shift = 3,
116	.pre_div_width = 2,
117	},
118	.s = {
119	.src_sel_shift = 0,
120	.parent_map = gcc_pxo_pll8_map,
121	},
122	.freq_tbl = clk_tbl_gsbi_uart,
123	.clkr = {
124	.enable_reg = 0x29d4,
125	.enable_mask = BIT(11),
126	.hw.init = &(struct clk_init_data){
127	.name = "gsbi1_uart_src",
128	.parent_data = gcc_pxo_pll8,
129	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
130	.ops = &clk_rcg_ops,
131	.flags = CLK_SET_PARENT_GATE,
132	},
133	},
134	};
135
136	static struct clk_branch gsbi1_uart_clk = {
137	.halt_reg = 0x2fcc,
138	.halt_bit = 10,
139	.clkr = {
140	.enable_reg = 0x29d4,
141	.enable_mask = BIT(9),
142	.hw.init = &(struct clk_init_data){
143	.name = "gsbi1_uart_clk",
144	.parent_hws = (const struct clk_hw*[]){
145	&gsbi1_uart_src.clkr.hw
146	},
147	.num_parents = 1,
148	.ops = &clk_branch_ops,
149	.flags = CLK_SET_RATE_PARENT,
150	},
151	},
152	};
153
154	static struct clk_rcg gsbi2_uart_src = {
155	.ns_reg = 0x29f4,
156	.md_reg = 0x29f0,
157	.mn = {
158	.mnctr_en_bit = 8,
159	.mnctr_reset_bit = 7,
160	.mnctr_mode_shift = 5,
161	.n_val_shift = 16,
162	.m_val_shift = 16,
163	.width = 16,
164	},
165	.p = {
166	.pre_div_shift = 3,
167	.pre_div_width = 2,
168	},
169	.s = {
170	.src_sel_shift = 0,
171	.parent_map = gcc_pxo_pll8_map,
172	},
173	.freq_tbl = clk_tbl_gsbi_uart,
174	.clkr = {
175	.enable_reg = 0x29f4,
176	.enable_mask = BIT(11),
177	.hw.init = &(struct clk_init_data){
178	.name = "gsbi2_uart_src",
179	.parent_data = gcc_pxo_pll8,
180	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
181	.ops = &clk_rcg_ops,
182	.flags = CLK_SET_PARENT_GATE,
183	},
184	},
185	};
186
187	static struct clk_branch gsbi2_uart_clk = {
188	.halt_reg = 0x2fcc,
189	.halt_bit = 6,
190	.clkr = {
191	.enable_reg = 0x29f4,
192	.enable_mask = BIT(9),
193	.hw.init = &(struct clk_init_data){
194	.name = "gsbi2_uart_clk",
195	.parent_hws = (const struct clk_hw*[]){
196	&gsbi2_uart_src.clkr.hw
197	},
198	.num_parents = 1,
199	.ops = &clk_branch_ops,
200	.flags = CLK_SET_RATE_PARENT,
201	},
202	},
203	};
204
205	static struct clk_rcg gsbi3_uart_src = {
206	.ns_reg = 0x2a14,
207	.md_reg = 0x2a10,
208	.mn = {
209	.mnctr_en_bit = 8,
210	.mnctr_reset_bit = 7,
211	.mnctr_mode_shift = 5,
212	.n_val_shift = 16,
213	.m_val_shift = 16,
214	.width = 16,
215	},
216	.p = {
217	.pre_div_shift = 3,
218	.pre_div_width = 2,
219	},
220	.s = {
221	.src_sel_shift = 0,
222	.parent_map = gcc_pxo_pll8_map,
223	},
224	.freq_tbl = clk_tbl_gsbi_uart,
225	.clkr = {
226	.enable_reg = 0x2a14,
227	.enable_mask = BIT(11),
228	.hw.init = &(struct clk_init_data){
229	.name = "gsbi3_uart_src",
230	.parent_data = gcc_pxo_pll8,
231	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
232	.ops = &clk_rcg_ops,
233	.flags = CLK_SET_PARENT_GATE,
234	},
235	},
236	};
237
238	static struct clk_branch gsbi3_uart_clk = {
239	.halt_reg = 0x2fcc,
240	.halt_bit = 2,
241	.clkr = {
242	.enable_reg = 0x2a14,
243	.enable_mask = BIT(9),
244	.hw.init = &(struct clk_init_data){
245	.name = "gsbi3_uart_clk",
246	.parent_hws = (const struct clk_hw*[]){
247	&gsbi3_uart_src.clkr.hw
248	},
249	.num_parents = 1,
250	.ops = &clk_branch_ops,
251	.flags = CLK_SET_RATE_PARENT,
252	},
253	},
254	};
255
256	static struct clk_rcg gsbi4_uart_src = {
257	.ns_reg = 0x2a34,
258	.md_reg = 0x2a30,
259	.mn = {
260	.mnctr_en_bit = 8,
261	.mnctr_reset_bit = 7,
262	.mnctr_mode_shift = 5,
263	.n_val_shift = 16,
264	.m_val_shift = 16,
265	.width = 16,
266	},
267	.p = {
268	.pre_div_shift = 3,
269	.pre_div_width = 2,
270	},
271	.s = {
272	.src_sel_shift = 0,
273	.parent_map = gcc_pxo_pll8_map,
274	},
275	.freq_tbl = clk_tbl_gsbi_uart,
276	.clkr = {
277	.enable_reg = 0x2a34,
278	.enable_mask = BIT(11),
279	.hw.init = &(struct clk_init_data){
280	.name = "gsbi4_uart_src",
281	.parent_data = gcc_pxo_pll8,
282	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
283	.ops = &clk_rcg_ops,
284	.flags = CLK_SET_PARENT_GATE,
285	},
286	},
287	};
288
289	static struct clk_branch gsbi4_uart_clk = {
290	.halt_reg = 0x2fd0,
291	.halt_bit = 26,
292	.clkr = {
293	.enable_reg = 0x2a34,
294	.enable_mask = BIT(9),
295	.hw.init = &(struct clk_init_data){
296	.name = "gsbi4_uart_clk",
297	.parent_hws = (const struct clk_hw*[]){
298	&gsbi4_uart_src.clkr.hw
299	},
300	.num_parents = 1,
301	.ops = &clk_branch_ops,
302	.flags = CLK_SET_RATE_PARENT,
303	},
304	},
305	};
306
307	static struct clk_rcg gsbi5_uart_src = {
308	.ns_reg = 0x2a54,
309	.md_reg = 0x2a50,
310	.mn = {
311	.mnctr_en_bit = 8,
312	.mnctr_reset_bit = 7,
313	.mnctr_mode_shift = 5,
314	.n_val_shift = 16,
315	.m_val_shift = 16,
316	.width = 16,
317	},
318	.p = {
319	.pre_div_shift = 3,
320	.pre_div_width = 2,
321	},
322	.s = {
323	.src_sel_shift = 0,
324	.parent_map = gcc_pxo_pll8_map,
325	},
326	.freq_tbl = clk_tbl_gsbi_uart,
327	.clkr = {
328	.enable_reg = 0x2a54,
329	.enable_mask = BIT(11),
330	.hw.init = &(struct clk_init_data){
331	.name = "gsbi5_uart_src",
332	.parent_data = gcc_pxo_pll8,
333	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
334	.ops = &clk_rcg_ops,
335	.flags = CLK_SET_PARENT_GATE,
336	},
337	},
338	};
339
340	static struct clk_branch gsbi5_uart_clk = {
341	.halt_reg = 0x2fd0,
342	.halt_bit = 22,
343	.clkr = {
344	.enable_reg = 0x2a54,
345	.enable_mask = BIT(9),
346	.hw.init = &(struct clk_init_data){
347	.name = "gsbi5_uart_clk",
348	.parent_hws = (const struct clk_hw*[]){
349	&gsbi5_uart_src.clkr.hw
350	},
351	.num_parents = 1,
352	.ops = &clk_branch_ops,
353	.flags = CLK_SET_RATE_PARENT,
354	},
355	},
356	};
357
358	static struct clk_rcg gsbi6_uart_src = {
359	.ns_reg = 0x2a74,
360	.md_reg = 0x2a70,
361	.mn = {
362	.mnctr_en_bit = 8,
363	.mnctr_reset_bit = 7,
364	.mnctr_mode_shift = 5,
365	.n_val_shift = 16,
366	.m_val_shift = 16,
367	.width = 16,
368	},
369	.p = {
370	.pre_div_shift = 3,
371	.pre_div_width = 2,
372	},
373	.s = {
374	.src_sel_shift = 0,
375	.parent_map = gcc_pxo_pll8_map,
376	},
377	.freq_tbl = clk_tbl_gsbi_uart,
378	.clkr = {
379	.enable_reg = 0x2a74,
380	.enable_mask = BIT(11),
381	.hw.init = &(struct clk_init_data){
382	.name = "gsbi6_uart_src",
383	.parent_data = gcc_pxo_pll8,
384	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
385	.ops = &clk_rcg_ops,
386	.flags = CLK_SET_PARENT_GATE,
387	},
388	},
389	};
390
391	static struct clk_branch gsbi6_uart_clk = {
392	.halt_reg = 0x2fd0,
393	.halt_bit = 18,
394	.clkr = {
395	.enable_reg = 0x2a74,
396	.enable_mask = BIT(9),
397	.hw.init = &(struct clk_init_data){
398	.name = "gsbi6_uart_clk",
399	.parent_hws = (const struct clk_hw*[]){
400	&gsbi6_uart_src.clkr.hw
401	},
402	.num_parents = 1,
403	.ops = &clk_branch_ops,
404	.flags = CLK_SET_RATE_PARENT,
405	},
406	},
407	};
408
409	static struct clk_rcg gsbi7_uart_src = {
410	.ns_reg = 0x2a94,
411	.md_reg = 0x2a90,
412	.mn = {
413	.mnctr_en_bit = 8,
414	.mnctr_reset_bit = 7,
415	.mnctr_mode_shift = 5,
416	.n_val_shift = 16,
417	.m_val_shift = 16,
418	.width = 16,
419	},
420	.p = {
421	.pre_div_shift = 3,
422	.pre_div_width = 2,
423	},
424	.s = {
425	.src_sel_shift = 0,
426	.parent_map = gcc_pxo_pll8_map,
427	},
428	.freq_tbl = clk_tbl_gsbi_uart,
429	.clkr = {
430	.enable_reg = 0x2a94,
431	.enable_mask = BIT(11),
432	.hw.init = &(struct clk_init_data){
433	.name = "gsbi7_uart_src",
434	.parent_data = gcc_pxo_pll8,
435	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
436	.ops = &clk_rcg_ops,
437	.flags = CLK_SET_PARENT_GATE,
438	},
439	},
440	};
441
442	static struct clk_branch gsbi7_uart_clk = {
443	.halt_reg = 0x2fd0,
444	.halt_bit = 14,
445	.clkr = {
446	.enable_reg = 0x2a94,
447	.enable_mask = BIT(9),
448	.hw.init = &(struct clk_init_data){
449	.name = "gsbi7_uart_clk",
450	.parent_hws = (const struct clk_hw*[]){
451	&gsbi7_uart_src.clkr.hw
452	},
453	.num_parents = 1,
454	.ops = &clk_branch_ops,
455	.flags = CLK_SET_RATE_PARENT,
456	},
457	},
458	};
459
460	static struct clk_rcg gsbi8_uart_src = {
461	.ns_reg = 0x2ab4,
462	.md_reg = 0x2ab0,
463	.mn = {
464	.mnctr_en_bit = 8,
465	.mnctr_reset_bit = 7,
466	.mnctr_mode_shift = 5,
467	.n_val_shift = 16,
468	.m_val_shift = 16,
469	.width = 16,
470	},
471	.p = {
472	.pre_div_shift = 3,
473	.pre_div_width = 2,
474	},
475	.s = {
476	.src_sel_shift = 0,
477	.parent_map = gcc_pxo_pll8_map,
478	},
479	.freq_tbl = clk_tbl_gsbi_uart,
480	.clkr = {
481	.enable_reg = 0x2ab4,
482	.enable_mask = BIT(11),
483	.hw.init = &(struct clk_init_data){
484	.name = "gsbi8_uart_src",
485	.parent_data = gcc_pxo_pll8,
486	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
487	.ops = &clk_rcg_ops,
488	.flags = CLK_SET_PARENT_GATE,
489	},
490	},
491	};
492
493	static struct clk_branch gsbi8_uart_clk = {
494	.halt_reg = 0x2fd0,
495	.halt_bit = 10,
496	.clkr = {
497	.enable_reg = 0x2ab4,
498	.enable_mask = BIT(9),
499	.hw.init = &(struct clk_init_data){
500	.name = "gsbi8_uart_clk",
501	.parent_hws = (const struct clk_hw*[]){
502	&gsbi8_uart_src.clkr.hw
503	},
504	.num_parents = 1,
505	.ops = &clk_branch_ops,
506	.flags = CLK_SET_RATE_PARENT,
507	},
508	},
509	};
510
511	static struct clk_rcg gsbi9_uart_src = {
512	.ns_reg = 0x2ad4,
513	.md_reg = 0x2ad0,
514	.mn = {
515	.mnctr_en_bit = 8,
516	.mnctr_reset_bit = 7,
517	.mnctr_mode_shift = 5,
518	.n_val_shift = 16,
519	.m_val_shift = 16,
520	.width = 16,
521	},
522	.p = {
523	.pre_div_shift = 3,
524	.pre_div_width = 2,
525	},
526	.s = {
527	.src_sel_shift = 0,
528	.parent_map = gcc_pxo_pll8_map,
529	},
530	.freq_tbl = clk_tbl_gsbi_uart,
531	.clkr = {
532	.enable_reg = 0x2ad4,
533	.enable_mask = BIT(11),
534	.hw.init = &(struct clk_init_data){
535	.name = "gsbi9_uart_src",
536	.parent_data = gcc_pxo_pll8,
537	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
538	.ops = &clk_rcg_ops,
539	.flags = CLK_SET_PARENT_GATE,
540	},
541	},
542	};
543
544	static struct clk_branch gsbi9_uart_clk = {
545	.halt_reg = 0x2fd0,
546	.halt_bit = 6,
547	.clkr = {
548	.enable_reg = 0x2ad4,
549	.enable_mask = BIT(9),
550	.hw.init = &(struct clk_init_data){
551	.name = "gsbi9_uart_clk",
552	.parent_hws = (const struct clk_hw*[]){
553	&gsbi9_uart_src.clkr.hw
554	},
555	.num_parents = 1,
556	.ops = &clk_branch_ops,
557	.flags = CLK_SET_RATE_PARENT,
558	},
559	},
560	};
561
562	static struct clk_rcg gsbi10_uart_src = {
563	.ns_reg = 0x2af4,
564	.md_reg = 0x2af0,
565	.mn = {
566	.mnctr_en_bit = 8,
567	.mnctr_reset_bit = 7,
568	.mnctr_mode_shift = 5,
569	.n_val_shift = 16,
570	.m_val_shift = 16,
571	.width = 16,
572	},
573	.p = {
574	.pre_div_shift = 3,
575	.pre_div_width = 2,
576	},
577	.s = {
578	.src_sel_shift = 0,
579	.parent_map = gcc_pxo_pll8_map,
580	},
581	.freq_tbl = clk_tbl_gsbi_uart,
582	.clkr = {
583	.enable_reg = 0x2af4,
584	.enable_mask = BIT(11),
585	.hw.init = &(struct clk_init_data){
586	.name = "gsbi10_uart_src",
587	.parent_data = gcc_pxo_pll8,
588	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
589	.ops = &clk_rcg_ops,
590	.flags = CLK_SET_PARENT_GATE,
591	},
592	},
593	};
594
595	static struct clk_branch gsbi10_uart_clk = {
596	.halt_reg = 0x2fd0,
597	.halt_bit = 2,
598	.clkr = {
599	.enable_reg = 0x2af4,
600	.enable_mask = BIT(9),
601	.hw.init = &(struct clk_init_data){
602	.name = "gsbi10_uart_clk",
603	.parent_hws = (const struct clk_hw*[]){
604	&gsbi10_uart_src.clkr.hw
605	},
606	.num_parents = 1,
607	.ops = &clk_branch_ops,
608	.flags = CLK_SET_RATE_PARENT,
609	},
610	},
611	};
612
613	static struct clk_rcg gsbi11_uart_src = {
614	.ns_reg = 0x2b14,
615	.md_reg = 0x2b10,
616	.mn = {
617	.mnctr_en_bit = 8,
618	.mnctr_reset_bit = 7,
619	.mnctr_mode_shift = 5,
620	.n_val_shift = 16,
621	.m_val_shift = 16,
622	.width = 16,
623	},
624	.p = {
625	.pre_div_shift = 3,
626	.pre_div_width = 2,
627	},
628	.s = {
629	.src_sel_shift = 0,
630	.parent_map = gcc_pxo_pll8_map,
631	},
632	.freq_tbl = clk_tbl_gsbi_uart,
633	.clkr = {
634	.enable_reg = 0x2b14,
635	.enable_mask = BIT(11),
636	.hw.init = &(struct clk_init_data){
637	.name = "gsbi11_uart_src",
638	.parent_data = gcc_pxo_pll8,
639	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
640	.ops = &clk_rcg_ops,
641	.flags = CLK_SET_PARENT_GATE,
642	},
643	},
644	};
645
646	static struct clk_branch gsbi11_uart_clk = {
647	.halt_reg = 0x2fd4,
648	.halt_bit = 17,
649	.clkr = {
650	.enable_reg = 0x2b14,
651	.enable_mask = BIT(9),
652	.hw.init = &(struct clk_init_data){
653	.name = "gsbi11_uart_clk",
654	.parent_hws = (const struct clk_hw*[]){
655	&gsbi11_uart_src.clkr.hw
656	},
657	.num_parents = 1,
658	.ops = &clk_branch_ops,
659	.flags = CLK_SET_RATE_PARENT,
660	},
661	},
662	};
663
664	static struct clk_rcg gsbi12_uart_src = {
665	.ns_reg = 0x2b34,
666	.md_reg = 0x2b30,
667	.mn = {
668	.mnctr_en_bit = 8,
669	.mnctr_reset_bit = 7,
670	.mnctr_mode_shift = 5,
671	.n_val_shift = 16,
672	.m_val_shift = 16,
673	.width = 16,
674	},
675	.p = {
676	.pre_div_shift = 3,
677	.pre_div_width = 2,
678	},
679	.s = {
680	.src_sel_shift = 0,
681	.parent_map = gcc_pxo_pll8_map,
682	},
683	.freq_tbl = clk_tbl_gsbi_uart,
684	.clkr = {
685	.enable_reg = 0x2b34,
686	.enable_mask = BIT(11),
687	.hw.init = &(struct clk_init_data){
688	.name = "gsbi12_uart_src",
689	.parent_data = gcc_pxo_pll8,
690	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
691	.ops = &clk_rcg_ops,
692	.flags = CLK_SET_PARENT_GATE,
693	},
694	},
695	};
696
697	static struct clk_branch gsbi12_uart_clk = {
698	.halt_reg = 0x2fd4,
699	.halt_bit = 13,
700	.clkr = {
701	.enable_reg = 0x2b34,
702	.enable_mask = BIT(9),
703	.hw.init = &(struct clk_init_data){
704	.name = "gsbi12_uart_clk",
705	.parent_hws = (const struct clk_hw*[]){
706	&gsbi12_uart_src.clkr.hw
707	},
708	.num_parents = 1,
709	.ops = &clk_branch_ops,
710	.flags = CLK_SET_RATE_PARENT,
711	},
712	},
713	};
714
715	static struct freq_tbl clk_tbl_gsbi_qup[] = {
716	{ 1100000, P_PXO, 1, 2, 49 },
717	{ 5400000, P_PXO, 1, 1, 5 },
718	{ 10800000, P_PXO, 1, 2, 5 },
719	{ 15060000, P_PLL8, 1, 2, 51 },
720	{ 24000000, P_PLL8, 4, 1, 4 },
721	{ 25600000, P_PLL8, 1, 1, 15 },
722	{ 27000000, P_PXO, 1, 0, 0 },
723	{ 48000000, P_PLL8, 4, 1, 2 },
724	{ 51200000, P_PLL8, 1, 2, 15 },
725	{ }
726	};
727
728	static struct clk_rcg gsbi1_qup_src = {
729	.ns_reg = 0x29cc,
730	.md_reg = 0x29c8,
731	.mn = {
732	.mnctr_en_bit = 8,
733	.mnctr_reset_bit = 7,
734	.mnctr_mode_shift = 5,
735	.n_val_shift = 16,
736	.m_val_shift = 16,
737	.width = 8,
738	},
739	.p = {
740	.pre_div_shift = 3,
741	.pre_div_width = 2,
742	},
743	.s = {
744	.src_sel_shift = 0,
745	.parent_map = gcc_pxo_pll8_map,
746	},
747	.freq_tbl = clk_tbl_gsbi_qup,
748	.clkr = {
749	.enable_reg = 0x29cc,
750	.enable_mask = BIT(11),
751	.hw.init = &(struct clk_init_data){
752	.name = "gsbi1_qup_src",
753	.parent_data = gcc_pxo_pll8,
754	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
755	.ops = &clk_rcg_ops,
756	.flags = CLK_SET_PARENT_GATE,
757	},
758	},
759	};
760
761	static struct clk_branch gsbi1_qup_clk = {
762	.halt_reg = 0x2fcc,
763	.halt_bit = 9,
764	.clkr = {
765	.enable_reg = 0x29cc,
766	.enable_mask = BIT(9),
767	.hw.init = &(struct clk_init_data){
768	.name = "gsbi1_qup_clk",
769	.parent_hws = (const struct clk_hw*[]){
770	&gsbi1_qup_src.clkr.hw
771	},
772	.num_parents = 1,
773	.ops = &clk_branch_ops,
774	.flags = CLK_SET_RATE_PARENT,
775	},
776	},
777	};
778
779	static struct clk_rcg gsbi2_qup_src = {
780	.ns_reg = 0x29ec,
781	.md_reg = 0x29e8,
782	.mn = {
783	.mnctr_en_bit = 8,
784	.mnctr_reset_bit = 7,
785	.mnctr_mode_shift = 5,
786	.n_val_shift = 16,
787	.m_val_shift = 16,
788	.width = 8,
789	},
790	.p = {
791	.pre_div_shift = 3,
792	.pre_div_width = 2,
793	},
794	.s = {
795	.src_sel_shift = 0,
796	.parent_map = gcc_pxo_pll8_map,
797	},
798	.freq_tbl = clk_tbl_gsbi_qup,
799	.clkr = {
800	.enable_reg = 0x29ec,
801	.enable_mask = BIT(11),
802	.hw.init = &(struct clk_init_data){
803	.name = "gsbi2_qup_src",
804	.parent_data = gcc_pxo_pll8,
805	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
806	.ops = &clk_rcg_ops,
807	.flags = CLK_SET_PARENT_GATE,
808	},
809	},
810	};
811
812	static struct clk_branch gsbi2_qup_clk = {
813	.halt_reg = 0x2fcc,
814	.halt_bit = 4,
815	.clkr = {
816	.enable_reg = 0x29ec,
817	.enable_mask = BIT(9),
818	.hw.init = &(struct clk_init_data){
819	.name = "gsbi2_qup_clk",
820	.parent_hws = (const struct clk_hw*[]){
821	&gsbi2_qup_src.clkr.hw
822	},
823	.num_parents = 1,
824	.ops = &clk_branch_ops,
825	.flags = CLK_SET_RATE_PARENT,
826	},
827	},
828	};
829
830	static struct clk_rcg gsbi3_qup_src = {
831	.ns_reg = 0x2a0c,
832	.md_reg = 0x2a08,
833	.mn = {
834	.mnctr_en_bit = 8,
835	.mnctr_reset_bit = 7,
836	.mnctr_mode_shift = 5,
837	.n_val_shift = 16,
838	.m_val_shift = 16,
839	.width = 8,
840	},
841	.p = {
842	.pre_div_shift = 3,
843	.pre_div_width = 2,
844	},
845	.s = {
846	.src_sel_shift = 0,
847	.parent_map = gcc_pxo_pll8_map,
848	},
849	.freq_tbl = clk_tbl_gsbi_qup,
850	.clkr = {
851	.enable_reg = 0x2a0c,
852	.enable_mask = BIT(11),
853	.hw.init = &(struct clk_init_data){
854	.name = "gsbi3_qup_src",
855	.parent_data = gcc_pxo_pll8,
856	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
857	.ops = &clk_rcg_ops,
858	.flags = CLK_SET_PARENT_GATE,
859	},
860	},
861	};
862
863	static struct clk_branch gsbi3_qup_clk = {
864	.halt_reg = 0x2fcc,
865	.halt_bit = 0,
866	.clkr = {
867	.enable_reg = 0x2a0c,
868	.enable_mask = BIT(9),
869	.hw.init = &(struct clk_init_data){
870	.name = "gsbi3_qup_clk",
871	.parent_hws = (const struct clk_hw*[]){
872	&gsbi3_qup_src.clkr.hw
873	},
874	.num_parents = 1,
875	.ops = &clk_branch_ops,
876	.flags = CLK_SET_RATE_PARENT,
877	},
878	},
879	};
880
881	static struct clk_rcg gsbi4_qup_src = {
882	.ns_reg = 0x2a2c,
883	.md_reg = 0x2a28,
884	.mn = {
885	.mnctr_en_bit = 8,
886	.mnctr_reset_bit = 7,
887	.mnctr_mode_shift = 5,
888	.n_val_shift = 16,
889	.m_val_shift = 16,
890	.width = 8,
891	},
892	.p = {
893	.pre_div_shift = 3,
894	.pre_div_width = 2,
895	},
896	.s = {
897	.src_sel_shift = 0,
898	.parent_map = gcc_pxo_pll8_map,
899	},
900	.freq_tbl = clk_tbl_gsbi_qup,
901	.clkr = {
902	.enable_reg = 0x2a2c,
903	.enable_mask = BIT(11),
904	.hw.init = &(struct clk_init_data){
905	.name = "gsbi4_qup_src",
906	.parent_data = gcc_pxo_pll8,
907	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
908	.ops = &clk_rcg_ops,
909	.flags = CLK_SET_PARENT_GATE,
910	},
911	},
912	};
913
914	static struct clk_branch gsbi4_qup_clk = {
915	.halt_reg = 0x2fd0,
916	.halt_bit = 24,
917	.clkr = {
918	.enable_reg = 0x2a2c,
919	.enable_mask = BIT(9),
920	.hw.init = &(struct clk_init_data){
921	.name = "gsbi4_qup_clk",
922	.parent_hws = (const struct clk_hw*[]){
923	&gsbi4_qup_src.clkr.hw
924	},
925	.num_parents = 1,
926	.ops = &clk_branch_ops,
927	.flags = CLK_SET_RATE_PARENT,
928	},
929	},
930	};
931
932	static struct clk_rcg gsbi5_qup_src = {
933	.ns_reg = 0x2a4c,
934	.md_reg = 0x2a48,
935	.mn = {
936	.mnctr_en_bit = 8,
937	.mnctr_reset_bit = 7,
938	.mnctr_mode_shift = 5,
939	.n_val_shift = 16,
940	.m_val_shift = 16,
941	.width = 8,
942	},
943	.p = {
944	.pre_div_shift = 3,
945	.pre_div_width = 2,
946	},
947	.s = {
948	.src_sel_shift = 0,
949	.parent_map = gcc_pxo_pll8_map,
950	},
951	.freq_tbl = clk_tbl_gsbi_qup,
952	.clkr = {
953	.enable_reg = 0x2a4c,
954	.enable_mask = BIT(11),
955	.hw.init = &(struct clk_init_data){
956	.name = "gsbi5_qup_src",
957	.parent_data = gcc_pxo_pll8,
958	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
959	.ops = &clk_rcg_ops,
960	.flags = CLK_SET_PARENT_GATE,
961	},
962	},
963	};
964
965	static struct clk_branch gsbi5_qup_clk = {
966	.halt_reg = 0x2fd0,
967	.halt_bit = 20,
968	.clkr = {
969	.enable_reg = 0x2a4c,
970	.enable_mask = BIT(9),
971	.hw.init = &(struct clk_init_data){
972	.name = "gsbi5_qup_clk",
973	.parent_hws = (const struct clk_hw*[]){
974	&gsbi5_qup_src.clkr.hw
975	},
976	.num_parents = 1,
977	.ops = &clk_branch_ops,
978	.flags = CLK_SET_RATE_PARENT,
979	},
980	},
981	};
982
983	static struct clk_rcg gsbi6_qup_src = {
984	.ns_reg = 0x2a6c,
985	.md_reg = 0x2a68,
986	.mn = {
987	.mnctr_en_bit = 8,
988	.mnctr_reset_bit = 7,
989	.mnctr_mode_shift = 5,
990	.n_val_shift = 16,
991	.m_val_shift = 16,
992	.width = 8,
993	},
994	.p = {
995	.pre_div_shift = 3,
996	.pre_div_width = 2,
997	},
998	.s = {
999	.src_sel_shift = 0,
1000	.parent_map = gcc_pxo_pll8_map,
1001	},
1002	.freq_tbl = clk_tbl_gsbi_qup,
1003	.clkr = {
1004	.enable_reg = 0x2a6c,
1005	.enable_mask = BIT(11),
1006	.hw.init = &(struct clk_init_data){
1007	.name = "gsbi6_qup_src",
1008	.parent_data = gcc_pxo_pll8,
1009	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1010	.ops = &clk_rcg_ops,
1011	.flags = CLK_SET_PARENT_GATE,
1012	},
1013	},
1014	};
1015
1016	static struct clk_branch gsbi6_qup_clk = {
1017	.halt_reg = 0x2fd0,
1018	.halt_bit = 16,
1019	.clkr = {
1020	.enable_reg = 0x2a6c,
1021	.enable_mask = BIT(9),
1022	.hw.init = &(struct clk_init_data){
1023	.name = "gsbi6_qup_clk",
1024	.parent_hws = (const struct clk_hw*[]){
1025	&gsbi6_qup_src.clkr.hw
1026	},
1027	.num_parents = 1,
1028	.ops = &clk_branch_ops,
1029	.flags = CLK_SET_RATE_PARENT,
1030	},
1031	},
1032	};
1033
1034	static struct clk_rcg gsbi7_qup_src = {
1035	.ns_reg = 0x2a8c,
1036	.md_reg = 0x2a88,
1037	.mn = {
1038	.mnctr_en_bit = 8,
1039	.mnctr_reset_bit = 7,
1040	.mnctr_mode_shift = 5,
1041	.n_val_shift = 16,
1042	.m_val_shift = 16,
1043	.width = 8,
1044	},
1045	.p = {
1046	.pre_div_shift = 3,
1047	.pre_div_width = 2,
1048	},
1049	.s = {
1050	.src_sel_shift = 0,
1051	.parent_map = gcc_pxo_pll8_map,
1052	},
1053	.freq_tbl = clk_tbl_gsbi_qup,
1054	.clkr = {
1055	.enable_reg = 0x2a8c,
1056	.enable_mask = BIT(11),
1057	.hw.init = &(struct clk_init_data){
1058	.name = "gsbi7_qup_src",
1059	.parent_data = gcc_pxo_pll8,
1060	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1061	.ops = &clk_rcg_ops,
1062	.flags = CLK_SET_PARENT_GATE,
1063	},
1064	},
1065	};
1066
1067	static struct clk_branch gsbi7_qup_clk = {
1068	.halt_reg = 0x2fd0,
1069	.halt_bit = 12,
1070	.clkr = {
1071	.enable_reg = 0x2a8c,
1072	.enable_mask = BIT(9),
1073	.hw.init = &(struct clk_init_data){
1074	.name = "gsbi7_qup_clk",
1075	.parent_hws = (const struct clk_hw*[]){
1076	&gsbi7_qup_src.clkr.hw
1077	},
1078	.num_parents = 1,
1079	.ops = &clk_branch_ops,
1080	.flags = CLK_SET_RATE_PARENT,
1081	},
1082	},
1083	};
1084
1085	static struct clk_rcg gsbi8_qup_src = {
1086	.ns_reg = 0x2aac,
1087	.md_reg = 0x2aa8,
1088	.mn = {
1089	.mnctr_en_bit = 8,
1090	.mnctr_reset_bit = 7,
1091	.mnctr_mode_shift = 5,
1092	.n_val_shift = 16,
1093	.m_val_shift = 16,
1094	.width = 8,
1095	},
1096	.p = {
1097	.pre_div_shift = 3,
1098	.pre_div_width = 2,
1099	},
1100	.s = {
1101	.src_sel_shift = 0,
1102	.parent_map = gcc_pxo_pll8_map,
1103	},
1104	.freq_tbl = clk_tbl_gsbi_qup,
1105	.clkr = {
1106	.enable_reg = 0x2aac,
1107	.enable_mask = BIT(11),
1108	.hw.init = &(struct clk_init_data){
1109	.name = "gsbi8_qup_src",
1110	.parent_data = gcc_pxo_pll8,
1111	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1112	.ops = &clk_rcg_ops,
1113	.flags = CLK_SET_PARENT_GATE,
1114	},
1115	},
1116	};
1117
1118	static struct clk_branch gsbi8_qup_clk = {
1119	.halt_reg = 0x2fd0,
1120	.halt_bit = 8,
1121	.clkr = {
1122	.enable_reg = 0x2aac,
1123	.enable_mask = BIT(9),
1124	.hw.init = &(struct clk_init_data){
1125	.name = "gsbi8_qup_clk",
1126	.parent_hws = (const struct clk_hw*[]){
1127	&gsbi8_qup_src.clkr.hw
1128	},
1129	.num_parents = 1,
1130	.ops = &clk_branch_ops,
1131	.flags = CLK_SET_RATE_PARENT,
1132	},
1133	},
1134	};
1135
1136	static struct clk_rcg gsbi9_qup_src = {
1137	.ns_reg = 0x2acc,
1138	.md_reg = 0x2ac8,
1139	.mn = {
1140	.mnctr_en_bit = 8,
1141	.mnctr_reset_bit = 7,
1142	.mnctr_mode_shift = 5,
1143	.n_val_shift = 16,
1144	.m_val_shift = 16,
1145	.width = 8,
1146	},
1147	.p = {
1148	.pre_div_shift = 3,
1149	.pre_div_width = 2,
1150	},
1151	.s = {
1152	.src_sel_shift = 0,
1153	.parent_map = gcc_pxo_pll8_map,
1154	},
1155	.freq_tbl = clk_tbl_gsbi_qup,
1156	.clkr = {
1157	.enable_reg = 0x2acc,
1158	.enable_mask = BIT(11),
1159	.hw.init = &(struct clk_init_data){
1160	.name = "gsbi9_qup_src",
1161	.parent_data = gcc_pxo_pll8,
1162	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1163	.ops = &clk_rcg_ops,
1164	.flags = CLK_SET_PARENT_GATE,
1165	},
1166	},
1167	};
1168
1169	static struct clk_branch gsbi9_qup_clk = {
1170	.halt_reg = 0x2fd0,
1171	.halt_bit = 4,
1172	.clkr = {
1173	.enable_reg = 0x2acc,
1174	.enable_mask = BIT(9),
1175	.hw.init = &(struct clk_init_data){
1176	.name = "gsbi9_qup_clk",
1177	.parent_hws = (const struct clk_hw*[]){
1178	&gsbi9_qup_src.clkr.hw
1179	},
1180	.num_parents = 1,
1181	.ops = &clk_branch_ops,
1182	.flags = CLK_SET_RATE_PARENT,
1183	},
1184	},
1185	};
1186
1187	static struct clk_rcg gsbi10_qup_src = {
1188	.ns_reg = 0x2aec,
1189	.md_reg = 0x2ae8,
1190	.mn = {
1191	.mnctr_en_bit = 8,
1192	.mnctr_reset_bit = 7,
1193	.mnctr_mode_shift = 5,
1194	.n_val_shift = 16,
1195	.m_val_shift = 16,
1196	.width = 8,
1197	},
1198	.p = {
1199	.pre_div_shift = 3,
1200	.pre_div_width = 2,
1201	},
1202	.s = {
1203	.src_sel_shift = 0,
1204	.parent_map = gcc_pxo_pll8_map,
1205	},
1206	.freq_tbl = clk_tbl_gsbi_qup,
1207	.clkr = {
1208	.enable_reg = 0x2aec,
1209	.enable_mask = BIT(11),
1210	.hw.init = &(struct clk_init_data){
1211	.name = "gsbi10_qup_src",
1212	.parent_data = gcc_pxo_pll8,
1213	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1214	.ops = &clk_rcg_ops,
1215	.flags = CLK_SET_PARENT_GATE,
1216	},
1217	},
1218	};
1219
1220	static struct clk_branch gsbi10_qup_clk = {
1221	.halt_reg = 0x2fd0,
1222	.halt_bit = 0,
1223	.clkr = {
1224	.enable_reg = 0x2aec,
1225	.enable_mask = BIT(9),
1226	.hw.init = &(struct clk_init_data){
1227	.name = "gsbi10_qup_clk",
1228	.parent_hws = (const struct clk_hw*[]){
1229	&gsbi10_qup_src.clkr.hw
1230	},
1231	.num_parents = 1,
1232	.ops = &clk_branch_ops,
1233	.flags = CLK_SET_RATE_PARENT,
1234	},
1235	},
1236	};
1237
1238	static struct clk_rcg gsbi11_qup_src = {
1239	.ns_reg = 0x2b0c,
1240	.md_reg = 0x2b08,
1241	.mn = {
1242	.mnctr_en_bit = 8,
1243	.mnctr_reset_bit = 7,
1244	.mnctr_mode_shift = 5,
1245	.n_val_shift = 16,
1246	.m_val_shift = 16,
1247	.width = 8,
1248	},
1249	.p = {
1250	.pre_div_shift = 3,
1251	.pre_div_width = 2,
1252	},
1253	.s = {
1254	.src_sel_shift = 0,
1255	.parent_map = gcc_pxo_pll8_map,
1256	},
1257	.freq_tbl = clk_tbl_gsbi_qup,
1258	.clkr = {
1259	.enable_reg = 0x2b0c,
1260	.enable_mask = BIT(11),
1261	.hw.init = &(struct clk_init_data){
1262	.name = "gsbi11_qup_src",
1263	.parent_data = gcc_pxo_pll8,
1264	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1265	.ops = &clk_rcg_ops,
1266	.flags = CLK_SET_PARENT_GATE,
1267	},
1268	},
1269	};
1270
1271	static struct clk_branch gsbi11_qup_clk = {
1272	.halt_reg = 0x2fd4,
1273	.halt_bit = 15,
1274	.clkr = {
1275	.enable_reg = 0x2b0c,
1276	.enable_mask = BIT(9),
1277	.hw.init = &(struct clk_init_data){
1278	.name = "gsbi11_qup_clk",
1279	.parent_hws = (const struct clk_hw*[]){
1280	&gsbi11_qup_src.clkr.hw
1281	},
1282	.num_parents = 1,
1283	.ops = &clk_branch_ops,
1284	.flags = CLK_SET_RATE_PARENT,
1285	},
1286	},
1287	};
1288
1289	static struct clk_rcg gsbi12_qup_src = {
1290	.ns_reg = 0x2b2c,
1291	.md_reg = 0x2b28,
1292	.mn = {
1293	.mnctr_en_bit = 8,
1294	.mnctr_reset_bit = 7,
1295	.mnctr_mode_shift = 5,
1296	.n_val_shift = 16,
1297	.m_val_shift = 16,
1298	.width = 8,
1299	},
1300	.p = {
1301	.pre_div_shift = 3,
1302	.pre_div_width = 2,
1303	},
1304	.s = {
1305	.src_sel_shift = 0,
1306	.parent_map = gcc_pxo_pll8_map,
1307	},
1308	.freq_tbl = clk_tbl_gsbi_qup,
1309	.clkr = {
1310	.enable_reg = 0x2b2c,
1311	.enable_mask = BIT(11),
1312	.hw.init = &(struct clk_init_data){
1313	.name = "gsbi12_qup_src",
1314	.parent_data = gcc_pxo_pll8,
1315	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1316	.ops = &clk_rcg_ops,
1317	.flags = CLK_SET_PARENT_GATE,
1318	},
1319	},
1320	};
1321
1322	static struct clk_branch gsbi12_qup_clk = {
1323	.halt_reg = 0x2fd4,
1324	.halt_bit = 11,
1325	.clkr = {
1326	.enable_reg = 0x2b2c,
1327	.enable_mask = BIT(9),
1328	.hw.init = &(struct clk_init_data){
1329	.name = "gsbi12_qup_clk",
1330	.parent_hws = (const struct clk_hw*[]){
1331	&gsbi12_qup_src.clkr.hw
1332	},
1333	.num_parents = 1,
1334	.ops = &clk_branch_ops,
1335	.flags = CLK_SET_RATE_PARENT,
1336	},
1337	},
1338	};
1339
1340	static const struct freq_tbl clk_tbl_gp[] = {
1341	{ 9600000, P_CXO, 2, 0, 0 },
1342	{ 13500000, P_PXO, 2, 0, 0 },
1343	{ 19200000, P_CXO, 1, 0, 0 },
1344	{ 27000000, P_PXO, 1, 0, 0 },
1345	{ 64000000, P_PLL8, 2, 1, 3 },
1346	{ 76800000, P_PLL8, 1, 1, 5 },
1347	{ 96000000, P_PLL8, 4, 0, 0 },
1348	{ 128000000, P_PLL8, 3, 0, 0 },
1349	{ 192000000, P_PLL8, 2, 0, 0 },
1350	{ }
1351	};
1352
1353	static struct clk_rcg gp0_src = {
1354	.ns_reg = 0x2d24,
1355	.md_reg = 0x2d00,
1356	.mn = {
1357	.mnctr_en_bit = 8,
1358	.mnctr_reset_bit = 7,
1359	.mnctr_mode_shift = 5,
1360	.n_val_shift = 16,
1361	.m_val_shift = 16,
1362	.width = 8,
1363	},
1364	.p = {
1365	.pre_div_shift = 3,
1366	.pre_div_width = 2,
1367	},
1368	.s = {
1369	.src_sel_shift = 0,
1370	.parent_map = gcc_pxo_pll8_cxo_map,
1371	},
1372	.freq_tbl = clk_tbl_gp,
1373	.clkr = {
1374	.enable_reg = 0x2d24,
1375	.enable_mask = BIT(11),
1376	.hw.init = &(struct clk_init_data){
1377	.name = "gp0_src",
1378	.parent_data = gcc_pxo_pll8_cxo,
1379	.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1380	.ops = &clk_rcg_ops,
1381	.flags = CLK_SET_PARENT_GATE,
1382	},
1383	}
1384	};
1385
1386	static struct clk_branch gp0_clk = {
1387	.halt_reg = 0x2fd8,
1388	.halt_bit = 7,
1389	.clkr = {
1390	.enable_reg = 0x2d24,
1391	.enable_mask = BIT(9),
1392	.hw.init = &(struct clk_init_data){
1393	.name = "gp0_clk",
1394	.parent_hws = (const struct clk_hw*[]){
1395	&gp0_src.clkr.hw
1396	},
1397	.num_parents = 1,
1398	.ops = &clk_branch_ops,
1399	.flags = CLK_SET_RATE_PARENT,
1400	},
1401	},
1402	};
1403
1404	static struct clk_rcg gp1_src = {
1405	.ns_reg = 0x2d44,
1406	.md_reg = 0x2d40,
1407	.mn = {
1408	.mnctr_en_bit = 8,
1409	.mnctr_reset_bit = 7,
1410	.mnctr_mode_shift = 5,
1411	.n_val_shift = 16,
1412	.m_val_shift = 16,
1413	.width = 8,
1414	},
1415	.p = {
1416	.pre_div_shift = 3,
1417	.pre_div_width = 2,
1418	},
1419	.s = {
1420	.src_sel_shift = 0,
1421	.parent_map = gcc_pxo_pll8_cxo_map,
1422	},
1423	.freq_tbl = clk_tbl_gp,
1424	.clkr = {
1425	.enable_reg = 0x2d44,
1426	.enable_mask = BIT(11),
1427	.hw.init = &(struct clk_init_data){
1428	.name = "gp1_src",
1429	.parent_data = gcc_pxo_pll8_cxo,
1430	.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1431	.ops = &clk_rcg_ops,
1432	.flags = CLK_SET_RATE_GATE,
1433	},
1434	}
1435	};
1436
1437	static struct clk_branch gp1_clk = {
1438	.halt_reg = 0x2fd8,
1439	.halt_bit = 6,
1440	.clkr = {
1441	.enable_reg = 0x2d44,
1442	.enable_mask = BIT(9),
1443	.hw.init = &(struct clk_init_data){
1444	.name = "gp1_clk",
1445	.parent_hws = (const struct clk_hw*[]){
1446	&gp1_src.clkr.hw
1447	},
1448	.num_parents = 1,
1449	.ops = &clk_branch_ops,
1450	.flags = CLK_SET_RATE_PARENT,
1451	},
1452	},
1453	};
1454
1455	static struct clk_rcg gp2_src = {
1456	.ns_reg = 0x2d64,
1457	.md_reg = 0x2d60,
1458	.mn = {
1459	.mnctr_en_bit = 8,
1460	.mnctr_reset_bit = 7,
1461	.mnctr_mode_shift = 5,
1462	.n_val_shift = 16,
1463	.m_val_shift = 16,
1464	.width = 8,
1465	},
1466	.p = {
1467	.pre_div_shift = 3,
1468	.pre_div_width = 2,
1469	},
1470	.s = {
1471	.src_sel_shift = 0,
1472	.parent_map = gcc_pxo_pll8_cxo_map,
1473	},
1474	.freq_tbl = clk_tbl_gp,
1475	.clkr = {
1476	.enable_reg = 0x2d64,
1477	.enable_mask = BIT(11),
1478	.hw.init = &(struct clk_init_data){
1479	.name = "gp2_src",
1480	.parent_data = gcc_pxo_pll8_cxo,
1481	.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1482	.ops = &clk_rcg_ops,
1483	.flags = CLK_SET_RATE_GATE,
1484	},
1485	}
1486	};
1487
1488	static struct clk_branch gp2_clk = {
1489	.halt_reg = 0x2fd8,
1490	.halt_bit = 5,
1491	.clkr = {
1492	.enable_reg = 0x2d64,
1493	.enable_mask = BIT(9),
1494	.hw.init = &(struct clk_init_data){
1495	.name = "gp2_clk",
1496	.parent_hws = (const struct clk_hw*[]){
1497	&gp2_src.clkr.hw
1498	},
1499	.num_parents = 1,
1500	.ops = &clk_branch_ops,
1501	.flags = CLK_SET_RATE_PARENT,
1502	},
1503	},
1504	};
1505
1506	static struct clk_branch pmem_clk = {
1507	.hwcg_reg = 0x25a0,
1508	.hwcg_bit = 6,
1509	.halt_reg = 0x2fc8,
1510	.halt_bit = 20,
1511	.clkr = {
1512	.enable_reg = 0x25a0,
1513	.enable_mask = BIT(4),
1514	.hw.init = &(struct clk_init_data){
1515	.name = "pmem_clk",
1516	.ops = &clk_branch_ops,
1517	},
1518	},
1519	};
1520
1521	static struct clk_rcg prng_src = {
1522	.ns_reg = 0x2e80,
1523	.p = {
1524	.pre_div_shift = 3,
1525	.pre_div_width = 4,
1526	},
1527	.s = {
1528	.src_sel_shift = 0,
1529	.parent_map = gcc_pxo_pll8_map,
1530	},
1531	.clkr.hw = {
1532	.init = &(struct clk_init_data){
1533	.name = "prng_src",
1534	.parent_data = gcc_pxo_pll8,
1535	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1536	.ops = &clk_rcg_ops,
1537	},
1538	},
1539	};
1540
1541	static struct clk_branch prng_clk = {
1542	.halt_reg = 0x2fd8,
1543	.halt_check = BRANCH_HALT_VOTED,
1544	.halt_bit = 10,
1545	.clkr = {
1546	.enable_reg = 0x3080,
1547	.enable_mask = BIT(10),
1548	.hw.init = &(struct clk_init_data){
1549	.name = "prng_clk",
1550	.parent_hws = (const struct clk_hw*[]){
1551	&prng_src.clkr.hw
1552	},
1553	.num_parents = 1,
1554	.ops = &clk_branch_ops,
1555	},
1556	},
1557	};
1558
1559	static const struct freq_tbl clk_tbl_sdc[] = {
1560	{ 144000, P_PXO, 3, 2, 125 },
1561	{ 400000, P_PLL8, 4, 1, 240 },
1562	{ 16000000, P_PLL8, 4, 1, 6 },
1563	{ 17070000, P_PLL8, 1, 2, 45 },
1564	{ 20210000, P_PLL8, 1, 1, 19 },
1565	{ 24000000, P_PLL8, 4, 1, 4 },
1566	{ 48000000, P_PLL8, 4, 1, 2 },
1567	{ }
1568	};
1569
1570	static struct clk_rcg sdc1_src = {
1571	.ns_reg = 0x282c,
1572	.md_reg = 0x2828,
1573	.mn = {
1574	.mnctr_en_bit = 8,
1575	.mnctr_reset_bit = 7,
1576	.mnctr_mode_shift = 5,
1577	.n_val_shift = 16,
1578	.m_val_shift = 16,
1579	.width = 8,
1580	},
1581	.p = {
1582	.pre_div_shift = 3,
1583	.pre_div_width = 2,
1584	},
1585	.s = {
1586	.src_sel_shift = 0,
1587	.parent_map = gcc_pxo_pll8_map,
1588	},
1589	.freq_tbl = clk_tbl_sdc,
1590	.clkr = {
1591	.enable_reg = 0x282c,
1592	.enable_mask = BIT(11),
1593	.hw.init = &(struct clk_init_data){
1594	.name = "sdc1_src",
1595	.parent_data = gcc_pxo_pll8,
1596	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1597	.ops = &clk_rcg_ops,
1598	},
1599	}
1600	};
1601
1602	static struct clk_branch sdc1_clk = {
1603	.halt_reg = 0x2fc8,
1604	.halt_bit = 6,
1605	.clkr = {
1606	.enable_reg = 0x282c,
1607	.enable_mask = BIT(9),
1608	.hw.init = &(struct clk_init_data){
1609	.name = "sdc1_clk",
1610	.parent_hws = (const struct clk_hw*[]){
1611	&sdc1_src.clkr.hw
1612	},
1613	.num_parents = 1,
1614	.ops = &clk_branch_ops,
1615	.flags = CLK_SET_RATE_PARENT,
1616	},
1617	},
1618	};
1619
1620	static struct clk_rcg sdc2_src = {
1621	.ns_reg = 0x284c,
1622	.md_reg = 0x2848,
1623	.mn = {
1624	.mnctr_en_bit = 8,
1625	.mnctr_reset_bit = 7,
1626	.mnctr_mode_shift = 5,
1627	.n_val_shift = 16,
1628	.m_val_shift = 16,
1629	.width = 8,
1630	},
1631	.p = {
1632	.pre_div_shift = 3,
1633	.pre_div_width = 2,
1634	},
1635	.s = {
1636	.src_sel_shift = 0,
1637	.parent_map = gcc_pxo_pll8_map,
1638	},
1639	.freq_tbl = clk_tbl_sdc,
1640	.clkr = {
1641	.enable_reg = 0x284c,
1642	.enable_mask = BIT(11),
1643	.hw.init = &(struct clk_init_data){
1644	.name = "sdc2_src",
1645	.parent_data = gcc_pxo_pll8,
1646	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1647	.ops = &clk_rcg_ops,
1648	},
1649	}
1650	};
1651
1652	static struct clk_branch sdc2_clk = {
1653	.halt_reg = 0x2fc8,
1654	.halt_bit = 5,
1655	.clkr = {
1656	.enable_reg = 0x284c,
1657	.enable_mask = BIT(9),
1658	.hw.init = &(struct clk_init_data){
1659	.name = "sdc2_clk",
1660	.parent_hws = (const struct clk_hw*[]){
1661	&sdc2_src.clkr.hw
1662	},
1663	.num_parents = 1,
1664	.ops = &clk_branch_ops,
1665	.flags = CLK_SET_RATE_PARENT,
1666	},
1667	},
1668	};
1669
1670	static struct clk_rcg sdc3_src = {
1671	.ns_reg = 0x286c,
1672	.md_reg = 0x2868,
1673	.mn = {
1674	.mnctr_en_bit = 8,
1675	.mnctr_reset_bit = 7,
1676	.mnctr_mode_shift = 5,
1677	.n_val_shift = 16,
1678	.m_val_shift = 16,
1679	.width = 8,
1680	},
1681	.p = {
1682	.pre_div_shift = 3,
1683	.pre_div_width = 2,
1684	},
1685	.s = {
1686	.src_sel_shift = 0,
1687	.parent_map = gcc_pxo_pll8_map,
1688	},
1689	.freq_tbl = clk_tbl_sdc,
1690	.clkr = {
1691	.enable_reg = 0x286c,
1692	.enable_mask = BIT(11),
1693	.hw.init = &(struct clk_init_data){
1694	.name = "sdc3_src",
1695	.parent_data = gcc_pxo_pll8,
1696	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1697	.ops = &clk_rcg_ops,
1698	},
1699	}
1700	};
1701
1702	static struct clk_branch sdc3_clk = {
1703	.halt_reg = 0x2fc8,
1704	.halt_bit = 4,
1705	.clkr = {
1706	.enable_reg = 0x286c,
1707	.enable_mask = BIT(9),
1708	.hw.init = &(struct clk_init_data){
1709	.name = "sdc3_clk",
1710	.parent_hws = (const struct clk_hw*[]){
1711	&sdc3_src.clkr.hw
1712	},
1713	.num_parents = 1,
1714	.ops = &clk_branch_ops,
1715	.flags = CLK_SET_RATE_PARENT,
1716	},
1717	},
1718	};
1719
1720	static struct clk_rcg sdc4_src = {
1721	.ns_reg = 0x288c,
1722	.md_reg = 0x2888,
1723	.mn = {
1724	.mnctr_en_bit = 8,
1725	.mnctr_reset_bit = 7,
1726	.mnctr_mode_shift = 5,
1727	.n_val_shift = 16,
1728	.m_val_shift = 16,
1729	.width = 8,
1730	},
1731	.p = {
1732	.pre_div_shift = 3,
1733	.pre_div_width = 2,
1734	},
1735	.s = {
1736	.src_sel_shift = 0,
1737	.parent_map = gcc_pxo_pll8_map,
1738	},
1739	.freq_tbl = clk_tbl_sdc,
1740	.clkr = {
1741	.enable_reg = 0x288c,
1742	.enable_mask = BIT(11),
1743	.hw.init = &(struct clk_init_data){
1744	.name = "sdc4_src",
1745	.parent_data = gcc_pxo_pll8,
1746	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1747	.ops = &clk_rcg_ops,
1748	},
1749	}
1750	};
1751
1752	static struct clk_branch sdc4_clk = {
1753	.halt_reg = 0x2fc8,
1754	.halt_bit = 3,
1755	.clkr = {
1756	.enable_reg = 0x288c,
1757	.enable_mask = BIT(9),
1758	.hw.init = &(struct clk_init_data){
1759	.name = "sdc4_clk",
1760	.parent_hws = (const struct clk_hw*[]){
1761	&sdc4_src.clkr.hw
1762	},
1763	.num_parents = 1,
1764	.ops = &clk_branch_ops,
1765	.flags = CLK_SET_RATE_PARENT,
1766	},
1767	},
1768	};
1769
1770	static struct clk_rcg sdc5_src = {
1771	.ns_reg = 0x28ac,
1772	.md_reg = 0x28a8,
1773	.mn = {
1774	.mnctr_en_bit = 8,
1775	.mnctr_reset_bit = 7,
1776	.mnctr_mode_shift = 5,
1777	.n_val_shift = 16,
1778	.m_val_shift = 16,
1779	.width = 8,
1780	},
1781	.p = {
1782	.pre_div_shift = 3,
1783	.pre_div_width = 2,
1784	},
1785	.s = {
1786	.src_sel_shift = 0,
1787	.parent_map = gcc_pxo_pll8_map,
1788	},
1789	.freq_tbl = clk_tbl_sdc,
1790	.clkr = {
1791	.enable_reg = 0x28ac,
1792	.enable_mask = BIT(11),
1793	.hw.init = &(struct clk_init_data){
1794	.name = "sdc5_src",
1795	.parent_data = gcc_pxo_pll8,
1796	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1797	.ops = &clk_rcg_ops,
1798	},
1799	}
1800	};
1801
1802	static struct clk_branch sdc5_clk = {
1803	.halt_reg = 0x2fc8,
1804	.halt_bit = 2,
1805	.clkr = {
1806	.enable_reg = 0x28ac,
1807	.enable_mask = BIT(9),
1808	.hw.init = &(struct clk_init_data){
1809	.name = "sdc5_clk",
1810	.parent_hws = (const struct clk_hw*[]){
1811	&sdc5_src.clkr.hw
1812	},
1813	.num_parents = 1,
1814	.ops = &clk_branch_ops,
1815	.flags = CLK_SET_RATE_PARENT,
1816	},
1817	},
1818	};
1819
1820	static const struct freq_tbl clk_tbl_tsif_ref[] = {
1821	{ 105000, P_PXO, 1, 1, 256 },
1822	{ }
1823	};
1824
1825	static struct clk_rcg tsif_ref_src = {
1826	.ns_reg = 0x2710,
1827	.md_reg = 0x270c,
1828	.mn = {
1829	.mnctr_en_bit = 8,
1830	.mnctr_reset_bit = 7,
1831	.mnctr_mode_shift = 5,
1832	.n_val_shift = 16,
1833	.m_val_shift = 16,
1834	.width = 16,
1835	},
1836	.p = {
1837	.pre_div_shift = 3,
1838	.pre_div_width = 2,
1839	},
1840	.s = {
1841	.src_sel_shift = 0,
1842	.parent_map = gcc_pxo_pll8_map,
1843	},
1844	.freq_tbl = clk_tbl_tsif_ref,
1845	.clkr = {
1846	.enable_reg = 0x2710,
1847	.enable_mask = BIT(11),
1848	.hw.init = &(struct clk_init_data){
1849	.name = "tsif_ref_src",
1850	.parent_data = gcc_pxo_pll8,
1851	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1852	.ops = &clk_rcg_ops,
1853	.flags = CLK_SET_RATE_GATE,
1854	},
1855	}
1856	};
1857
1858	static struct clk_branch tsif_ref_clk = {
1859	.halt_reg = 0x2fd4,
1860	.halt_bit = 5,
1861	.clkr = {
1862	.enable_reg = 0x2710,
1863	.enable_mask = BIT(9),
1864	.hw.init = &(struct clk_init_data){
1865	.name = "tsif_ref_clk",
1866	.parent_hws = (const struct clk_hw*[]){
1867	&tsif_ref_src.clkr.hw
1868	},
1869	.num_parents = 1,
1870	.ops = &clk_branch_ops,
1871	.flags = CLK_SET_RATE_PARENT,
1872	},
1873	},
1874	};
1875
1876	static const struct freq_tbl clk_tbl_usb[] = {
1877	{ 60000000, P_PLL8, 1, 5, 32 },
1878	{ }
1879	};
1880
1881	static struct clk_rcg usb_hs1_xcvr_src = {
1882	.ns_reg = 0x290c,
1883	.md_reg = 0x2908,
1884	.mn = {
1885	.mnctr_en_bit = 8,
1886	.mnctr_reset_bit = 7,
1887	.mnctr_mode_shift = 5,
1888	.n_val_shift = 16,
1889	.m_val_shift = 16,
1890	.width = 8,
1891	},
1892	.p = {
1893	.pre_div_shift = 3,
1894	.pre_div_width = 2,
1895	},
1896	.s = {
1897	.src_sel_shift = 0,
1898	.parent_map = gcc_pxo_pll8_map,
1899	},
1900	.freq_tbl = clk_tbl_usb,
1901	.clkr = {
1902	.enable_reg = 0x290c,
1903	.enable_mask = BIT(11),
1904	.hw.init = &(struct clk_init_data){
1905	.name = "usb_hs1_xcvr_src",
1906	.parent_data = gcc_pxo_pll8,
1907	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1908	.ops = &clk_rcg_ops,
1909	.flags = CLK_SET_RATE_GATE,
1910	},
1911	}
1912	};
1913
1914	static struct clk_branch usb_hs1_xcvr_clk = {
1915	.halt_reg = 0x2fc8,
1916	.halt_bit = 0,
1917	.clkr = {
1918	.enable_reg = 0x290c,
1919	.enable_mask = BIT(9),
1920	.hw.init = &(struct clk_init_data){
1921	.name = "usb_hs1_xcvr_clk",
1922	.parent_hws = (const struct clk_hw*[]){
1923	&usb_hs1_xcvr_src.clkr.hw
1924	},
1925	.num_parents = 1,
1926	.ops = &clk_branch_ops,
1927	.flags = CLK_SET_RATE_PARENT,
1928	},
1929	},
1930	};
1931
1932	static struct clk_rcg usb_fs1_xcvr_fs_src = {
1933	.ns_reg = 0x2968,
1934	.md_reg = 0x2964,
1935	.mn = {
1936	.mnctr_en_bit = 8,
1937	.mnctr_reset_bit = 7,
1938	.mnctr_mode_shift = 5,
1939	.n_val_shift = 16,
1940	.m_val_shift = 16,
1941	.width = 8,
1942	},
1943	.p = {
1944	.pre_div_shift = 3,
1945	.pre_div_width = 2,
1946	},
1947	.s = {
1948	.src_sel_shift = 0,
1949	.parent_map = gcc_pxo_pll8_map,
1950	},
1951	.freq_tbl = clk_tbl_usb,
1952	.clkr = {
1953	.enable_reg = 0x2968,
1954	.enable_mask = BIT(11),
1955	.hw.init = &(struct clk_init_data){
1956	.name = "usb_fs1_xcvr_fs_src",
1957	.parent_data = gcc_pxo_pll8,
1958	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1959	.ops = &clk_rcg_ops,
1960	.flags = CLK_SET_RATE_GATE,
1961	},
1962	}
1963	};
1964
1965	static struct clk_branch usb_fs1_xcvr_fs_clk = {
1966	.halt_reg = 0x2fcc,
1967	.halt_bit = 15,
1968	.clkr = {
1969	.enable_reg = 0x2968,
1970	.enable_mask = BIT(9),
1971	.hw.init = &(struct clk_init_data){
1972	.name = "usb_fs1_xcvr_fs_clk",
1973	.parent_hws = (const struct clk_hw*[]){
1974	&usb_fs1_xcvr_fs_src.clkr.hw,
1975	},
1976	.num_parents = 1,
1977	.ops = &clk_branch_ops,
1978	.flags = CLK_SET_RATE_PARENT,
1979	},
1980	},
1981	};
1982
1983	static struct clk_branch usb_fs1_system_clk = {
1984	.halt_reg = 0x2fcc,
1985	.halt_bit = 16,
1986	.clkr = {
1987	.enable_reg = 0x296c,
1988	.enable_mask = BIT(4),
1989	.hw.init = &(struct clk_init_data){
1990	.parent_hws = (const struct clk_hw*[]){
1991	&usb_fs1_xcvr_fs_src.clkr.hw,
1992	},
1993	.num_parents = 1,
1994	.name = "usb_fs1_system_clk",
1995	.ops = &clk_branch_ops,
1996	.flags = CLK_SET_RATE_PARENT,
1997	},
1998	},
1999	};
2000
2001	static struct clk_rcg usb_fs2_xcvr_fs_src = {
2002	.ns_reg = 0x2988,
2003	.md_reg = 0x2984,
2004	.mn = {
2005	.mnctr_en_bit = 8,
2006	.mnctr_reset_bit = 7,
2007	.mnctr_mode_shift = 5,
2008	.n_val_shift = 16,
2009	.m_val_shift = 16,
2010	.width = 8,
2011	},
2012	.p = {
2013	.pre_div_shift = 3,
2014	.pre_div_width = 2,
2015	},
2016	.s = {
2017	.src_sel_shift = 0,
2018	.parent_map = gcc_pxo_pll8_map,
2019	},
2020	.freq_tbl = clk_tbl_usb,
2021	.clkr = {
2022	.enable_reg = 0x2988,
2023	.enable_mask = BIT(11),
2024	.hw.init = &(struct clk_init_data){
2025	.name = "usb_fs2_xcvr_fs_src",
2026	.parent_data = gcc_pxo_pll8,
2027	.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2028	.ops = &clk_rcg_ops,
2029	.flags = CLK_SET_RATE_GATE,
2030	},
2031	}
2032	};
2033
2034	static struct clk_branch usb_fs2_xcvr_fs_clk = {
2035	.halt_reg = 0x2fcc,
2036	.halt_bit = 12,
2037	.clkr = {
2038	.enable_reg = 0x2988,
2039	.enable_mask = BIT(9),
2040	.hw.init = &(struct clk_init_data){
2041	.name = "usb_fs2_xcvr_fs_clk",
2042	.parent_hws = (const struct clk_hw*[]){
2043	&usb_fs2_xcvr_fs_src.clkr.hw,
2044	},
2045	.num_parents = 1,
2046	.ops = &clk_branch_ops,
2047	.flags = CLK_SET_RATE_PARENT,
2048	},
2049	},
2050	};
2051
2052	static struct clk_branch usb_fs2_system_clk = {
2053	.halt_reg = 0x2fcc,
2054	.halt_bit = 13,
2055	.clkr = {
2056	.enable_reg = 0x298c,
2057	.enable_mask = BIT(4),
2058	.hw.init = &(struct clk_init_data){
2059	.name = "usb_fs2_system_clk",
2060	.parent_hws = (const struct clk_hw*[]){
2061	&usb_fs2_xcvr_fs_src.clkr.hw,
2062	},
2063	.num_parents = 1,
2064	.ops = &clk_branch_ops,
2065	.flags = CLK_SET_RATE_PARENT,
2066	},
2067	},
2068	};
2069
2070	static struct clk_branch gsbi1_h_clk = {
2071	.halt_reg = 0x2fcc,
2072	.halt_bit = 11,
2073	.clkr = {
2074	.enable_reg = 0x29c0,
2075	.enable_mask = BIT(4),
2076	.hw.init = &(struct clk_init_data){
2077	.name = "gsbi1_h_clk",
2078	.ops = &clk_branch_ops,
2079	},
2080	},
2081	};
2082
2083	static struct clk_branch gsbi2_h_clk = {
2084	.halt_reg = 0x2fcc,
2085	.halt_bit = 7,
2086	.clkr = {
2087	.enable_reg = 0x29e0,
2088	.enable_mask = BIT(4),
2089	.hw.init = &(struct clk_init_data){
2090	.name = "gsbi2_h_clk",
2091	.ops = &clk_branch_ops,
2092	},
2093	},
2094	};
2095
2096	static struct clk_branch gsbi3_h_clk = {
2097	.halt_reg = 0x2fcc,
2098	.halt_bit = 3,
2099	.clkr = {
2100	.enable_reg = 0x2a00,
2101	.enable_mask = BIT(4),
2102	.hw.init = &(struct clk_init_data){
2103	.name = "gsbi3_h_clk",
2104	.ops = &clk_branch_ops,
2105	},
2106	},
2107	};
2108
2109	static struct clk_branch gsbi4_h_clk = {
2110	.halt_reg = 0x2fd0,
2111	.halt_bit = 27,
2112	.clkr = {
2113	.enable_reg = 0x2a20,
2114	.enable_mask = BIT(4),
2115	.hw.init = &(struct clk_init_data){
2116	.name = "gsbi4_h_clk",
2117	.ops = &clk_branch_ops,
2118	},
2119	},
2120	};
2121
2122	static struct clk_branch gsbi5_h_clk = {
2123	.halt_reg = 0x2fd0,
2124	.halt_bit = 23,
2125	.clkr = {
2126	.enable_reg = 0x2a40,
2127	.enable_mask = BIT(4),
2128	.hw.init = &(struct clk_init_data){
2129	.name = "gsbi5_h_clk",
2130	.ops = &clk_branch_ops,
2131	},
2132	},
2133	};
2134
2135	static struct clk_branch gsbi6_h_clk = {
2136	.halt_reg = 0x2fd0,
2137	.halt_bit = 19,
2138	.clkr = {
2139	.enable_reg = 0x2a60,
2140	.enable_mask = BIT(4),
2141	.hw.init = &(struct clk_init_data){
2142	.name = "gsbi6_h_clk",
2143	.ops = &clk_branch_ops,
2144	},
2145	},
2146	};
2147
2148	static struct clk_branch gsbi7_h_clk = {
2149	.halt_reg = 0x2fd0,
2150	.halt_bit = 15,
2151	.clkr = {
2152	.enable_reg = 0x2a80,
2153	.enable_mask = BIT(4),
2154	.hw.init = &(struct clk_init_data){
2155	.name = "gsbi7_h_clk",
2156	.ops = &clk_branch_ops,
2157	},
2158	},
2159	};
2160
2161	static struct clk_branch gsbi8_h_clk = {
2162	.halt_reg = 0x2fd0,
2163	.halt_bit = 11,
2164	.clkr = {
2165	.enable_reg = 0x2aa0,
2166	.enable_mask = BIT(4),
2167	.hw.init = &(struct clk_init_data){
2168	.name = "gsbi8_h_clk",
2169	.ops = &clk_branch_ops,
2170	},
2171	},
2172	};
2173
2174	static struct clk_branch gsbi9_h_clk = {
2175	.halt_reg = 0x2fd0,
2176	.halt_bit = 7,
2177	.clkr = {
2178	.enable_reg = 0x2ac0,
2179	.enable_mask = BIT(4),
2180	.hw.init = &(struct clk_init_data){
2181	.name = "gsbi9_h_clk",
2182	.ops = &clk_branch_ops,
2183	},
2184	},
2185	};
2186
2187	static struct clk_branch gsbi10_h_clk = {
2188	.halt_reg = 0x2fd0,
2189	.halt_bit = 3,
2190	.clkr = {
2191	.enable_reg = 0x2ae0,
2192	.enable_mask = BIT(4),
2193	.hw.init = &(struct clk_init_data){
2194	.name = "gsbi10_h_clk",
2195	.ops = &clk_branch_ops,
2196	},
2197	},
2198	};
2199
2200	static struct clk_branch gsbi11_h_clk = {
2201	.halt_reg = 0x2fd4,
2202	.halt_bit = 18,
2203	.clkr = {
2204	.enable_reg = 0x2b00,
2205	.enable_mask = BIT(4),
2206	.hw.init = &(struct clk_init_data){
2207	.name = "gsbi11_h_clk",
2208	.ops = &clk_branch_ops,
2209	},
2210	},
2211	};
2212
2213	static struct clk_branch gsbi12_h_clk = {
2214	.halt_reg = 0x2fd4,
2215	.halt_bit = 14,
2216	.clkr = {
2217	.enable_reg = 0x2b20,
2218	.enable_mask = BIT(4),
2219	.hw.init = &(struct clk_init_data){
2220	.name = "gsbi12_h_clk",
2221	.ops = &clk_branch_ops,
2222	},
2223	},
2224	};
2225
2226	static struct clk_branch tsif_h_clk = {
2227	.halt_reg = 0x2fd4,
2228	.halt_bit = 7,
2229	.clkr = {
2230	.enable_reg = 0x2700,
2231	.enable_mask = BIT(4),
2232	.hw.init = &(struct clk_init_data){
2233	.name = "tsif_h_clk",
2234	.ops = &clk_branch_ops,
2235	},
2236	},
2237	};
2238
2239	static struct clk_branch usb_fs1_h_clk = {
2240	.halt_reg = 0x2fcc,
2241	.halt_bit = 17,
2242	.clkr = {
2243	.enable_reg = 0x2960,
2244	.enable_mask = BIT(4),
2245	.hw.init = &(struct clk_init_data){
2246	.name = "usb_fs1_h_clk",
2247	.ops = &clk_branch_ops,
2248	},
2249	},
2250	};
2251
2252	static struct clk_branch usb_fs2_h_clk = {
2253	.halt_reg = 0x2fcc,
2254	.halt_bit = 14,
2255	.clkr = {
2256	.enable_reg = 0x2980,
2257	.enable_mask = BIT(4),
2258	.hw.init = &(struct clk_init_data){
2259	.name = "usb_fs2_h_clk",
2260	.ops = &clk_branch_ops,
2261	},
2262	},
2263	};
2264
2265	static struct clk_branch usb_hs1_h_clk = {
2266	.halt_reg = 0x2fc8,
2267	.halt_bit = 1,
2268	.clkr = {
2269	.enable_reg = 0x2900,
2270	.enable_mask = BIT(4),
2271	.hw.init = &(struct clk_init_data){
2272	.name = "usb_hs1_h_clk",
2273	.ops = &clk_branch_ops,
2274	},
2275	},
2276	};
2277
2278	static struct clk_branch sdc1_h_clk = {
2279	.halt_reg = 0x2fc8,
2280	.halt_bit = 11,
2281	.clkr = {
2282	.enable_reg = 0x2820,
2283	.enable_mask = BIT(4),
2284	.hw.init = &(struct clk_init_data){
2285	.name = "sdc1_h_clk",
2286	.ops = &clk_branch_ops,
2287	},
2288	},
2289	};
2290
2291	static struct clk_branch sdc2_h_clk = {
2292	.halt_reg = 0x2fc8,
2293	.halt_bit = 10,
2294	.clkr = {
2295	.enable_reg = 0x2840,
2296	.enable_mask = BIT(4),
2297	.hw.init = &(struct clk_init_data){
2298	.name = "sdc2_h_clk",
2299	.ops = &clk_branch_ops,
2300	},
2301	},
2302	};
2303
2304	static struct clk_branch sdc3_h_clk = {
2305	.halt_reg = 0x2fc8,
2306	.halt_bit = 9,
2307	.clkr = {
2308	.enable_reg = 0x2860,
2309	.enable_mask = BIT(4),
2310	.hw.init = &(struct clk_init_data){
2311	.name = "sdc3_h_clk",
2312	.ops = &clk_branch_ops,
2313	},
2314	},
2315	};
2316
2317	static struct clk_branch sdc4_h_clk = {
2318	.halt_reg = 0x2fc8,
2319	.halt_bit = 8,
2320	.clkr = {
2321	.enable_reg = 0x2880,
2322	.enable_mask = BIT(4),
2323	.hw.init = &(struct clk_init_data){
2324	.name = "sdc4_h_clk",
2325	.ops = &clk_branch_ops,
2326	},
2327	},
2328	};
2329
2330	static struct clk_branch sdc5_h_clk = {
2331	.halt_reg = 0x2fc8,
2332	.halt_bit = 7,
2333	.clkr = {
2334	.enable_reg = 0x28a0,
2335	.enable_mask = BIT(4),
2336	.hw.init = &(struct clk_init_data){
2337	.name = "sdc5_h_clk",
2338	.ops = &clk_branch_ops,
2339	},
2340	},
2341	};
2342
2343	static struct clk_branch ebi2_2x_clk = {
2344	.halt_reg = 0x2fcc,
2345	.halt_bit = 18,
2346	.clkr = {
2347	.enable_reg = 0x2660,
2348	.enable_mask = BIT(4),
2349	.hw.init = &(struct clk_init_data){
2350	.name = "ebi2_2x_clk",
2351	.ops = &clk_branch_ops,
2352	},
2353	},
2354	};
2355
2356	static struct clk_branch ebi2_clk = {
2357	.halt_reg = 0x2fcc,
2358	.halt_bit = 19,
2359	.clkr = {
2360	.enable_reg = 0x2664,
2361	.enable_mask = BIT(4),
2362	.hw.init = &(struct clk_init_data){
2363	.name = "ebi2_clk",
2364	.ops = &clk_branch_ops,
2365	},
2366	},
2367	};
2368
2369	static struct clk_branch adm0_clk = {
2370	.halt_reg = 0x2fdc,
2371	.halt_check = BRANCH_HALT_VOTED,
2372	.halt_bit = 14,
2373	.clkr = {
2374	.enable_reg = 0x3080,
2375	.enable_mask = BIT(2),
2376	.hw.init = &(struct clk_init_data){
2377	.name = "adm0_clk",
2378	.ops = &clk_branch_ops,
2379	},
2380	},
2381	};
2382
2383	static struct clk_branch adm0_pbus_clk = {
2384	.halt_reg = 0x2fdc,
2385	.halt_check = BRANCH_HALT_VOTED,
2386	.halt_bit = 13,
2387	.clkr = {
2388	.enable_reg = 0x3080,
2389	.enable_mask = BIT(3),
2390	.hw.init = &(struct clk_init_data){
2391	.name = "adm0_pbus_clk",
2392	.ops = &clk_branch_ops,
2393	},
2394	},
2395	};
2396
2397	static struct clk_branch adm1_clk = {
2398	.halt_reg = 0x2fdc,
2399	.halt_bit = 12,
2400	.halt_check = BRANCH_HALT_VOTED,
2401	.clkr = {
2402	.enable_reg = 0x3080,
2403	.enable_mask = BIT(4),
2404	.hw.init = &(struct clk_init_data){
2405	.name = "adm1_clk",
2406	.ops = &clk_branch_ops,
2407	},
2408	},
2409	};
2410
2411	static struct clk_branch adm1_pbus_clk = {
2412	.halt_reg = 0x2fdc,
2413	.halt_bit = 11,
2414	.halt_check = BRANCH_HALT_VOTED,
2415	.clkr = {
2416	.enable_reg = 0x3080,
2417	.enable_mask = BIT(5),
2418	.hw.init = &(struct clk_init_data){
2419	.name = "adm1_pbus_clk",
2420	.ops = &clk_branch_ops,
2421	},
2422	},
2423	};
2424
2425	static struct clk_branch modem_ahb1_h_clk = {
2426	.halt_reg = 0x2fdc,
2427	.halt_bit = 8,
2428	.halt_check = BRANCH_HALT_VOTED,
2429	.clkr = {
2430	.enable_reg = 0x3080,
2431	.enable_mask = BIT(0),
2432	.hw.init = &(struct clk_init_data){
2433	.name = "modem_ahb1_h_clk",
2434	.ops = &clk_branch_ops,
2435	},
2436	},
2437	};
2438
2439	static struct clk_branch modem_ahb2_h_clk = {
2440	.halt_reg = 0x2fdc,
2441	.halt_bit = 7,
2442	.halt_check = BRANCH_HALT_VOTED,
2443	.clkr = {
2444	.enable_reg = 0x3080,
2445	.enable_mask = BIT(1),
2446	.hw.init = &(struct clk_init_data){
2447	.name = "modem_ahb2_h_clk",
2448	.ops = &clk_branch_ops,
2449	},
2450	},
2451	};
2452
2453	static struct clk_branch pmic_arb0_h_clk = {
2454	.halt_reg = 0x2fd8,
2455	.halt_check = BRANCH_HALT_VOTED,
2456	.halt_bit = 22,
2457	.clkr = {
2458	.enable_reg = 0x3080,
2459	.enable_mask = BIT(8),
2460	.hw.init = &(struct clk_init_data){
2461	.name = "pmic_arb0_h_clk",
2462	.ops = &clk_branch_ops,
2463	},
2464	},
2465	};
2466
2467	static struct clk_branch pmic_arb1_h_clk = {
2468	.halt_reg = 0x2fd8,
2469	.halt_check = BRANCH_HALT_VOTED,
2470	.halt_bit = 21,
2471	.clkr = {
2472	.enable_reg = 0x3080,
2473	.enable_mask = BIT(9),
2474	.hw.init = &(struct clk_init_data){
2475	.name = "pmic_arb1_h_clk",
2476	.ops = &clk_branch_ops,
2477	},
2478	},
2479	};
2480
2481	static struct clk_branch pmic_ssbi2_clk = {
2482	.halt_reg = 0x2fd8,
2483	.halt_check = BRANCH_HALT_VOTED,
2484	.halt_bit = 23,
2485	.clkr = {
2486	.enable_reg = 0x3080,
2487	.enable_mask = BIT(7),
2488	.hw.init = &(struct clk_init_data){
2489	.name = "pmic_ssbi2_clk",
2490	.ops = &clk_branch_ops,
2491	},
2492	},
2493	};
2494
2495	static struct clk_branch rpm_msg_ram_h_clk = {
2496	.hwcg_reg = 0x27e0,
2497	.hwcg_bit = 6,
2498	.halt_reg = 0x2fd8,
2499	.halt_check = BRANCH_HALT_VOTED,
2500	.halt_bit = 12,
2501	.clkr = {
2502	.enable_reg = 0x3080,
2503	.enable_mask = BIT(6),
2504	.hw.init = &(struct clk_init_data){
2505	.name = "rpm_msg_ram_h_clk",
2506	.ops = &clk_branch_ops,
2507	},
2508	},
2509	};
2510
2511	static struct clk_regmap *gcc_msm8660_clks[] = {
2512	[PLL8] = &pll8.clkr,
2513	[PLL8_VOTE] = &pll8_vote,
2514	[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2515	[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2516	[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2517	[GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2518	[GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2519	[GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2520	[GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2521	[GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2522	[GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2523	[GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2524	[GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2525	[GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2526	[GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2527	[GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2528	[GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2529	[GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2530	[GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2531	[GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2532	[GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2533	[GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2534	[GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2535	[GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2536	[GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2537	[GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2538	[GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2539	[GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2540	[GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2541	[GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2542	[GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2543	[GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2544	[GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2545	[GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2546	[GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2547	[GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2548	[GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2549	[GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2550	[GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2551	[GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2552	[GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2553	[GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2554	[GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2555	[GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2556	[GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2557	[GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2558	[GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2559	[GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2560	[GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2561	[GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2562	[GP0_SRC] = &gp0_src.clkr,
2563	[GP0_CLK] = &gp0_clk.clkr,
2564	[GP1_SRC] = &gp1_src.clkr,
2565	[GP1_CLK] = &gp1_clk.clkr,
2566	[GP2_SRC] = &gp2_src.clkr,
2567	[GP2_CLK] = &gp2_clk.clkr,
2568	[PMEM_CLK] = &pmem_clk.clkr,
2569	[PRNG_SRC] = &prng_src.clkr,
2570	[PRNG_CLK] = &prng_clk.clkr,
2571	[SDC1_SRC] = &sdc1_src.clkr,
2572	[SDC1_CLK] = &sdc1_clk.clkr,
2573	[SDC2_SRC] = &sdc2_src.clkr,
2574	[SDC2_CLK] = &sdc2_clk.clkr,
2575	[SDC3_SRC] = &sdc3_src.clkr,
2576	[SDC3_CLK] = &sdc3_clk.clkr,
2577	[SDC4_SRC] = &sdc4_src.clkr,
2578	[SDC4_CLK] = &sdc4_clk.clkr,
2579	[SDC5_SRC] = &sdc5_src.clkr,
2580	[SDC5_CLK] = &sdc5_clk.clkr,
2581	[TSIF_REF_SRC] = &tsif_ref_src.clkr,
2582	[TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2583	[USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2584	[USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2585	[USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2586	[USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2587	[USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2588	[USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2589	[USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2590	[USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2591	[GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2592	[GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2593	[GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2594	[GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2595	[GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2596	[GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2597	[GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2598	[GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2599	[GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2600	[GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2601	[GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2602	[GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2603	[TSIF_H_CLK] = &tsif_h_clk.clkr,
2604	[USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2605	[USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2606	[USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2607	[SDC1_H_CLK] = &sdc1_h_clk.clkr,
2608	[SDC2_H_CLK] = &sdc2_h_clk.clkr,
2609	[SDC3_H_CLK] = &sdc3_h_clk.clkr,
2610	[SDC4_H_CLK] = &sdc4_h_clk.clkr,
2611	[SDC5_H_CLK] = &sdc5_h_clk.clkr,
2612	[EBI2_2X_CLK] = &ebi2_2x_clk.clkr,
2613	[EBI2_CLK] = &ebi2_clk.clkr,
2614	[ADM0_CLK] = &adm0_clk.clkr,
2615	[ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2616	[ADM1_CLK] = &adm1_clk.clkr,
2617	[ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr,
2618	[MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr,
2619	[MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr,
2620	[PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2621	[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2622	[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2623	[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2624	};
2625
2626	static const struct qcom_reset_map gcc_msm8660_resets[] = {
2627	[AFAB_CORE_RESET] = { 0x2080, 7 },
2628	[SCSS_SYS_RESET] = { 0x20b4, 1 },
2629	[SCSS_SYS_POR_RESET] = { 0x20b4 },
2630	[AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2631	[AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2632	[AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2633	[AFAB_EBI1_S_RESET] = { 0x20c0, 7 },
2634	[SFAB_CORE_RESET] = { 0x2120, 7 },
2635	[SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2636	[SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2637	[SFAB_ADM0_M2_RESET] = { 0x21e4, 7 },
2638	[ADM0_C2_RESET] = { 0x220c, 4 },
2639	[ADM0_C1_RESET] = { 0x220c, 3 },
2640	[ADM0_C0_RESET] = { 0x220c, 2 },
2641	[ADM0_PBUS_RESET] = { 0x220c, 1 },
2642	[ADM0_RESET] = { 0x220c },
2643	[SFAB_ADM1_M0_RESET] = { 0x2220, 7 },
2644	[SFAB_ADM1_M1_RESET] = { 0x2224, 7 },
2645	[SFAB_ADM1_M2_RESET] = { 0x2228, 7 },
2646	[MMFAB_ADM1_M3_RESET] = { 0x2240, 7 },
2647	[ADM1_C3_RESET] = { 0x226c, 5 },
2648	[ADM1_C2_RESET] = { 0x226c, 4 },
2649	[ADM1_C1_RESET] = { 0x226c, 3 },
2650	[ADM1_C0_RESET] = { 0x226c, 2 },
2651	[ADM1_PBUS_RESET] = { 0x226c, 1 },
2652	[ADM1_RESET] = { 0x226c },
2653	[IMEM0_RESET] = { 0x2280, 7 },
2654	[SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 },
2655	[SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2656	[AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2657	[AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2658	[DFAB_CORE_RESET] = { 0x24ac, 7 },
2659	[SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2660	[DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2661	[DFAB_SWAY0_RESET] = { 0x2540, 7 },
2662	[DFAB_SWAY1_RESET] = { 0x2544, 7 },
2663	[DFAB_ARB0_RESET] = { 0x2560, 7 },
2664	[DFAB_ARB1_RESET] = { 0x2564, 7 },
2665	[PPSS_PROC_RESET] = { 0x2594, 1 },
2666	[PPSS_RESET] = { 0x2594 },
2667	[PMEM_RESET] = { 0x25a0, 7 },
2668	[DMA_BAM_RESET] = { 0x25c0, 7 },
2669	[SIC_RESET] = { 0x25e0, 7 },
2670	[SPS_TIC_RESET] = { 0x2600, 7 },
2671	[CFBP0_RESET] = { 0x2650, 7 },
2672	[CFBP1_RESET] = { 0x2654, 7 },
2673	[CFBP2_RESET] = { 0x2658, 7 },
2674	[EBI2_RESET] = { 0x2664, 7 },
2675	[SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2676	[CFPB_MASTER_RESET] = { 0x26a0, 7 },
2677	[SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2678	[CFPB_SPLITTER_RESET] = { 0x26e0, 7 },
2679	[TSIF_RESET] = { 0x2700, 7 },
2680	[CE1_RESET] = { 0x2720, 7 },
2681	[CE2_RESET] = { 0x2740, 7 },
2682	[SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2683	[SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2684	[RPM_PROC_RESET] = { 0x27c0, 7 },
2685	[RPM_BUS_RESET] = { 0x27c4, 7 },
2686	[RPM_MSG_RAM_RESET] = { 0x27e0, 7 },
2687	[PMIC_ARB0_RESET] = { 0x2800, 7 },
2688	[PMIC_ARB1_RESET] = { 0x2804, 7 },
2689	[PMIC_SSBI2_RESET] = { 0x280c, 12 },
2690	[SDC1_RESET] = { 0x2830 },
2691	[SDC2_RESET] = { 0x2850 },
2692	[SDC3_RESET] = { 0x2870 },
2693	[SDC4_RESET] = { 0x2890 },
2694	[SDC5_RESET] = { 0x28b0 },
2695	[USB_HS1_RESET] = { 0x2910 },
2696	[USB_HS2_XCVR_RESET] = { 0x2934, 1 },
2697	[USB_HS2_RESET] = { 0x2934 },
2698	[USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2699	[USB_FS1_RESET] = { 0x2974 },
2700	[USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2701	[USB_FS2_RESET] = { 0x2994 },
2702	[GSBI1_RESET] = { 0x29dc },
2703	[GSBI2_RESET] = { 0x29fc },
2704	[GSBI3_RESET] = { 0x2a1c },
2705	[GSBI4_RESET] = { 0x2a3c },
2706	[GSBI5_RESET] = { 0x2a5c },
2707	[GSBI6_RESET] = { 0x2a7c },
2708	[GSBI7_RESET] = { 0x2a9c },
2709	[GSBI8_RESET] = { 0x2abc },
2710	[GSBI9_RESET] = { 0x2adc },
2711	[GSBI10_RESET] = { 0x2afc },
2712	[GSBI11_RESET] = { 0x2b1c },
2713	[GSBI12_RESET] = { 0x2b3c },
2714	[SPDM_RESET] = { 0x2b6c },
2715	[SEC_CTRL_RESET] = { 0x2b80, 7 },
2716	[TLMM_H_RESET] = { 0x2ba0, 7 },
2717	[TLMM_RESET] = { 0x2ba4, 7 },
2718	[MARRM_PWRON_RESET] = { 0x2bd4, 1 },
2719	[MARM_RESET] = { 0x2bd4 },
2720	[MAHB1_RESET] = { 0x2be4, 7 },
2721	[SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2722	[MAHB2_RESET] = { 0x2c20, 7 },
2723	[MODEM_SW_AHB_RESET] = { 0x2c48, 1 },
2724	[MODEM_RESET] = { 0x2c48 },
2725	[SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 },
2726	[SFAB_MSS_MDM0_RESET] = { 0x2c4c },
2727	[MSS_SLP_RESET] = { 0x2c60, 7 },
2728	[MSS_MARM_SAW_RESET] = { 0x2c68, 1 },
2729	[MSS_WDOG_RESET] = { 0x2c68 },
2730	[TSSC_RESET] = { 0x2ca0, 7 },
2731	[PDM_RESET] = { 0x2cc0, 12 },
2732	[SCSS_CORE0_RESET] = { 0x2d60, 1 },
2733	[SCSS_CORE0_POR_RESET] = { 0x2d60 },
2734	[SCSS_CORE1_RESET] = { 0x2d80, 1 },
2735	[SCSS_CORE1_POR_RESET] = { 0x2d80 },
2736	[MPM_RESET] = { 0x2da4, 1 },
2737	[EBI1_1X_DIV_RESET] = { 0x2dec, 9 },
2738	[EBI1_RESET] = { 0x2dec, 7 },
2739	[SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2740	[USB_PHY0_RESET] = { 0x2e20 },
2741	[USB_PHY1_RESET] = { 0x2e40 },
2742	[PRNG_RESET] = { 0x2e80, 12 },
2743	};
2744
2745	static const struct regmap_config gcc_msm8660_regmap_config = {
2746	.reg_bits = 32,
2747	.reg_stride = 4,
2748	.val_bits = 32,
2749	.max_register = 0x363c,
2750	.fast_io = true,
2751	};
2752
2753	static const struct qcom_cc_desc gcc_msm8660_desc = {
2754	.config = &gcc_msm8660_regmap_config,
2755	.clks = gcc_msm8660_clks,
2756	.num_clks = ARRAY_SIZE(gcc_msm8660_clks),
2757	.resets = gcc_msm8660_resets,
2758	.num_resets = ARRAY_SIZE(gcc_msm8660_resets),
2759	};
2760
2761	static const struct of_device_id gcc_msm8660_match_table[] = {
2762	{ .compatible = "qcom,gcc-msm8660" },
2763	{ }
2764	};
2765	MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
2766
2767	static int gcc_msm8660_probe(struct platform_device *pdev)
2768	{
2769	return qcom_cc_probe(pdev, desc: &gcc_msm8660_desc);
2770	}
2771
2772	static struct platform_driver gcc_msm8660_driver = {
2773	.probe = gcc_msm8660_probe,
2774	.driver = {
2775	.name = "gcc-msm8660",
2776	.of_match_table = gcc_msm8660_match_table,
2777	},
2778	};
2779
2780	static int __init gcc_msm8660_init(void)
2781	{
2782	return platform_driver_register(&gcc_msm8660_driver);
2783	}
2784	core_initcall(gcc_msm8660_init);
2785
2786	static void __exit gcc_msm8660_exit(void)
2787	{
2788	platform_driver_unregister(&gcc_msm8660_driver);
2789	}
2790	module_exit(gcc_msm8660_exit);
2791
2792	MODULE_DESCRIPTION("GCC MSM 8660 Driver");
2793	MODULE_LICENSE("GPL v2");
2794	MODULE_ALIAS("platform:gcc-msm8660");
2795