1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4	*/
5
6	#include <linux/clk-provider.h>
7	#include <linux/kernel.h>
8	#include <linux/platform_device.h>
9	#include <linux/module.h>
10	#include <linux/regmap.h>
11	#include <linux/reset-controller.h>
12
13	#include <dt-bindings/clock/qcom,mmcc-apq8084.h>
14	#include <dt-bindings/reset/qcom,mmcc-apq8084.h>
15
16	#include "common.h"
17	#include "clk-regmap.h"
18	#include "clk-pll.h"
19	#include "clk-rcg.h"
20	#include "clk-branch.h"
21	#include "reset.h"
22	#include "gdsc.h"
23
24	enum {
25	P_XO,
26	P_MMPLL0,
27	P_EDPLINK,
28	P_MMPLL1,
29	P_HDMIPLL,
30	P_GPLL0,
31	P_EDPVCO,
32	P_MMPLL4,
33	P_DSI0PLL,
34	P_DSI0PLL_BYTE,
35	P_MMPLL2,
36	P_MMPLL3,
37	P_GPLL1,
38	P_DSI1PLL,
39	P_DSI1PLL_BYTE,
40	P_MMSLEEP,
41	};
42
43	static struct clk_pll mmpll0 = {
44	.l_reg = 0x0004,
45	.m_reg = 0x0008,
46	.n_reg = 0x000c,
47	.config_reg = 0x0014,
48	.mode_reg = 0x0000,
49	.status_reg = 0x001c,
50	.status_bit = 17,
51	.clkr.hw.init = &(struct clk_init_data){
52	.name = "mmpll0",
53	.parent_data = (const struct clk_parent_data[]){
54	{ .fw_name = "xo", .name = "xo_board" },
55	},
56	.num_parents = 1,
57	.ops = &clk_pll_ops,
58	},
59	};
60
61	static struct clk_regmap mmpll0_vote = {
62	.enable_reg = 0x0100,
63	.enable_mask = BIT(0),
64	.hw.init = &(struct clk_init_data){
65	.name = "mmpll0_vote",
66	.parent_hws = (const struct clk_hw*[]){
67	&mmpll0.clkr.hw
68	},
69	.num_parents = 1,
70	.ops = &clk_pll_vote_ops,
71	},
72	};
73
74	static struct clk_pll mmpll1 = {
75	.l_reg = 0x0044,
76	.m_reg = 0x0048,
77	.n_reg = 0x004c,
78	.config_reg = 0x0050,
79	.mode_reg = 0x0040,
80	.status_reg = 0x005c,
81	.status_bit = 17,
82	.clkr.hw.init = &(struct clk_init_data){
83	.name = "mmpll1",
84	.parent_data = (const struct clk_parent_data[]){
85	{ .fw_name = "xo", .name = "xo_board" },
86	},
87	.num_parents = 1,
88	.ops = &clk_pll_ops,
89	},
90	};
91
92	static struct clk_regmap mmpll1_vote = {
93	.enable_reg = 0x0100,
94	.enable_mask = BIT(1),
95	.hw.init = &(struct clk_init_data){
96	.name = "mmpll1_vote",
97	.parent_hws = (const struct clk_hw*[]){
98	&mmpll1.clkr.hw
99	},
100	.num_parents = 1,
101	.ops = &clk_pll_vote_ops,
102	},
103	};
104
105	static struct clk_pll mmpll2 = {
106	.l_reg = 0x4104,
107	.m_reg = 0x4108,
108	.n_reg = 0x410c,
109	.config_reg = 0x4110,
110	.mode_reg = 0x4100,
111	.status_reg = 0x411c,
112	.clkr.hw.init = &(struct clk_init_data){
113	.name = "mmpll2",
114	.parent_data = (const struct clk_parent_data[]){
115	{ .fw_name = "xo", .name = "xo_board" },
116	},
117	.num_parents = 1,
118	.ops = &clk_pll_ops,
119	},
120	};
121
122	static struct clk_pll mmpll3 = {
123	.l_reg = 0x0084,
124	.m_reg = 0x0088,
125	.n_reg = 0x008c,
126	.config_reg = 0x0090,
127	.mode_reg = 0x0080,
128	.status_reg = 0x009c,
129	.status_bit = 17,
130	.clkr.hw.init = &(struct clk_init_data){
131	.name = "mmpll3",
132	.parent_data = (const struct clk_parent_data[]){
133	{ .fw_name = "xo", .name = "xo_board" },
134	},
135	.num_parents = 1,
136	.ops = &clk_pll_ops,
137	},
138	};
139
140	static struct clk_pll mmpll4 = {
141	.l_reg = 0x00a4,
142	.m_reg = 0x00a8,
143	.n_reg = 0x00ac,
144	.config_reg = 0x00b0,
145	.mode_reg = 0x0080,
146	.status_reg = 0x00bc,
147	.clkr.hw.init = &(struct clk_init_data){
148	.name = "mmpll4",
149	.parent_data = (const struct clk_parent_data[]){
150	{ .fw_name = "xo", .name = "xo_board" },
151	},
152	.num_parents = 1,
153	.ops = &clk_pll_ops,
154	},
155	};
156
157	static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
158	{ P_XO, 0 },
159	{ P_MMPLL0, 1 },
160	{ P_MMPLL1, 2 },
161	{ P_GPLL0, 5 }
162	};
163
164	static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
165	{ .fw_name = "xo", .name = "xo_board" },
166	{ .hw = &mmpll0_vote.hw },
167	{ .hw = &mmpll1_vote.hw },
168	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
169	};
170
171	static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
172	{ P_XO, 0 },
173	{ P_MMPLL0, 1 },
174	{ P_HDMIPLL, 4 },
175	{ P_GPLL0, 5 },
176	{ P_DSI0PLL, 2 },
177	{ P_DSI1PLL, 3 }
178	};
179
180	static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
181	{ .fw_name = "xo", .name = "xo_board" },
182	{ .hw = &mmpll0_vote.hw },
183	{ .fw_name = "hdmipll", .name = "hdmipll" },
184	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
185	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
186	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
187	};
188
189	static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
190	{ P_XO, 0 },
191	{ P_MMPLL0, 1 },
192	{ P_MMPLL1, 2 },
193	{ P_GPLL0, 5 },
194	{ P_MMPLL2, 3 }
195	};
196
197	static const struct clk_parent_data mmcc_xo_mmpll0_1_2_gpll0[] = {
198	{ .fw_name = "xo", .name = "xo_board" },
199	{ .hw = &mmpll0_vote.hw },
200	{ .hw = &mmpll1_vote.hw },
201	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
202	{ .hw = &mmpll2.clkr.hw },
203	};
204
205	static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
206	{ P_XO, 0 },
207	{ P_MMPLL0, 1 },
208	{ P_MMPLL1, 2 },
209	{ P_GPLL0, 5 },
210	{ P_MMPLL3, 3 }
211	};
212
213	static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
214	{ .fw_name = "xo", .name = "xo_board" },
215	{ .hw = &mmpll0_vote.hw },
216	{ .hw = &mmpll1_vote.hw },
217	{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
218	{ .hw = &mmpll3.clkr.hw },
219	};
220
221	static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
222	{ P_XO, 0 },
223	{ P_EDPLINK, 4 },
224	{ P_HDMIPLL, 3 },
225	{ P_EDPVCO, 5 },
226	{ P_DSI0PLL, 1 },
227	{ P_DSI1PLL, 2 }
228	};
229
230	static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
231	{ .fw_name = "xo", .name = "xo_board" },
232	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
233	{ .fw_name = "hdmipll", .name = "hdmipll" },
234	{ .fw_name = "edp_vco_div", .name = "edp_vco_div" },
235	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
236	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
237	};
238
239	static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
240	{ P_XO, 0 },
241	{ P_EDPLINK, 4 },
242	{ P_HDMIPLL, 3 },
243	{ P_GPLL0, 5 },
244	{ P_DSI0PLL, 1 },
245	{ P_DSI1PLL, 2 }
246	};
247
248	static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
249	{ .fw_name = "xo", .name = "xo_board" },
250	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
251	{ .fw_name = "hdmipll", .name = "hdmipll" },
252	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
253	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
254	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
255	};
256
257	static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
258	{ P_XO, 0 },
259	{ P_EDPLINK, 4 },
260	{ P_HDMIPLL, 3 },
261	{ P_GPLL0, 5 },
262	{ P_DSI0PLL_BYTE, 1 },
263	{ P_DSI1PLL_BYTE, 2 }
264	};
265
266	static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
267	{ .fw_name = "xo", .name = "xo_board" },
268	{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
269	{ .fw_name = "hdmipll", .name = "hdmipll" },
270	{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
271	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
272	{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
273	};
274
275	static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
276	{ P_XO, 0 },
277	{ P_MMPLL0, 1 },
278	{ P_MMPLL1, 2 },
279	{ P_GPLL0, 5 },
280	{ P_MMPLL4, 3 }
281	};
282
283	static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll0[] = {
284	{ .fw_name = "xo", .name = "xo_board" },
285	{ .hw = &mmpll0.clkr.hw },
286	{ .hw = &mmpll1.clkr.hw },
287	{ .hw = &mmpll4.clkr.hw },
288	{ .fw_name = "gpll0", .name = "gpll0" },
289	};
290
291	static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
292	{ P_XO, 0 },
293	{ P_MMPLL0, 1 },
294	{ P_MMPLL1, 2 },
295	{ P_MMPLL4, 3 },
296	{ P_GPLL0, 5 },
297	{ P_GPLL1, 4 }
298	};
299
300	static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0[] = {
301	{ .fw_name = "xo", .name = "xo_board" },
302	{ .hw = &mmpll0.clkr.hw },
303	{ .hw = &mmpll1.clkr.hw },
304	{ .hw = &mmpll4.clkr.hw },
305	{ .fw_name = "gpll1", .name = "gpll1" },
306	{ .fw_name = "gpll0", .name = "gpll0" },
307	};
308
309	static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
310	{ P_XO, 0 },
311	{ P_MMPLL0, 1 },
312	{ P_MMPLL1, 2 },
313	{ P_MMPLL4, 3 },
314	{ P_GPLL0, 5 },
315	{ P_GPLL1, 4 },
316	{ P_MMSLEEP, 6 }
317	};
318
319	static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
320	{ .fw_name = "xo", .name = "xo_board" },
321	{ .hw = &mmpll0.clkr.hw },
322	{ .hw = &mmpll1.clkr.hw },
323	{ .hw = &mmpll4.clkr.hw },
324	{ .fw_name = "gpll1", .name = "gpll1" },
325	{ .fw_name = "gpll0", .name = "gpll0" },
326	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
327	};
328
329	static struct clk_rcg2 mmss_ahb_clk_src = {
330	.cmd_rcgr = 0x5000,
331	.hid_width = 5,
332	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
333	.clkr.hw.init = &(struct clk_init_data){
334	.name = "mmss_ahb_clk_src",
335	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
336	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
337	.ops = &clk_rcg2_ops,
338	},
339	};
340
341	static struct freq_tbl ftbl_mmss_axi_clk[] = {
342	F(19200000, P_XO, 1, 0, 0),
343	F(37500000, P_GPLL0, 16, 0, 0),
344	F(50000000, P_GPLL0, 12, 0, 0),
345	F(75000000, P_GPLL0, 8, 0, 0),
346	F(100000000, P_GPLL0, 6, 0, 0),
347	F(150000000, P_GPLL0, 4, 0, 0),
348	F(333430000, P_MMPLL1, 3.5, 0, 0),
349	F(400000000, P_MMPLL0, 2, 0, 0),
350	F(466800000, P_MMPLL1, 2.5, 0, 0),
351	};
352
353	static struct clk_rcg2 mmss_axi_clk_src = {
354	.cmd_rcgr = 0x5040,
355	.hid_width = 5,
356	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
357	.freq_tbl = ftbl_mmss_axi_clk,
358	.clkr.hw.init = &(struct clk_init_data){
359	.name = "mmss_axi_clk_src",
360	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
361	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
362	.ops = &clk_rcg2_ops,
363	},
364	};
365
366	static struct freq_tbl ftbl_ocmemnoc_clk[] = {
367	F(19200000, P_XO, 1, 0, 0),
368	F(37500000, P_GPLL0, 16, 0, 0),
369	F(50000000, P_GPLL0, 12, 0, 0),
370	F(75000000, P_GPLL0, 8, 0, 0),
371	F(109090000, P_GPLL0, 5.5, 0, 0),
372	F(150000000, P_GPLL0, 4, 0, 0),
373	F(228570000, P_MMPLL0, 3.5, 0, 0),
374	F(320000000, P_MMPLL0, 2.5, 0, 0),
375	};
376
377	static struct clk_rcg2 ocmemnoc_clk_src = {
378	.cmd_rcgr = 0x5090,
379	.hid_width = 5,
380	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
381	.freq_tbl = ftbl_ocmemnoc_clk,
382	.clkr.hw.init = &(struct clk_init_data){
383	.name = "ocmemnoc_clk_src",
384	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
385	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
386	.ops = &clk_rcg2_ops,
387	},
388	};
389
390	static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
391	F(100000000, P_GPLL0, 6, 0, 0),
392	F(200000000, P_MMPLL0, 4, 0, 0),
393	{ }
394	};
395
396	static struct clk_rcg2 csi0_clk_src = {
397	.cmd_rcgr = 0x3090,
398	.hid_width = 5,
399	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
400	.freq_tbl = ftbl_camss_csi0_3_clk,
401	.clkr.hw.init = &(struct clk_init_data){
402	.name = "csi0_clk_src",
403	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
404	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
405	.ops = &clk_rcg2_ops,
406	},
407	};
408
409	static struct clk_rcg2 csi1_clk_src = {
410	.cmd_rcgr = 0x3100,
411	.hid_width = 5,
412	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
413	.freq_tbl = ftbl_camss_csi0_3_clk,
414	.clkr.hw.init = &(struct clk_init_data){
415	.name = "csi1_clk_src",
416	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
417	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
418	.ops = &clk_rcg2_ops,
419	},
420	};
421
422	static struct clk_rcg2 csi2_clk_src = {
423	.cmd_rcgr = 0x3160,
424	.hid_width = 5,
425	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
426	.freq_tbl = ftbl_camss_csi0_3_clk,
427	.clkr.hw.init = &(struct clk_init_data){
428	.name = "csi2_clk_src",
429	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
430	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
431	.ops = &clk_rcg2_ops,
432	},
433	};
434
435	static struct clk_rcg2 csi3_clk_src = {
436	.cmd_rcgr = 0x31c0,
437	.hid_width = 5,
438	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
439	.freq_tbl = ftbl_camss_csi0_3_clk,
440	.clkr.hw.init = &(struct clk_init_data){
441	.name = "csi3_clk_src",
442	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
443	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
444	.ops = &clk_rcg2_ops,
445	},
446	};
447
448	static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
449	F(37500000, P_GPLL0, 16, 0, 0),
450	F(50000000, P_GPLL0, 12, 0, 0),
451	F(60000000, P_GPLL0, 10, 0, 0),
452	F(80000000, P_GPLL0, 7.5, 0, 0),
453	F(100000000, P_GPLL0, 6, 0, 0),
454	F(109090000, P_GPLL0, 5.5, 0, 0),
455	F(133330000, P_GPLL0, 4.5, 0, 0),
456	F(200000000, P_GPLL0, 3, 0, 0),
457	F(228570000, P_MMPLL0, 3.5, 0, 0),
458	F(266670000, P_MMPLL0, 3, 0, 0),
459	F(320000000, P_MMPLL0, 2.5, 0, 0),
460	F(465000000, P_MMPLL4, 2, 0, 0),
461	F(600000000, P_GPLL0, 1, 0, 0),
462	{ }
463	};
464
465	static struct clk_rcg2 vfe0_clk_src = {
466	.cmd_rcgr = 0x3600,
467	.hid_width = 5,
468	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
469	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
470	.clkr.hw.init = &(struct clk_init_data){
471	.name = "vfe0_clk_src",
472	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
473	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
474	.ops = &clk_rcg2_ops,
475	},
476	};
477
478	static struct clk_rcg2 vfe1_clk_src = {
479	.cmd_rcgr = 0x3620,
480	.hid_width = 5,
481	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
482	.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
483	.clkr.hw.init = &(struct clk_init_data){
484	.name = "vfe1_clk_src",
485	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
486	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
487	.ops = &clk_rcg2_ops,
488	},
489	};
490
491	static struct freq_tbl ftbl_mdss_mdp_clk[] = {
492	F(37500000, P_GPLL0, 16, 0, 0),
493	F(60000000, P_GPLL0, 10, 0, 0),
494	F(75000000, P_GPLL0, 8, 0, 0),
495	F(85710000, P_GPLL0, 7, 0, 0),
496	F(100000000, P_GPLL0, 6, 0, 0),
497	F(150000000, P_GPLL0, 4, 0, 0),
498	F(160000000, P_MMPLL0, 5, 0, 0),
499	F(200000000, P_MMPLL0, 4, 0, 0),
500	F(228570000, P_MMPLL0, 3.5, 0, 0),
501	F(300000000, P_GPLL0, 2, 0, 0),
502	F(320000000, P_MMPLL0, 2.5, 0, 0),
503	{ }
504	};
505
506	static struct clk_rcg2 mdp_clk_src = {
507	.cmd_rcgr = 0x2040,
508	.hid_width = 5,
509	.parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
510	.freq_tbl = ftbl_mdss_mdp_clk,
511	.clkr.hw.init = &(struct clk_init_data){
512	.name = "mdp_clk_src",
513	.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
514	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
515	.ops = &clk_rcg2_ops,
516	},
517	};
518
519	static struct clk_rcg2 gfx3d_clk_src = {
520	.cmd_rcgr = 0x4000,
521	.hid_width = 5,
522	.parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
523	.clkr.hw.init = &(struct clk_init_data){
524	.name = "gfx3d_clk_src",
525	.parent_data = mmcc_xo_mmpll0_1_2_gpll0,
526	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0),
527	.ops = &clk_rcg2_ops,
528	},
529	};
530
531	static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
532	F(75000000, P_GPLL0, 8, 0, 0),
533	F(133330000, P_GPLL0, 4.5, 0, 0),
534	F(200000000, P_GPLL0, 3, 0, 0),
535	F(228570000, P_MMPLL0, 3.5, 0, 0),
536	F(266670000, P_MMPLL0, 3, 0, 0),
537	F(320000000, P_MMPLL0, 2.5, 0, 0),
538	{ }
539	};
540
541	static struct clk_rcg2 jpeg0_clk_src = {
542	.cmd_rcgr = 0x3500,
543	.hid_width = 5,
544	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
545	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
546	.clkr.hw.init = &(struct clk_init_data){
547	.name = "jpeg0_clk_src",
548	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
549	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
550	.ops = &clk_rcg2_ops,
551	},
552	};
553
554	static struct clk_rcg2 jpeg1_clk_src = {
555	.cmd_rcgr = 0x3520,
556	.hid_width = 5,
557	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
558	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
559	.clkr.hw.init = &(struct clk_init_data){
560	.name = "jpeg1_clk_src",
561	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
562	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
563	.ops = &clk_rcg2_ops,
564	},
565	};
566
567	static struct clk_rcg2 jpeg2_clk_src = {
568	.cmd_rcgr = 0x3540,
569	.hid_width = 5,
570	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
571	.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
572	.clkr.hw.init = &(struct clk_init_data){
573	.name = "jpeg2_clk_src",
574	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
575	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
576	.ops = &clk_rcg2_ops,
577	},
578	};
579
580	static struct clk_rcg2 pclk0_clk_src = {
581	.cmd_rcgr = 0x2000,
582	.mnd_width = 8,
583	.hid_width = 5,
584	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
585	.clkr.hw.init = &(struct clk_init_data){
586	.name = "pclk0_clk_src",
587	.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
588	.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
589	.ops = &clk_pixel_ops,
590	.flags = CLK_SET_RATE_PARENT,
591	},
592	};
593
594	static struct clk_rcg2 pclk1_clk_src = {
595	.cmd_rcgr = 0x2020,
596	.mnd_width = 8,
597	.hid_width = 5,
598	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
599	.clkr.hw.init = &(struct clk_init_data){
600	.name = "pclk1_clk_src",
601	.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
602	.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
603	.ops = &clk_pixel_ops,
604	.flags = CLK_SET_RATE_PARENT,
605	},
606	};
607
608	static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
609	F(50000000, P_GPLL0, 12, 0, 0),
610	F(100000000, P_GPLL0, 6, 0, 0),
611	F(133330000, P_GPLL0, 4.5, 0, 0),
612	F(200000000, P_MMPLL0, 4, 0, 0),
613	F(266670000, P_MMPLL0, 3, 0, 0),
614	F(465000000, P_MMPLL3, 2, 0, 0),
615	{ }
616	};
617
618	static struct clk_rcg2 vcodec0_clk_src = {
619	.cmd_rcgr = 0x1000,
620	.mnd_width = 8,
621	.hid_width = 5,
622	.parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
623	.freq_tbl = ftbl_venus0_vcodec0_clk,
624	.clkr.hw.init = &(struct clk_init_data){
625	.name = "vcodec0_clk_src",
626	.parent_data = mmcc_xo_mmpll0_1_3_gpll0,
627	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
628	.ops = &clk_rcg2_ops,
629	},
630	};
631
632	static struct freq_tbl ftbl_avsync_vp_clk[] = {
633	F(150000000, P_GPLL0, 4, 0, 0),
634	F(320000000, P_MMPLL0, 2.5, 0, 0),
635	{ }
636	};
637
638	static struct clk_rcg2 vp_clk_src = {
639	.cmd_rcgr = 0x2430,
640	.hid_width = 5,
641	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
642	.freq_tbl = ftbl_avsync_vp_clk,
643	.clkr.hw.init = &(struct clk_init_data){
644	.name = "vp_clk_src",
645	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
646	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
647	.ops = &clk_rcg2_ops,
648	},
649	};
650
651	static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
652	F(19200000, P_XO, 1, 0, 0),
653	{ }
654	};
655
656	static struct clk_rcg2 cci_clk_src = {
657	.cmd_rcgr = 0x3300,
658	.mnd_width = 8,
659	.hid_width = 5,
660	.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
661	.freq_tbl = ftbl_camss_cci_cci_clk,
662	.clkr.hw.init = &(struct clk_init_data){
663	.name = "cci_clk_src",
664	.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
665	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
666	.ops = &clk_rcg2_ops,
667	},
668	};
669
670	static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
671	F(10000, P_XO, 16, 1, 120),
672	F(24000, P_XO, 16, 1, 50),
673	F(6000000, P_GPLL0, 10, 1, 10),
674	F(12000000, P_GPLL0, 10, 1, 5),
675	F(13000000, P_GPLL0, 4, 13, 150),
676	F(24000000, P_GPLL0, 5, 1, 5),
677	{ }
678	};
679
680	static struct clk_rcg2 camss_gp0_clk_src = {
681	.cmd_rcgr = 0x3420,
682	.mnd_width = 8,
683	.hid_width = 5,
684	.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
685	.freq_tbl = ftbl_camss_gp0_1_clk,
686	.clkr.hw.init = &(struct clk_init_data){
687	.name = "camss_gp0_clk_src",
688	.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
689	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
690	.ops = &clk_rcg2_ops,
691	},
692	};
693
694	static struct clk_rcg2 camss_gp1_clk_src = {
695	.cmd_rcgr = 0x3450,
696	.mnd_width = 8,
697	.hid_width = 5,
698	.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
699	.freq_tbl = ftbl_camss_gp0_1_clk,
700	.clkr.hw.init = &(struct clk_init_data){
701	.name = "camss_gp1_clk_src",
702	.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
703	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
704	.ops = &clk_rcg2_ops,
705	},
706	};
707
708	static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
709	F(4800000, P_XO, 4, 0, 0),
710	F(6000000, P_GPLL0, 10, 1, 10),
711	F(8000000, P_GPLL0, 15, 1, 5),
712	F(9600000, P_XO, 2, 0, 0),
713	F(16000000, P_MMPLL0, 10, 1, 5),
714	F(19200000, P_XO, 1, 0, 0),
715	F(24000000, P_GPLL0, 5, 1, 5),
716	F(32000000, P_MMPLL0, 5, 1, 5),
717	F(48000000, P_GPLL0, 12.5, 0, 0),
718	F(64000000, P_MMPLL0, 12.5, 0, 0),
719	{ }
720	};
721
722	static struct clk_rcg2 mclk0_clk_src = {
723	.cmd_rcgr = 0x3360,
724	.mnd_width = 8,
725	.hid_width = 5,
726	.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
727	.freq_tbl = ftbl_camss_mclk0_3_clk,
728	.clkr.hw.init = &(struct clk_init_data){
729	.name = "mclk0_clk_src",
730	.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
731	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
732	.ops = &clk_rcg2_ops,
733	},
734	};
735
736	static struct clk_rcg2 mclk1_clk_src = {
737	.cmd_rcgr = 0x3390,
738	.mnd_width = 8,
739	.hid_width = 5,
740	.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
741	.freq_tbl = ftbl_camss_mclk0_3_clk,
742	.clkr.hw.init = &(struct clk_init_data){
743	.name = "mclk1_clk_src",
744	.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
745	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
746	.ops = &clk_rcg2_ops,
747	},
748	};
749
750	static struct clk_rcg2 mclk2_clk_src = {
751	.cmd_rcgr = 0x33c0,
752	.mnd_width = 8,
753	.hid_width = 5,
754	.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
755	.freq_tbl = ftbl_camss_mclk0_3_clk,
756	.clkr.hw.init = &(struct clk_init_data){
757	.name = "mclk2_clk_src",
758	.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
759	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
760	.ops = &clk_rcg2_ops,
761	},
762	};
763
764	static struct clk_rcg2 mclk3_clk_src = {
765	.cmd_rcgr = 0x33f0,
766	.mnd_width = 8,
767	.hid_width = 5,
768	.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
769	.freq_tbl = ftbl_camss_mclk0_3_clk,
770	.clkr.hw.init = &(struct clk_init_data){
771	.name = "mclk3_clk_src",
772	.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
773	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
774	.ops = &clk_rcg2_ops,
775	},
776	};
777
778	static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
779	F(100000000, P_GPLL0, 6, 0, 0),
780	F(200000000, P_MMPLL0, 4, 0, 0),
781	{ }
782	};
783
784	static struct clk_rcg2 csi0phytimer_clk_src = {
785	.cmd_rcgr = 0x3000,
786	.hid_width = 5,
787	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
788	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
789	.clkr.hw.init = &(struct clk_init_data){
790	.name = "csi0phytimer_clk_src",
791	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
792	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
793	.ops = &clk_rcg2_ops,
794	},
795	};
796
797	static struct clk_rcg2 csi1phytimer_clk_src = {
798	.cmd_rcgr = 0x3030,
799	.hid_width = 5,
800	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
801	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
802	.clkr.hw.init = &(struct clk_init_data){
803	.name = "csi1phytimer_clk_src",
804	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
805	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
806	.ops = &clk_rcg2_ops,
807	},
808	};
809
810	static struct clk_rcg2 csi2phytimer_clk_src = {
811	.cmd_rcgr = 0x3060,
812	.hid_width = 5,
813	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
814	.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
815	.clkr.hw.init = &(struct clk_init_data){
816	.name = "csi2phytimer_clk_src",
817	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
818	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
819	.ops = &clk_rcg2_ops,
820	},
821	};
822
823	static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
824	F(133330000, P_GPLL0, 4.5, 0, 0),
825	F(266670000, P_MMPLL0, 3, 0, 0),
826	F(320000000, P_MMPLL0, 2.5, 0, 0),
827	F(372000000, P_MMPLL4, 2.5, 0, 0),
828	F(465000000, P_MMPLL4, 2, 0, 0),
829	F(600000000, P_GPLL0, 1, 0, 0),
830	{ }
831	};
832
833	static struct clk_rcg2 cpp_clk_src = {
834	.cmd_rcgr = 0x3640,
835	.hid_width = 5,
836	.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
837	.freq_tbl = ftbl_camss_vfe_cpp_clk,
838	.clkr.hw.init = &(struct clk_init_data){
839	.name = "cpp_clk_src",
840	.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
841	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
842	.ops = &clk_rcg2_ops,
843	},
844	};
845
846	static struct clk_rcg2 byte0_clk_src = {
847	.cmd_rcgr = 0x2120,
848	.hid_width = 5,
849	.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
850	.clkr.hw.init = &(struct clk_init_data){
851	.name = "byte0_clk_src",
852	.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
853	.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
854	.ops = &clk_byte2_ops,
855	.flags = CLK_SET_RATE_PARENT,
856	},
857	};
858
859	static struct clk_rcg2 byte1_clk_src = {
860	.cmd_rcgr = 0x2140,
861	.hid_width = 5,
862	.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
863	.clkr.hw.init = &(struct clk_init_data){
864	.name = "byte1_clk_src",
865	.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
866	.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
867	.ops = &clk_byte2_ops,
868	.flags = CLK_SET_RATE_PARENT,
869	},
870	};
871
872	static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
873	F(19200000, P_XO, 1, 0, 0),
874	{ }
875	};
876
877	static struct clk_rcg2 edpaux_clk_src = {
878	.cmd_rcgr = 0x20e0,
879	.hid_width = 5,
880	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
881	.freq_tbl = ftbl_mdss_edpaux_clk,
882	.clkr.hw.init = &(struct clk_init_data){
883	.name = "edpaux_clk_src",
884	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
885	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
886	.ops = &clk_rcg2_ops,
887	},
888	};
889
890	static struct freq_tbl ftbl_mdss_edplink_clk[] = {
891	F(135000000, P_EDPLINK, 2, 0, 0),
892	F(270000000, P_EDPLINK, 11, 0, 0),
893	{ }
894	};
895
896	static struct clk_rcg2 edplink_clk_src = {
897	.cmd_rcgr = 0x20c0,
898	.hid_width = 5,
899	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
900	.freq_tbl = ftbl_mdss_edplink_clk,
901	.clkr.hw.init = &(struct clk_init_data){
902	.name = "edplink_clk_src",
903	.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
904	.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
905	.ops = &clk_rcg2_ops,
906	.flags = CLK_SET_RATE_PARENT,
907	},
908	};
909
910	static struct freq_tbl edp_pixel_freq_tbl[] = {
911	{ .src = P_EDPVCO },
912	{ }
913	};
914
915	static struct clk_rcg2 edppixel_clk_src = {
916	.cmd_rcgr = 0x20a0,
917	.mnd_width = 8,
918	.hid_width = 5,
919	.parent_map = mmcc_xo_dsi_hdmi_edp_map,
920	.freq_tbl = edp_pixel_freq_tbl,
921	.clkr.hw.init = &(struct clk_init_data){
922	.name = "edppixel_clk_src",
923	.parent_data = mmcc_xo_dsi_hdmi_edp,
924	.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
925	.ops = &clk_edp_pixel_ops,
926	},
927	};
928
929	static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
930	F(19200000, P_XO, 1, 0, 0),
931	{ }
932	};
933
934	static struct clk_rcg2 esc0_clk_src = {
935	.cmd_rcgr = 0x2160,
936	.hid_width = 5,
937	.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
938	.freq_tbl = ftbl_mdss_esc0_1_clk,
939	.clkr.hw.init = &(struct clk_init_data){
940	.name = "esc0_clk_src",
941	.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
942	.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
943	.ops = &clk_rcg2_ops,
944	},
945	};
946
947	static struct clk_rcg2 esc1_clk_src = {
948	.cmd_rcgr = 0x2180,
949	.hid_width = 5,
950	.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
951	.freq_tbl = ftbl_mdss_esc0_1_clk,
952	.clkr.hw.init = &(struct clk_init_data){
953	.name = "esc1_clk_src",
954	.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
955	.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
956	.ops = &clk_rcg2_ops,
957	},
958	};
959
960	static struct freq_tbl extpclk_freq_tbl[] = {
961	{ .src = P_HDMIPLL },
962	{ }
963	};
964
965	static struct clk_rcg2 extpclk_clk_src = {
966	.cmd_rcgr = 0x2060,
967	.hid_width = 5,
968	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
969	.freq_tbl = extpclk_freq_tbl,
970	.clkr.hw.init = &(struct clk_init_data){
971	.name = "extpclk_clk_src",
972	.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
973	.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
974	.ops = &clk_byte_ops,
975	.flags = CLK_SET_RATE_PARENT,
976	},
977	};
978
979	static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
980	F(19200000, P_XO, 1, 0, 0),
981	{ }
982	};
983
984	static struct clk_rcg2 hdmi_clk_src = {
985	.cmd_rcgr = 0x2100,
986	.hid_width = 5,
987	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
988	.freq_tbl = ftbl_mdss_hdmi_clk,
989	.clkr.hw.init = &(struct clk_init_data){
990	.name = "hdmi_clk_src",
991	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
992	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
993	.ops = &clk_rcg2_ops,
994	},
995	};
996
997	static struct freq_tbl ftbl_mdss_vsync_clk[] = {
998	F(19200000, P_XO, 1, 0, 0),
999	{ }
1000	};
1001
1002	static struct clk_rcg2 vsync_clk_src = {
1003	.cmd_rcgr = 0x2080,
1004	.hid_width = 5,
1005	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1006	.freq_tbl = ftbl_mdss_vsync_clk,
1007	.clkr.hw.init = &(struct clk_init_data){
1008	.name = "vsync_clk_src",
1009	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
1010	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
1011	.ops = &clk_rcg2_ops,
1012	},
1013	};
1014
1015	static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1016	F(50000000, P_GPLL0, 12, 0, 0),
1017	{ }
1018	};
1019
1020	static struct clk_rcg2 rbcpr_clk_src = {
1021	.cmd_rcgr = 0x4060,
1022	.hid_width = 5,
1023	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1024	.freq_tbl = ftbl_mmss_rbcpr_clk,
1025	.clkr.hw.init = &(struct clk_init_data){
1026	.name = "rbcpr_clk_src",
1027	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
1028	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
1029	.ops = &clk_rcg2_ops,
1030	},
1031	};
1032
1033	static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1034	F(19200000, P_XO, 1, 0, 0),
1035	{ }
1036	};
1037
1038	static struct clk_rcg2 rbbmtimer_clk_src = {
1039	.cmd_rcgr = 0x4090,
1040	.hid_width = 5,
1041	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1042	.freq_tbl = ftbl_oxili_rbbmtimer_clk,
1043	.clkr.hw.init = &(struct clk_init_data){
1044	.name = "rbbmtimer_clk_src",
1045	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
1046	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
1047	.ops = &clk_rcg2_ops,
1048	},
1049	};
1050
1051	static struct freq_tbl ftbl_vpu_maple_clk[] = {
1052	F(50000000, P_GPLL0, 12, 0, 0),
1053	F(100000000, P_GPLL0, 6, 0, 0),
1054	F(133330000, P_GPLL0, 4.5, 0, 0),
1055	F(200000000, P_MMPLL0, 4, 0, 0),
1056	F(266670000, P_MMPLL0, 3, 0, 0),
1057	F(465000000, P_MMPLL3, 2, 0, 0),
1058	{ }
1059	};
1060
1061	static struct clk_rcg2 maple_clk_src = {
1062	.cmd_rcgr = 0x1320,
1063	.hid_width = 5,
1064	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1065	.freq_tbl = ftbl_vpu_maple_clk,
1066	.clkr.hw.init = &(struct clk_init_data){
1067	.name = "maple_clk_src",
1068	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
1069	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
1070	.ops = &clk_rcg2_ops,
1071	},
1072	};
1073
1074	static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1075	F(50000000, P_GPLL0, 12, 0, 0),
1076	F(100000000, P_GPLL0, 6, 0, 0),
1077	F(200000000, P_MMPLL0, 4, 0, 0),
1078	F(320000000, P_MMPLL0, 2.5, 0, 0),
1079	F(400000000, P_MMPLL0, 2, 0, 0),
1080	{ }
1081	};
1082
1083	static struct clk_rcg2 vdp_clk_src = {
1084	.cmd_rcgr = 0x1300,
1085	.hid_width = 5,
1086	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1087	.freq_tbl = ftbl_vpu_vdp_clk,
1088	.clkr.hw.init = &(struct clk_init_data){
1089	.name = "vdp_clk_src",
1090	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
1091	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
1092	.ops = &clk_rcg2_ops,
1093	},
1094	};
1095
1096	static struct freq_tbl ftbl_vpu_bus_clk[] = {
1097	F(40000000, P_GPLL0, 15, 0, 0),
1098	F(80000000, P_MMPLL0, 10, 0, 0),
1099	{ }
1100	};
1101
1102	static struct clk_rcg2 vpu_bus_clk_src = {
1103	.cmd_rcgr = 0x1340,
1104	.hid_width = 5,
1105	.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1106	.freq_tbl = ftbl_vpu_bus_clk,
1107	.clkr.hw.init = &(struct clk_init_data){
1108	.name = "vpu_bus_clk_src",
1109	.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
1110	.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
1111	.ops = &clk_rcg2_ops,
1112	},
1113	};
1114
1115	static struct clk_branch mmss_cxo_clk = {
1116	.halt_reg = 0x5104,
1117	.clkr = {
1118	.enable_reg = 0x5104,
1119	.enable_mask = BIT(0),
1120	.hw.init = &(struct clk_init_data){
1121	.name = "mmss_cxo_clk",
1122	.parent_data = (const struct clk_parent_data[]){
1123	{ .fw_name = "xo", .name = "xo_board" },
1124	},
1125	.num_parents = 1,
1126	.flags = CLK_SET_RATE_PARENT,
1127	.ops = &clk_branch2_ops,
1128	},
1129	},
1130	};
1131
1132	static struct clk_branch mmss_sleepclk_clk = {
1133	.halt_reg = 0x5100,
1134	.clkr = {
1135	.enable_reg = 0x5100,
1136	.enable_mask = BIT(0),
1137	.hw.init = &(struct clk_init_data){
1138	.name = "mmss_sleepclk_clk",
1139	.parent_data = (const struct clk_parent_data[]){
1140	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
1141	},
1142	.num_parents = 1,
1143	.flags = CLK_SET_RATE_PARENT,
1144	.ops = &clk_branch2_ops,
1145	},
1146	},
1147	};
1148
1149	static struct clk_branch avsync_ahb_clk = {
1150	.halt_reg = 0x2414,
1151	.clkr = {
1152	.enable_reg = 0x2414,
1153	.enable_mask = BIT(0),
1154	.hw.init = &(struct clk_init_data){
1155	.name = "avsync_ahb_clk",
1156	.parent_hws = (const struct clk_hw*[]){
1157	&mmss_ahb_clk_src.clkr.hw
1158	},
1159	.num_parents = 1,
1160	.flags = CLK_SET_RATE_PARENT,
1161	.ops = &clk_branch2_ops,
1162	},
1163	},
1164	};
1165
1166	static struct clk_branch avsync_edppixel_clk = {
1167	.halt_reg = 0x2418,
1168	.clkr = {
1169	.enable_reg = 0x2418,
1170	.enable_mask = BIT(0),
1171	.hw.init = &(struct clk_init_data){
1172	.name = "avsync_edppixel_clk",
1173	.parent_hws = (const struct clk_hw*[]){
1174	&edppixel_clk_src.clkr.hw
1175	},
1176	.num_parents = 1,
1177	.flags = CLK_SET_RATE_PARENT,
1178	.ops = &clk_branch2_ops,
1179	},
1180	},
1181	};
1182
1183	static struct clk_branch avsync_extpclk_clk = {
1184	.halt_reg = 0x2410,
1185	.clkr = {
1186	.enable_reg = 0x2410,
1187	.enable_mask = BIT(0),
1188	.hw.init = &(struct clk_init_data){
1189	.name = "avsync_extpclk_clk",
1190	.parent_hws = (const struct clk_hw*[]){
1191	&extpclk_clk_src.clkr.hw
1192	},
1193	.num_parents = 1,
1194	.flags = CLK_SET_RATE_PARENT,
1195	.ops = &clk_branch2_ops,
1196	},
1197	},
1198	};
1199
1200	static struct clk_branch avsync_pclk0_clk = {
1201	.halt_reg = 0x241c,
1202	.clkr = {
1203	.enable_reg = 0x241c,
1204	.enable_mask = BIT(0),
1205	.hw.init = &(struct clk_init_data){
1206	.name = "avsync_pclk0_clk",
1207	.parent_hws = (const struct clk_hw*[]){
1208	&pclk0_clk_src.clkr.hw
1209	},
1210	.num_parents = 1,
1211	.flags = CLK_SET_RATE_PARENT,
1212	.ops = &clk_branch2_ops,
1213	},
1214	},
1215	};
1216
1217	static struct clk_branch avsync_pclk1_clk = {
1218	.halt_reg = 0x2420,
1219	.clkr = {
1220	.enable_reg = 0x2420,
1221	.enable_mask = BIT(0),
1222	.hw.init = &(struct clk_init_data){
1223	.name = "avsync_pclk1_clk",
1224	.parent_hws = (const struct clk_hw*[]){
1225	&pclk1_clk_src.clkr.hw
1226	},
1227	.num_parents = 1,
1228	.flags = CLK_SET_RATE_PARENT,
1229	.ops = &clk_branch2_ops,
1230	},
1231	},
1232	};
1233
1234	static struct clk_branch avsync_vp_clk = {
1235	.halt_reg = 0x2404,
1236	.clkr = {
1237	.enable_reg = 0x2404,
1238	.enable_mask = BIT(0),
1239	.hw.init = &(struct clk_init_data){
1240	.name = "avsync_vp_clk",
1241	.parent_hws = (const struct clk_hw*[]){
1242	&vp_clk_src.clkr.hw
1243	},
1244	.num_parents = 1,
1245	.flags = CLK_SET_RATE_PARENT,
1246	.ops = &clk_branch2_ops,
1247	},
1248	},
1249	};
1250
1251	static struct clk_branch camss_ahb_clk = {
1252	.halt_reg = 0x348c,
1253	.clkr = {
1254	.enable_reg = 0x348c,
1255	.enable_mask = BIT(0),
1256	.hw.init = &(struct clk_init_data){
1257	.name = "camss_ahb_clk",
1258	.parent_hws = (const struct clk_hw*[]){
1259	&mmss_ahb_clk_src.clkr.hw
1260	},
1261	.num_parents = 1,
1262	.flags = CLK_SET_RATE_PARENT,
1263	.ops = &clk_branch2_ops,
1264	},
1265	},
1266	};
1267
1268	static struct clk_branch camss_cci_cci_ahb_clk = {
1269	.halt_reg = 0x3348,
1270	.clkr = {
1271	.enable_reg = 0x3348,
1272	.enable_mask = BIT(0),
1273	.hw.init = &(struct clk_init_data){
1274	.name = "camss_cci_cci_ahb_clk",
1275	.parent_hws = (const struct clk_hw*[]){
1276	&mmss_ahb_clk_src.clkr.hw
1277	},
1278	.num_parents = 1,
1279	.ops = &clk_branch2_ops,
1280	},
1281	},
1282	};
1283
1284	static struct clk_branch camss_cci_cci_clk = {
1285	.halt_reg = 0x3344,
1286	.clkr = {
1287	.enable_reg = 0x3344,
1288	.enable_mask = BIT(0),
1289	.hw.init = &(struct clk_init_data){
1290	.name = "camss_cci_cci_clk",
1291	.parent_hws = (const struct clk_hw*[]){
1292	&cci_clk_src.clkr.hw
1293	},
1294	.num_parents = 1,
1295	.flags = CLK_SET_RATE_PARENT,
1296	.ops = &clk_branch2_ops,
1297	},
1298	},
1299	};
1300
1301	static struct clk_branch camss_csi0_ahb_clk = {
1302	.halt_reg = 0x30bc,
1303	.clkr = {
1304	.enable_reg = 0x30bc,
1305	.enable_mask = BIT(0),
1306	.hw.init = &(struct clk_init_data){
1307	.name = "camss_csi0_ahb_clk",
1308	.parent_hws = (const struct clk_hw*[]){
1309	&mmss_ahb_clk_src.clkr.hw
1310	},
1311	.num_parents = 1,
1312	.ops = &clk_branch2_ops,
1313	},
1314	},
1315	};
1316
1317	static struct clk_branch camss_csi0_clk = {
1318	.halt_reg = 0x30b4,
1319	.clkr = {
1320	.enable_reg = 0x30b4,
1321	.enable_mask = BIT(0),
1322	.hw.init = &(struct clk_init_data){
1323	.name = "camss_csi0_clk",
1324	.parent_hws = (const struct clk_hw*[]){
1325	&csi0_clk_src.clkr.hw
1326	},
1327	.num_parents = 1,
1328	.flags = CLK_SET_RATE_PARENT,
1329	.ops = &clk_branch2_ops,
1330	},
1331	},
1332	};
1333
1334	static struct clk_branch camss_csi0phy_clk = {
1335	.halt_reg = 0x30c4,
1336	.clkr = {
1337	.enable_reg = 0x30c4,
1338	.enable_mask = BIT(0),
1339	.hw.init = &(struct clk_init_data){
1340	.name = "camss_csi0phy_clk",
1341	.parent_hws = (const struct clk_hw*[]){
1342	&csi0_clk_src.clkr.hw
1343	},
1344	.num_parents = 1,
1345	.flags = CLK_SET_RATE_PARENT,
1346	.ops = &clk_branch2_ops,
1347	},
1348	},
1349	};
1350
1351	static struct clk_branch camss_csi0pix_clk = {
1352	.halt_reg = 0x30e4,
1353	.clkr = {
1354	.enable_reg = 0x30e4,
1355	.enable_mask = BIT(0),
1356	.hw.init = &(struct clk_init_data){
1357	.name = "camss_csi0pix_clk",
1358	.parent_hws = (const struct clk_hw*[]){
1359	&csi0_clk_src.clkr.hw
1360	},
1361	.num_parents = 1,
1362	.flags = CLK_SET_RATE_PARENT,
1363	.ops = &clk_branch2_ops,
1364	},
1365	},
1366	};
1367
1368	static struct clk_branch camss_csi0rdi_clk = {
1369	.halt_reg = 0x30d4,
1370	.clkr = {
1371	.enable_reg = 0x30d4,
1372	.enable_mask = BIT(0),
1373	.hw.init = &(struct clk_init_data){
1374	.name = "camss_csi0rdi_clk",
1375	.parent_hws = (const struct clk_hw*[]){
1376	&csi0_clk_src.clkr.hw
1377	},
1378	.num_parents = 1,
1379	.flags = CLK_SET_RATE_PARENT,
1380	.ops = &clk_branch2_ops,
1381	},
1382	},
1383	};
1384
1385	static struct clk_branch camss_csi1_ahb_clk = {
1386	.halt_reg = 0x3128,
1387	.clkr = {
1388	.enable_reg = 0x3128,
1389	.enable_mask = BIT(0),
1390	.hw.init = &(struct clk_init_data){
1391	.name = "camss_csi1_ahb_clk",
1392	.parent_hws = (const struct clk_hw*[]){
1393	&mmss_ahb_clk_src.clkr.hw
1394	},
1395	.num_parents = 1,
1396	.flags = CLK_SET_RATE_PARENT,
1397	.ops = &clk_branch2_ops,
1398	},
1399	},
1400	};
1401
1402	static struct clk_branch camss_csi1_clk = {
1403	.halt_reg = 0x3124,
1404	.clkr = {
1405	.enable_reg = 0x3124,
1406	.enable_mask = BIT(0),
1407	.hw.init = &(struct clk_init_data){
1408	.name = "camss_csi1_clk",
1409	.parent_hws = (const struct clk_hw*[]){
1410	&csi1_clk_src.clkr.hw
1411	},
1412	.num_parents = 1,
1413	.flags = CLK_SET_RATE_PARENT,
1414	.ops = &clk_branch2_ops,
1415	},
1416	},
1417	};
1418
1419	static struct clk_branch camss_csi1phy_clk = {
1420	.halt_reg = 0x3134,
1421	.clkr = {
1422	.enable_reg = 0x3134,
1423	.enable_mask = BIT(0),
1424	.hw.init = &(struct clk_init_data){
1425	.name = "camss_csi1phy_clk",
1426	.parent_hws = (const struct clk_hw*[]){
1427	&csi1_clk_src.clkr.hw
1428	},
1429	.num_parents = 1,
1430	.flags = CLK_SET_RATE_PARENT,
1431	.ops = &clk_branch2_ops,
1432	},
1433	},
1434	};
1435
1436	static struct clk_branch camss_csi1pix_clk = {
1437	.halt_reg = 0x3154,
1438	.clkr = {
1439	.enable_reg = 0x3154,
1440	.enable_mask = BIT(0),
1441	.hw.init = &(struct clk_init_data){
1442	.name = "camss_csi1pix_clk",
1443	.parent_hws = (const struct clk_hw*[]){
1444	&csi1_clk_src.clkr.hw
1445	},
1446	.num_parents = 1,
1447	.flags = CLK_SET_RATE_PARENT,
1448	.ops = &clk_branch2_ops,
1449	},
1450	},
1451	};
1452
1453	static struct clk_branch camss_csi1rdi_clk = {
1454	.halt_reg = 0x3144,
1455	.clkr = {
1456	.enable_reg = 0x3144,
1457	.enable_mask = BIT(0),
1458	.hw.init = &(struct clk_init_data){
1459	.name = "camss_csi1rdi_clk",
1460	.parent_hws = (const struct clk_hw*[]){
1461	&csi1_clk_src.clkr.hw
1462	},
1463	.num_parents = 1,
1464	.flags = CLK_SET_RATE_PARENT,
1465	.ops = &clk_branch2_ops,
1466	},
1467	},
1468	};
1469
1470	static struct clk_branch camss_csi2_ahb_clk = {
1471	.halt_reg = 0x3188,
1472	.clkr = {
1473	.enable_reg = 0x3188,
1474	.enable_mask = BIT(0),
1475	.hw.init = &(struct clk_init_data){
1476	.name = "camss_csi2_ahb_clk",
1477	.parent_hws = (const struct clk_hw*[]){
1478	&mmss_ahb_clk_src.clkr.hw
1479	},
1480	.num_parents = 1,
1481	.ops = &clk_branch2_ops,
1482	},
1483	},
1484	};
1485
1486	static struct clk_branch camss_csi2_clk = {
1487	.halt_reg = 0x3184,
1488	.clkr = {
1489	.enable_reg = 0x3184,
1490	.enable_mask = BIT(0),
1491	.hw.init = &(struct clk_init_data){
1492	.name = "camss_csi2_clk",
1493	.parent_hws = (const struct clk_hw*[]){
1494	&csi2_clk_src.clkr.hw
1495	},
1496	.num_parents = 1,
1497	.flags = CLK_SET_RATE_PARENT,
1498	.ops = &clk_branch2_ops,
1499	},
1500	},
1501	};
1502
1503	static struct clk_branch camss_csi2phy_clk = {
1504	.halt_reg = 0x3194,
1505	.clkr = {
1506	.enable_reg = 0x3194,
1507	.enable_mask = BIT(0),
1508	.hw.init = &(struct clk_init_data){
1509	.name = "camss_csi2phy_clk",
1510	.parent_hws = (const struct clk_hw*[]){
1511	&csi2_clk_src.clkr.hw
1512	},
1513	.num_parents = 1,
1514	.flags = CLK_SET_RATE_PARENT,
1515	.ops = &clk_branch2_ops,
1516	},
1517	},
1518	};
1519
1520	static struct clk_branch camss_csi2pix_clk = {
1521	.halt_reg = 0x31b4,
1522	.clkr = {
1523	.enable_reg = 0x31b4,
1524	.enable_mask = BIT(0),
1525	.hw.init = &(struct clk_init_data){
1526	.name = "camss_csi2pix_clk",
1527	.parent_hws = (const struct clk_hw*[]){
1528	&csi2_clk_src.clkr.hw
1529	},
1530	.num_parents = 1,
1531	.flags = CLK_SET_RATE_PARENT,
1532	.ops = &clk_branch2_ops,
1533	},
1534	},
1535	};
1536
1537	static struct clk_branch camss_csi2rdi_clk = {
1538	.halt_reg = 0x31a4,
1539	.clkr = {
1540	.enable_reg = 0x31a4,
1541	.enable_mask = BIT(0),
1542	.hw.init = &(struct clk_init_data){
1543	.name = "camss_csi2rdi_clk",
1544	.parent_hws = (const struct clk_hw*[]){
1545	&csi2_clk_src.clkr.hw
1546	},
1547	.num_parents = 1,
1548	.flags = CLK_SET_RATE_PARENT,
1549	.ops = &clk_branch2_ops,
1550	},
1551	},
1552	};
1553
1554	static struct clk_branch camss_csi3_ahb_clk = {
1555	.halt_reg = 0x31e8,
1556	.clkr = {
1557	.enable_reg = 0x31e8,
1558	.enable_mask = BIT(0),
1559	.hw.init = &(struct clk_init_data){
1560	.name = "camss_csi3_ahb_clk",
1561	.parent_hws = (const struct clk_hw*[]){
1562	&mmss_ahb_clk_src.clkr.hw
1563	},
1564	.num_parents = 1,
1565	.ops = &clk_branch2_ops,
1566	},
1567	},
1568	};
1569
1570	static struct clk_branch camss_csi3_clk = {
1571	.halt_reg = 0x31e4,
1572	.clkr = {
1573	.enable_reg = 0x31e4,
1574	.enable_mask = BIT(0),
1575	.hw.init = &(struct clk_init_data){
1576	.name = "camss_csi3_clk",
1577	.parent_hws = (const struct clk_hw*[]){
1578	&csi3_clk_src.clkr.hw
1579	},
1580	.num_parents = 1,
1581	.flags = CLK_SET_RATE_PARENT,
1582	.ops = &clk_branch2_ops,
1583	},
1584	},
1585	};
1586
1587	static struct clk_branch camss_csi3phy_clk = {
1588	.halt_reg = 0x31f4,
1589	.clkr = {
1590	.enable_reg = 0x31f4,
1591	.enable_mask = BIT(0),
1592	.hw.init = &(struct clk_init_data){
1593	.name = "camss_csi3phy_clk",
1594	.parent_hws = (const struct clk_hw*[]){
1595	&csi3_clk_src.clkr.hw
1596	},
1597	.num_parents = 1,
1598	.flags = CLK_SET_RATE_PARENT,
1599	.ops = &clk_branch2_ops,
1600	},
1601	},
1602	};
1603
1604	static struct clk_branch camss_csi3pix_clk = {
1605	.halt_reg = 0x3214,
1606	.clkr = {
1607	.enable_reg = 0x3214,
1608	.enable_mask = BIT(0),
1609	.hw.init = &(struct clk_init_data){
1610	.name = "camss_csi3pix_clk",
1611	.parent_hws = (const struct clk_hw*[]){
1612	&csi3_clk_src.clkr.hw
1613	},
1614	.num_parents = 1,
1615	.flags = CLK_SET_RATE_PARENT,
1616	.ops = &clk_branch2_ops,
1617	},
1618	},
1619	};
1620
1621	static struct clk_branch camss_csi3rdi_clk = {
1622	.halt_reg = 0x3204,
1623	.clkr = {
1624	.enable_reg = 0x3204,
1625	.enable_mask = BIT(0),
1626	.hw.init = &(struct clk_init_data){
1627	.name = "camss_csi3rdi_clk",
1628	.parent_hws = (const struct clk_hw*[]){
1629	&csi3_clk_src.clkr.hw
1630	},
1631	.num_parents = 1,
1632	.flags = CLK_SET_RATE_PARENT,
1633	.ops = &clk_branch2_ops,
1634	},
1635	},
1636	};
1637
1638	static struct clk_branch camss_csi_vfe0_clk = {
1639	.halt_reg = 0x3704,
1640	.clkr = {
1641	.enable_reg = 0x3704,
1642	.enable_mask = BIT(0),
1643	.hw.init = &(struct clk_init_data){
1644	.name = "camss_csi_vfe0_clk",
1645	.parent_hws = (const struct clk_hw*[]){
1646	&vfe0_clk_src.clkr.hw
1647	},
1648	.num_parents = 1,
1649	.flags = CLK_SET_RATE_PARENT,
1650	.ops = &clk_branch2_ops,
1651	},
1652	},
1653	};
1654
1655	static struct clk_branch camss_csi_vfe1_clk = {
1656	.halt_reg = 0x3714,
1657	.clkr = {
1658	.enable_reg = 0x3714,
1659	.enable_mask = BIT(0),
1660	.hw.init = &(struct clk_init_data){
1661	.name = "camss_csi_vfe1_clk",
1662	.parent_hws = (const struct clk_hw*[]){
1663	&vfe1_clk_src.clkr.hw
1664	},
1665	.num_parents = 1,
1666	.flags = CLK_SET_RATE_PARENT,
1667	.ops = &clk_branch2_ops,
1668	},
1669	},
1670	};
1671
1672	static struct clk_branch camss_gp0_clk = {
1673	.halt_reg = 0x3444,
1674	.clkr = {
1675	.enable_reg = 0x3444,
1676	.enable_mask = BIT(0),
1677	.hw.init = &(struct clk_init_data){
1678	.name = "camss_gp0_clk",
1679	.parent_hws = (const struct clk_hw*[]){
1680	&camss_gp0_clk_src.clkr.hw
1681	},
1682	.num_parents = 1,
1683	.flags = CLK_SET_RATE_PARENT,
1684	.ops = &clk_branch2_ops,
1685	},
1686	},
1687	};
1688
1689	static struct clk_branch camss_gp1_clk = {
1690	.halt_reg = 0x3474,
1691	.clkr = {
1692	.enable_reg = 0x3474,
1693	.enable_mask = BIT(0),
1694	.hw.init = &(struct clk_init_data){
1695	.name = "camss_gp1_clk",
1696	.parent_hws = (const struct clk_hw*[]){
1697	&camss_gp1_clk_src.clkr.hw
1698	},
1699	.num_parents = 1,
1700	.flags = CLK_SET_RATE_PARENT,
1701	.ops = &clk_branch2_ops,
1702	},
1703	},
1704	};
1705
1706	static struct clk_branch camss_ispif_ahb_clk = {
1707	.halt_reg = 0x3224,
1708	.clkr = {
1709	.enable_reg = 0x3224,
1710	.enable_mask = BIT(0),
1711	.hw.init = &(struct clk_init_data){
1712	.name = "camss_ispif_ahb_clk",
1713	.parent_hws = (const struct clk_hw*[]){
1714	&mmss_ahb_clk_src.clkr.hw
1715	},
1716	.num_parents = 1,
1717	.flags = CLK_SET_RATE_PARENT,
1718	.ops = &clk_branch2_ops,
1719	},
1720	},
1721	};
1722
1723	static struct clk_branch camss_jpeg_jpeg0_clk = {
1724	.halt_reg = 0x35a8,
1725	.clkr = {
1726	.enable_reg = 0x35a8,
1727	.enable_mask = BIT(0),
1728	.hw.init = &(struct clk_init_data){
1729	.name = "camss_jpeg_jpeg0_clk",
1730	.parent_hws = (const struct clk_hw*[]){
1731	&jpeg0_clk_src.clkr.hw
1732	},
1733	.num_parents = 1,
1734	.flags = CLK_SET_RATE_PARENT,
1735	.ops = &clk_branch2_ops,
1736	},
1737	},
1738	};
1739
1740	static struct clk_branch camss_jpeg_jpeg1_clk = {
1741	.halt_reg = 0x35ac,
1742	.clkr = {
1743	.enable_reg = 0x35ac,
1744	.enable_mask = BIT(0),
1745	.hw.init = &(struct clk_init_data){
1746	.name = "camss_jpeg_jpeg1_clk",
1747	.parent_hws = (const struct clk_hw*[]){
1748	&jpeg1_clk_src.clkr.hw
1749	},
1750	.num_parents = 1,
1751	.flags = CLK_SET_RATE_PARENT,
1752	.ops = &clk_branch2_ops,
1753	},
1754	},
1755	};
1756
1757	static struct clk_branch camss_jpeg_jpeg2_clk = {
1758	.halt_reg = 0x35b0,
1759	.clkr = {
1760	.enable_reg = 0x35b0,
1761	.enable_mask = BIT(0),
1762	.hw.init = &(struct clk_init_data){
1763	.name = "camss_jpeg_jpeg2_clk",
1764	.parent_hws = (const struct clk_hw*[]){
1765	&jpeg2_clk_src.clkr.hw
1766	},
1767	.num_parents = 1,
1768	.flags = CLK_SET_RATE_PARENT,
1769	.ops = &clk_branch2_ops,
1770	},
1771	},
1772	};
1773
1774	static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1775	.halt_reg = 0x35b4,
1776	.clkr = {
1777	.enable_reg = 0x35b4,
1778	.enable_mask = BIT(0),
1779	.hw.init = &(struct clk_init_data){
1780	.name = "camss_jpeg_jpeg_ahb_clk",
1781	.parent_hws = (const struct clk_hw*[]){
1782	&mmss_ahb_clk_src.clkr.hw
1783	},
1784	.num_parents = 1,
1785	.ops = &clk_branch2_ops,
1786	},
1787	},
1788	};
1789
1790	static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1791	.halt_reg = 0x35b8,
1792	.clkr = {
1793	.enable_reg = 0x35b8,
1794	.enable_mask = BIT(0),
1795	.hw.init = &(struct clk_init_data){
1796	.name = "camss_jpeg_jpeg_axi_clk",
1797	.parent_hws = (const struct clk_hw*[]){
1798	&mmss_axi_clk_src.clkr.hw
1799	},
1800	.num_parents = 1,
1801	.ops = &clk_branch2_ops,
1802	},
1803	},
1804	};
1805
1806	static struct clk_branch camss_mclk0_clk = {
1807	.halt_reg = 0x3384,
1808	.clkr = {
1809	.enable_reg = 0x3384,
1810	.enable_mask = BIT(0),
1811	.hw.init = &(struct clk_init_data){
1812	.name = "camss_mclk0_clk",
1813	.parent_hws = (const struct clk_hw*[]){
1814	&mclk0_clk_src.clkr.hw
1815	},
1816	.num_parents = 1,
1817	.flags = CLK_SET_RATE_PARENT,
1818	.ops = &clk_branch2_ops,
1819	},
1820	},
1821	};
1822
1823	static struct clk_branch camss_mclk1_clk = {
1824	.halt_reg = 0x33b4,
1825	.clkr = {
1826	.enable_reg = 0x33b4,
1827	.enable_mask = BIT(0),
1828	.hw.init = &(struct clk_init_data){
1829	.name = "camss_mclk1_clk",
1830	.parent_hws = (const struct clk_hw*[]){
1831	&mclk1_clk_src.clkr.hw
1832	},
1833	.num_parents = 1,
1834	.flags = CLK_SET_RATE_PARENT,
1835	.ops = &clk_branch2_ops,
1836	},
1837	},
1838	};
1839
1840	static struct clk_branch camss_mclk2_clk = {
1841	.halt_reg = 0x33e4,
1842	.clkr = {
1843	.enable_reg = 0x33e4,
1844	.enable_mask = BIT(0),
1845	.hw.init = &(struct clk_init_data){
1846	.name = "camss_mclk2_clk",
1847	.parent_hws = (const struct clk_hw*[]){
1848	&mclk2_clk_src.clkr.hw
1849	},
1850	.num_parents = 1,
1851	.flags = CLK_SET_RATE_PARENT,
1852	.ops = &clk_branch2_ops,
1853	},
1854	},
1855	};
1856
1857	static struct clk_branch camss_mclk3_clk = {
1858	.halt_reg = 0x3414,
1859	.clkr = {
1860	.enable_reg = 0x3414,
1861	.enable_mask = BIT(0),
1862	.hw.init = &(struct clk_init_data){
1863	.name = "camss_mclk3_clk",
1864	.parent_hws = (const struct clk_hw*[]){
1865	&mclk3_clk_src.clkr.hw
1866	},
1867	.num_parents = 1,
1868	.flags = CLK_SET_RATE_PARENT,
1869	.ops = &clk_branch2_ops,
1870	},
1871	},
1872	};
1873
1874	static struct clk_branch camss_micro_ahb_clk = {
1875	.halt_reg = 0x3494,
1876	.clkr = {
1877	.enable_reg = 0x3494,
1878	.enable_mask = BIT(0),
1879	.hw.init = &(struct clk_init_data){
1880	.name = "camss_micro_ahb_clk",
1881	.parent_hws = (const struct clk_hw*[]){
1882	&mmss_ahb_clk_src.clkr.hw
1883	},
1884	.num_parents = 1,
1885	.ops = &clk_branch2_ops,
1886	},
1887	},
1888	};
1889
1890	static struct clk_branch camss_phy0_csi0phytimer_clk = {
1891	.halt_reg = 0x3024,
1892	.clkr = {
1893	.enable_reg = 0x3024,
1894	.enable_mask = BIT(0),
1895	.hw.init = &(struct clk_init_data){
1896	.name = "camss_phy0_csi0phytimer_clk",
1897	.parent_hws = (const struct clk_hw*[]){
1898	&csi0phytimer_clk_src.clkr.hw
1899	},
1900	.num_parents = 1,
1901	.flags = CLK_SET_RATE_PARENT,
1902	.ops = &clk_branch2_ops,
1903	},
1904	},
1905	};
1906
1907	static struct clk_branch camss_phy1_csi1phytimer_clk = {
1908	.halt_reg = 0x3054,
1909	.clkr = {
1910	.enable_reg = 0x3054,
1911	.enable_mask = BIT(0),
1912	.hw.init = &(struct clk_init_data){
1913	.name = "camss_phy1_csi1phytimer_clk",
1914	.parent_hws = (const struct clk_hw*[]){
1915	&csi1phytimer_clk_src.clkr.hw
1916	},
1917	.num_parents = 1,
1918	.flags = CLK_SET_RATE_PARENT,
1919	.ops = &clk_branch2_ops,
1920	},
1921	},
1922	};
1923
1924	static struct clk_branch camss_phy2_csi2phytimer_clk = {
1925	.halt_reg = 0x3084,
1926	.clkr = {
1927	.enable_reg = 0x3084,
1928	.enable_mask = BIT(0),
1929	.hw.init = &(struct clk_init_data){
1930	.name = "camss_phy2_csi2phytimer_clk",
1931	.parent_hws = (const struct clk_hw*[]){
1932	&csi2phytimer_clk_src.clkr.hw
1933	},
1934	.num_parents = 1,
1935	.flags = CLK_SET_RATE_PARENT,
1936	.ops = &clk_branch2_ops,
1937	},
1938	},
1939	};
1940
1941	static struct clk_branch camss_top_ahb_clk = {
1942	.halt_reg = 0x3484,
1943	.clkr = {
1944	.enable_reg = 0x3484,
1945	.enable_mask = BIT(0),
1946	.hw.init = &(struct clk_init_data){
1947	.name = "camss_top_ahb_clk",
1948	.parent_hws = (const struct clk_hw*[]){
1949	&mmss_ahb_clk_src.clkr.hw
1950	},
1951	.num_parents = 1,
1952	.flags = CLK_SET_RATE_PARENT,
1953	.ops = &clk_branch2_ops,
1954	},
1955	},
1956	};
1957
1958	static struct clk_branch camss_vfe_cpp_ahb_clk = {
1959	.halt_reg = 0x36b4,
1960	.clkr = {
1961	.enable_reg = 0x36b4,
1962	.enable_mask = BIT(0),
1963	.hw.init = &(struct clk_init_data){
1964	.name = "camss_vfe_cpp_ahb_clk",
1965	.parent_hws = (const struct clk_hw*[]){
1966	&mmss_ahb_clk_src.clkr.hw
1967	},
1968	.num_parents = 1,
1969	.flags = CLK_SET_RATE_PARENT,
1970	.ops = &clk_branch2_ops,
1971	},
1972	},
1973	};
1974
1975	static struct clk_branch camss_vfe_cpp_clk = {
1976	.halt_reg = 0x36b0,
1977	.clkr = {
1978	.enable_reg = 0x36b0,
1979	.enable_mask = BIT(0),
1980	.hw.init = &(struct clk_init_data){
1981	.name = "camss_vfe_cpp_clk",
1982	.parent_hws = (const struct clk_hw*[]){
1983	&cpp_clk_src.clkr.hw
1984	},
1985	.num_parents = 1,
1986	.flags = CLK_SET_RATE_PARENT,
1987	.ops = &clk_branch2_ops,
1988	},
1989	},
1990	};
1991
1992	static struct clk_branch camss_vfe_vfe0_clk = {
1993	.halt_reg = 0x36a8,
1994	.clkr = {
1995	.enable_reg = 0x36a8,
1996	.enable_mask = BIT(0),
1997	.hw.init = &(struct clk_init_data){
1998	.name = "camss_vfe_vfe0_clk",
1999	.parent_hws = (const struct clk_hw*[]){
2000	&vfe0_clk_src.clkr.hw
2001	},
2002	.num_parents = 1,
2003	.flags = CLK_SET_RATE_PARENT,
2004	.ops = &clk_branch2_ops,
2005	},
2006	},
2007	};
2008
2009	static struct clk_branch camss_vfe_vfe1_clk = {
2010	.halt_reg = 0x36ac,
2011	.clkr = {
2012	.enable_reg = 0x36ac,
2013	.enable_mask = BIT(0),
2014	.hw.init = &(struct clk_init_data){
2015	.name = "camss_vfe_vfe1_clk",
2016	.parent_hws = (const struct clk_hw*[]){
2017	&vfe1_clk_src.clkr.hw
2018	},
2019	.num_parents = 1,
2020	.flags = CLK_SET_RATE_PARENT,
2021	.ops = &clk_branch2_ops,
2022	},
2023	},
2024	};
2025
2026	static struct clk_branch camss_vfe_vfe_ahb_clk = {
2027	.halt_reg = 0x36b8,
2028	.clkr = {
2029	.enable_reg = 0x36b8,
2030	.enable_mask = BIT(0),
2031	.hw.init = &(struct clk_init_data){
2032	.name = "camss_vfe_vfe_ahb_clk",
2033	.parent_hws = (const struct clk_hw*[]){
2034	&mmss_ahb_clk_src.clkr.hw
2035	},
2036	.num_parents = 1,
2037	.flags = CLK_SET_RATE_PARENT,
2038	.ops = &clk_branch2_ops,
2039	},
2040	},
2041	};
2042
2043	static struct clk_branch camss_vfe_vfe_axi_clk = {
2044	.halt_reg = 0x36bc,
2045	.clkr = {
2046	.enable_reg = 0x36bc,
2047	.enable_mask = BIT(0),
2048	.hw.init = &(struct clk_init_data){
2049	.name = "camss_vfe_vfe_axi_clk",
2050	.parent_hws = (const struct clk_hw*[]){
2051	&mmss_axi_clk_src.clkr.hw
2052	},
2053	.num_parents = 1,
2054	.flags = CLK_SET_RATE_PARENT,
2055	.ops = &clk_branch2_ops,
2056	},
2057	},
2058	};
2059
2060	static struct clk_branch mdss_ahb_clk = {
2061	.halt_reg = 0x2308,
2062	.clkr = {
2063	.enable_reg = 0x2308,
2064	.enable_mask = BIT(0),
2065	.hw.init = &(struct clk_init_data){
2066	.name = "mdss_ahb_clk",
2067	.parent_hws = (const struct clk_hw*[]){
2068	&mmss_ahb_clk_src.clkr.hw
2069	},
2070	.num_parents = 1,
2071	.flags = CLK_SET_RATE_PARENT,
2072	.ops = &clk_branch2_ops,
2073	},
2074	},
2075	};
2076
2077	static struct clk_branch mdss_axi_clk = {
2078	.halt_reg = 0x2310,
2079	.clkr = {
2080	.enable_reg = 0x2310,
2081	.enable_mask = BIT(0),
2082	.hw.init = &(struct clk_init_data){
2083	.name = "mdss_axi_clk",
2084	.parent_hws = (const struct clk_hw*[]){
2085	&mmss_axi_clk_src.clkr.hw
2086	},
2087	.num_parents = 1,
2088	.flags = CLK_SET_RATE_PARENT,
2089	.ops = &clk_branch2_ops,
2090	},
2091	},
2092	};
2093
2094	static struct clk_branch mdss_byte0_clk = {
2095	.halt_reg = 0x233c,
2096	.clkr = {
2097	.enable_reg = 0x233c,
2098	.enable_mask = BIT(0),
2099	.hw.init = &(struct clk_init_data){
2100	.name = "mdss_byte0_clk",
2101	.parent_hws = (const struct clk_hw*[]){
2102	&byte0_clk_src.clkr.hw
2103	},
2104	.num_parents = 1,
2105	.flags = CLK_SET_RATE_PARENT,
2106	.ops = &clk_branch2_ops,
2107	},
2108	},
2109	};
2110
2111	static struct clk_branch mdss_byte1_clk = {
2112	.halt_reg = 0x2340,
2113	.clkr = {
2114	.enable_reg = 0x2340,
2115	.enable_mask = BIT(0),
2116	.hw.init = &(struct clk_init_data){
2117	.name = "mdss_byte1_clk",
2118	.parent_hws = (const struct clk_hw*[]){
2119	&byte1_clk_src.clkr.hw
2120	},
2121	.num_parents = 1,
2122	.flags = CLK_SET_RATE_PARENT,
2123	.ops = &clk_branch2_ops,
2124	},
2125	},
2126	};
2127
2128	static struct clk_branch mdss_edpaux_clk = {
2129	.halt_reg = 0x2334,
2130	.clkr = {
2131	.enable_reg = 0x2334,
2132	.enable_mask = BIT(0),
2133	.hw.init = &(struct clk_init_data){
2134	.name = "mdss_edpaux_clk",
2135	.parent_hws = (const struct clk_hw*[]){
2136	&edpaux_clk_src.clkr.hw
2137	},
2138	.num_parents = 1,
2139	.flags = CLK_SET_RATE_PARENT,
2140	.ops = &clk_branch2_ops,
2141	},
2142	},
2143	};
2144
2145	static struct clk_branch mdss_edplink_clk = {
2146	.halt_reg = 0x2330,
2147	.clkr = {
2148	.enable_reg = 0x2330,
2149	.enable_mask = BIT(0),
2150	.hw.init = &(struct clk_init_data){
2151	.name = "mdss_edplink_clk",
2152	.parent_hws = (const struct clk_hw*[]){
2153	&edplink_clk_src.clkr.hw
2154	},
2155	.num_parents = 1,
2156	.flags = CLK_SET_RATE_PARENT,
2157	.ops = &clk_branch2_ops,
2158	},
2159	},
2160	};
2161
2162	static struct clk_branch mdss_edppixel_clk = {
2163	.halt_reg = 0x232c,
2164	.clkr = {
2165	.enable_reg = 0x232c,
2166	.enable_mask = BIT(0),
2167	.hw.init = &(struct clk_init_data){
2168	.name = "mdss_edppixel_clk",
2169	.parent_hws = (const struct clk_hw*[]){
2170	&edppixel_clk_src.clkr.hw
2171	},
2172	.num_parents = 1,
2173	.flags = CLK_SET_RATE_PARENT,
2174	.ops = &clk_branch2_ops,
2175	},
2176	},
2177	};
2178
2179	static struct clk_branch mdss_esc0_clk = {
2180	.halt_reg = 0x2344,
2181	.clkr = {
2182	.enable_reg = 0x2344,
2183	.enable_mask = BIT(0),
2184	.hw.init = &(struct clk_init_data){
2185	.name = "mdss_esc0_clk",
2186	.parent_hws = (const struct clk_hw*[]){
2187	&esc0_clk_src.clkr.hw
2188	},
2189	.num_parents = 1,
2190	.flags = CLK_SET_RATE_PARENT,
2191	.ops = &clk_branch2_ops,
2192	},
2193	},
2194	};
2195
2196	static struct clk_branch mdss_esc1_clk = {
2197	.halt_reg = 0x2348,
2198	.clkr = {
2199	.enable_reg = 0x2348,
2200	.enable_mask = BIT(0),
2201	.hw.init = &(struct clk_init_data){
2202	.name = "mdss_esc1_clk",
2203	.parent_hws = (const struct clk_hw*[]){
2204	&esc1_clk_src.clkr.hw
2205	},
2206	.num_parents = 1,
2207	.flags = CLK_SET_RATE_PARENT,
2208	.ops = &clk_branch2_ops,
2209	},
2210	},
2211	};
2212
2213	static struct clk_branch mdss_extpclk_clk = {
2214	.halt_reg = 0x2324,
2215	.clkr = {
2216	.enable_reg = 0x2324,
2217	.enable_mask = BIT(0),
2218	.hw.init = &(struct clk_init_data){
2219	.name = "mdss_extpclk_clk",
2220	.parent_hws = (const struct clk_hw*[]){
2221	&extpclk_clk_src.clkr.hw
2222	},
2223	.num_parents = 1,
2224	.flags = CLK_SET_RATE_PARENT,
2225	.ops = &clk_branch2_ops,
2226	},
2227	},
2228	};
2229
2230	static struct clk_branch mdss_hdmi_ahb_clk = {
2231	.halt_reg = 0x230c,
2232	.clkr = {
2233	.enable_reg = 0x230c,
2234	.enable_mask = BIT(0),
2235	.hw.init = &(struct clk_init_data){
2236	.name = "mdss_hdmi_ahb_clk",
2237	.parent_hws = (const struct clk_hw*[]){
2238	&mmss_ahb_clk_src.clkr.hw
2239	},
2240	.num_parents = 1,
2241	.flags = CLK_SET_RATE_PARENT,
2242	.ops = &clk_branch2_ops,
2243	},
2244	},
2245	};
2246
2247	static struct clk_branch mdss_hdmi_clk = {
2248	.halt_reg = 0x2338,
2249	.clkr = {
2250	.enable_reg = 0x2338,
2251	.enable_mask = BIT(0),
2252	.hw.init = &(struct clk_init_data){
2253	.name = "mdss_hdmi_clk",
2254	.parent_hws = (const struct clk_hw*[]){
2255	&hdmi_clk_src.clkr.hw
2256	},
2257	.num_parents = 1,
2258	.flags = CLK_SET_RATE_PARENT,
2259	.ops = &clk_branch2_ops,
2260	},
2261	},
2262	};
2263
2264	static struct clk_branch mdss_mdp_clk = {
2265	.halt_reg = 0x231c,
2266	.clkr = {
2267	.enable_reg = 0x231c,
2268	.enable_mask = BIT(0),
2269	.hw.init = &(struct clk_init_data){
2270	.name = "mdss_mdp_clk",
2271	.parent_hws = (const struct clk_hw*[]){
2272	&mdp_clk_src.clkr.hw
2273	},
2274	.num_parents = 1,
2275	.flags = CLK_SET_RATE_PARENT,
2276	.ops = &clk_branch2_ops,
2277	},
2278	},
2279	};
2280
2281	static struct clk_branch mdss_mdp_lut_clk = {
2282	.halt_reg = 0x2320,
2283	.clkr = {
2284	.enable_reg = 0x2320,
2285	.enable_mask = BIT(0),
2286	.hw.init = &(struct clk_init_data){
2287	.name = "mdss_mdp_lut_clk",
2288	.parent_hws = (const struct clk_hw*[]){
2289	&mdp_clk_src.clkr.hw
2290	},
2291	.num_parents = 1,
2292	.flags = CLK_SET_RATE_PARENT,
2293	.ops = &clk_branch2_ops,
2294	},
2295	},
2296	};
2297
2298	static struct clk_branch mdss_pclk0_clk = {
2299	.halt_reg = 0x2314,
2300	.clkr = {
2301	.enable_reg = 0x2314,
2302	.enable_mask = BIT(0),
2303	.hw.init = &(struct clk_init_data){
2304	.name = "mdss_pclk0_clk",
2305	.parent_hws = (const struct clk_hw*[]){
2306	&pclk0_clk_src.clkr.hw
2307	},
2308	.num_parents = 1,
2309	.flags = CLK_SET_RATE_PARENT,
2310	.ops = &clk_branch2_ops,
2311	},
2312	},
2313	};
2314
2315	static struct clk_branch mdss_pclk1_clk = {
2316	.halt_reg = 0x2318,
2317	.clkr = {
2318	.enable_reg = 0x2318,
2319	.enable_mask = BIT(0),
2320	.hw.init = &(struct clk_init_data){
2321	.name = "mdss_pclk1_clk",
2322	.parent_hws = (const struct clk_hw*[]){
2323	&pclk1_clk_src.clkr.hw
2324	},
2325	.num_parents = 1,
2326	.flags = CLK_SET_RATE_PARENT,
2327	.ops = &clk_branch2_ops,
2328	},
2329	},
2330	};
2331
2332	static struct clk_branch mdss_vsync_clk = {
2333	.halt_reg = 0x2328,
2334	.clkr = {
2335	.enable_reg = 0x2328,
2336	.enable_mask = BIT(0),
2337	.hw.init = &(struct clk_init_data){
2338	.name = "mdss_vsync_clk",
2339	.parent_hws = (const struct clk_hw*[]){
2340	&vsync_clk_src.clkr.hw
2341	},
2342	.num_parents = 1,
2343	.flags = CLK_SET_RATE_PARENT,
2344	.ops = &clk_branch2_ops,
2345	},
2346	},
2347	};
2348
2349	static struct clk_branch mmss_rbcpr_ahb_clk = {
2350	.halt_reg = 0x4088,
2351	.clkr = {
2352	.enable_reg = 0x4088,
2353	.enable_mask = BIT(0),
2354	.hw.init = &(struct clk_init_data){
2355	.name = "mmss_rbcpr_ahb_clk",
2356	.parent_hws = (const struct clk_hw*[]){
2357	&mmss_ahb_clk_src.clkr.hw
2358	},
2359	.num_parents = 1,
2360	.flags = CLK_SET_RATE_PARENT,
2361	.ops = &clk_branch2_ops,
2362	},
2363	},
2364	};
2365
2366	static struct clk_branch mmss_rbcpr_clk = {
2367	.halt_reg = 0x4084,
2368	.clkr = {
2369	.enable_reg = 0x4084,
2370	.enable_mask = BIT(0),
2371	.hw.init = &(struct clk_init_data){
2372	.name = "mmss_rbcpr_clk",
2373	.parent_hws = (const struct clk_hw*[]){
2374	&rbcpr_clk_src.clkr.hw
2375	},
2376	.num_parents = 1,
2377	.flags = CLK_SET_RATE_PARENT,
2378	.ops = &clk_branch2_ops,
2379	},
2380	},
2381	};
2382
2383	static struct clk_branch mmss_misc_ahb_clk = {
2384	.halt_reg = 0x502c,
2385	.clkr = {
2386	.enable_reg = 0x502c,
2387	.enable_mask = BIT(0),
2388	.hw.init = &(struct clk_init_data){
2389	.name = "mmss_misc_ahb_clk",
2390	.parent_hws = (const struct clk_hw*[]){
2391	&mmss_ahb_clk_src.clkr.hw
2392	},
2393	.num_parents = 1,
2394	.flags = CLK_SET_RATE_PARENT,
2395	.ops = &clk_branch2_ops,
2396	},
2397	},
2398	};
2399
2400	static struct clk_branch mmss_mmssnoc_ahb_clk = {
2401	.halt_reg = 0x5024,
2402	.clkr = {
2403	.enable_reg = 0x5024,
2404	.enable_mask = BIT(0),
2405	.hw.init = &(struct clk_init_data){
2406	.name = "mmss_mmssnoc_ahb_clk",
2407	.parent_hws = (const struct clk_hw*[]){
2408	&mmss_ahb_clk_src.clkr.hw
2409	},
2410	.num_parents = 1,
2411	.ops = &clk_branch2_ops,
2412	.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2413	},
2414	},
2415	};
2416
2417	static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2418	.halt_reg = 0x5028,
2419	.clkr = {
2420	.enable_reg = 0x5028,
2421	.enable_mask = BIT(0),
2422	.hw.init = &(struct clk_init_data){
2423	.name = "mmss_mmssnoc_bto_ahb_clk",
2424	.parent_hws = (const struct clk_hw*[]){
2425	&mmss_ahb_clk_src.clkr.hw
2426	},
2427	.num_parents = 1,
2428	.ops = &clk_branch2_ops,
2429	.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2430	},
2431	},
2432	};
2433
2434	static struct clk_branch mmss_mmssnoc_axi_clk = {
2435	.halt_reg = 0x506c,
2436	.clkr = {
2437	.enable_reg = 0x506c,
2438	.enable_mask = BIT(0),
2439	.hw.init = &(struct clk_init_data){
2440	.name = "mmss_mmssnoc_axi_clk",
2441	.parent_hws = (const struct clk_hw*[]){
2442	&mmss_axi_clk_src.clkr.hw
2443	},
2444	.num_parents = 1,
2445	.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2446	.ops = &clk_branch2_ops,
2447	},
2448	},
2449	};
2450
2451	static struct clk_branch mmss_s0_axi_clk = {
2452	.halt_reg = 0x5064,
2453	.clkr = {
2454	.enable_reg = 0x5064,
2455	.enable_mask = BIT(0),
2456	.hw.init = &(struct clk_init_data){
2457	.name = "mmss_s0_axi_clk",
2458	.parent_hws = (const struct clk_hw*[]){
2459	&mmss_axi_clk_src.clkr.hw
2460	},
2461	.num_parents = 1,
2462	.ops = &clk_branch2_ops,
2463	.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2464	},
2465	},
2466	};
2467
2468	static struct clk_branch ocmemcx_ahb_clk = {
2469	.halt_reg = 0x405c,
2470	.clkr = {
2471	.enable_reg = 0x405c,
2472	.enable_mask = BIT(0),
2473	.hw.init = &(struct clk_init_data){
2474	.name = "ocmemcx_ahb_clk",
2475	.parent_hws = (const struct clk_hw*[]){
2476	&mmss_ahb_clk_src.clkr.hw
2477	},
2478	.num_parents = 1,
2479	.flags = CLK_SET_RATE_PARENT,
2480	.ops = &clk_branch2_ops,
2481	},
2482	},
2483	};
2484
2485	static struct clk_branch ocmemcx_ocmemnoc_clk = {
2486	.halt_reg = 0x4058,
2487	.clkr = {
2488	.enable_reg = 0x4058,
2489	.enable_mask = BIT(0),
2490	.hw.init = &(struct clk_init_data){
2491	.name = "ocmemcx_ocmemnoc_clk",
2492	.parent_hws = (const struct clk_hw*[]){
2493	&ocmemnoc_clk_src.clkr.hw
2494	},
2495	.num_parents = 1,
2496	.flags = CLK_SET_RATE_PARENT,
2497	.ops = &clk_branch2_ops,
2498	},
2499	},
2500	};
2501
2502	static struct clk_branch oxili_ocmemgx_clk = {
2503	.halt_reg = 0x402c,
2504	.clkr = {
2505	.enable_reg = 0x402c,
2506	.enable_mask = BIT(0),
2507	.hw.init = &(struct clk_init_data){
2508	.name = "oxili_ocmemgx_clk",
2509	.parent_hws = (const struct clk_hw*[]){
2510	&gfx3d_clk_src.clkr.hw
2511	},
2512	.num_parents = 1,
2513	.flags = CLK_SET_RATE_PARENT,
2514	.ops = &clk_branch2_ops,
2515	},
2516	},
2517	};
2518
2519	static struct clk_branch oxili_gfx3d_clk = {
2520	.halt_reg = 0x4028,
2521	.clkr = {
2522	.enable_reg = 0x4028,
2523	.enable_mask = BIT(0),
2524	.hw.init = &(struct clk_init_data){
2525	.name = "oxili_gfx3d_clk",
2526	.parent_hws = (const struct clk_hw*[]){
2527	&gfx3d_clk_src.clkr.hw
2528	},
2529	.num_parents = 1,
2530	.flags = CLK_SET_RATE_PARENT,
2531	.ops = &clk_branch2_ops,
2532	},
2533	},
2534	};
2535
2536	static struct clk_branch oxili_rbbmtimer_clk = {
2537	.halt_reg = 0x40b0,
2538	.clkr = {
2539	.enable_reg = 0x40b0,
2540	.enable_mask = BIT(0),
2541	.hw.init = &(struct clk_init_data){
2542	.name = "oxili_rbbmtimer_clk",
2543	.parent_hws = (const struct clk_hw*[]){
2544	&rbbmtimer_clk_src.clkr.hw
2545	},
2546	.num_parents = 1,
2547	.flags = CLK_SET_RATE_PARENT,
2548	.ops = &clk_branch2_ops,
2549	},
2550	},
2551	};
2552
2553	static struct clk_branch oxilicx_ahb_clk = {
2554	.halt_reg = 0x403c,
2555	.clkr = {
2556	.enable_reg = 0x403c,
2557	.enable_mask = BIT(0),
2558	.hw.init = &(struct clk_init_data){
2559	.name = "oxilicx_ahb_clk",
2560	.parent_hws = (const struct clk_hw*[]){
2561	&mmss_ahb_clk_src.clkr.hw
2562	},
2563	.num_parents = 1,
2564	.flags = CLK_SET_RATE_PARENT,
2565	.ops = &clk_branch2_ops,
2566	},
2567	},
2568	};
2569
2570	static struct clk_branch venus0_ahb_clk = {
2571	.halt_reg = 0x1030,
2572	.clkr = {
2573	.enable_reg = 0x1030,
2574	.enable_mask = BIT(0),
2575	.hw.init = &(struct clk_init_data){
2576	.name = "venus0_ahb_clk",
2577	.parent_hws = (const struct clk_hw*[]){
2578	&mmss_ahb_clk_src.clkr.hw
2579	},
2580	.num_parents = 1,
2581	.flags = CLK_SET_RATE_PARENT,
2582	.ops = &clk_branch2_ops,
2583	},
2584	},
2585	};
2586
2587	static struct clk_branch venus0_axi_clk = {
2588	.halt_reg = 0x1034,
2589	.clkr = {
2590	.enable_reg = 0x1034,
2591	.enable_mask = BIT(0),
2592	.hw.init = &(struct clk_init_data){
2593	.name = "venus0_axi_clk",
2594	.parent_hws = (const struct clk_hw*[]){
2595	&mmss_axi_clk_src.clkr.hw
2596	},
2597	.num_parents = 1,
2598	.flags = CLK_SET_RATE_PARENT,
2599	.ops = &clk_branch2_ops,
2600	},
2601	},
2602	};
2603
2604	static struct clk_branch venus0_core0_vcodec_clk = {
2605	.halt_reg = 0x1048,
2606	.clkr = {
2607	.enable_reg = 0x1048,
2608	.enable_mask = BIT(0),
2609	.hw.init = &(struct clk_init_data){
2610	.name = "venus0_core0_vcodec_clk",
2611	.parent_hws = (const struct clk_hw*[]){
2612	&vcodec0_clk_src.clkr.hw
2613	},
2614	.num_parents = 1,
2615	.flags = CLK_SET_RATE_PARENT,
2616	.ops = &clk_branch2_ops,
2617	},
2618	},
2619	};
2620
2621	static struct clk_branch venus0_core1_vcodec_clk = {
2622	.halt_reg = 0x104c,
2623	.clkr = {
2624	.enable_reg = 0x104c,
2625	.enable_mask = BIT(0),
2626	.hw.init = &(struct clk_init_data){
2627	.name = "venus0_core1_vcodec_clk",
2628	.parent_hws = (const struct clk_hw*[]){
2629	&vcodec0_clk_src.clkr.hw
2630	},
2631	.num_parents = 1,
2632	.flags = CLK_SET_RATE_PARENT,
2633	.ops = &clk_branch2_ops,
2634	},
2635	},
2636	};
2637
2638	static struct clk_branch venus0_ocmemnoc_clk = {
2639	.halt_reg = 0x1038,
2640	.clkr = {
2641	.enable_reg = 0x1038,
2642	.enable_mask = BIT(0),
2643	.hw.init = &(struct clk_init_data){
2644	.name = "venus0_ocmemnoc_clk",
2645	.parent_hws = (const struct clk_hw*[]){
2646	&ocmemnoc_clk_src.clkr.hw
2647	},
2648	.num_parents = 1,
2649	.flags = CLK_SET_RATE_PARENT,
2650	.ops = &clk_branch2_ops,
2651	},
2652	},
2653	};
2654
2655	static struct clk_branch venus0_vcodec0_clk = {
2656	.halt_reg = 0x1028,
2657	.clkr = {
2658	.enable_reg = 0x1028,
2659	.enable_mask = BIT(0),
2660	.hw.init = &(struct clk_init_data){
2661	.name = "venus0_vcodec0_clk",
2662	.parent_hws = (const struct clk_hw*[]){
2663	&vcodec0_clk_src.clkr.hw
2664	},
2665	.num_parents = 1,
2666	.flags = CLK_SET_RATE_PARENT,
2667	.ops = &clk_branch2_ops,
2668	},
2669	},
2670	};
2671
2672	static struct clk_branch vpu_ahb_clk = {
2673	.halt_reg = 0x1430,
2674	.clkr = {
2675	.enable_reg = 0x1430,
2676	.enable_mask = BIT(0),
2677	.hw.init = &(struct clk_init_data){
2678	.name = "vpu_ahb_clk",
2679	.parent_hws = (const struct clk_hw*[]){
2680	&mmss_ahb_clk_src.clkr.hw
2681	},
2682	.num_parents = 1,
2683	.flags = CLK_SET_RATE_PARENT,
2684	.ops = &clk_branch2_ops,
2685	},
2686	},
2687	};
2688
2689	static struct clk_branch vpu_axi_clk = {
2690	.halt_reg = 0x143c,
2691	.clkr = {
2692	.enable_reg = 0x143c,
2693	.enable_mask = BIT(0),
2694	.hw.init = &(struct clk_init_data){
2695	.name = "vpu_axi_clk",
2696	.parent_hws = (const struct clk_hw*[]){
2697	&mmss_axi_clk_src.clkr.hw
2698	},
2699	.num_parents = 1,
2700	.flags = CLK_SET_RATE_PARENT,
2701	.ops = &clk_branch2_ops,
2702	},
2703	},
2704	};
2705
2706	static struct clk_branch vpu_bus_clk = {
2707	.halt_reg = 0x1440,
2708	.clkr = {
2709	.enable_reg = 0x1440,
2710	.enable_mask = BIT(0),
2711	.hw.init = &(struct clk_init_data){
2712	.name = "vpu_bus_clk",
2713	.parent_hws = (const struct clk_hw*[]){
2714	&vpu_bus_clk_src.clkr.hw
2715	},
2716	.num_parents = 1,
2717	.flags = CLK_SET_RATE_PARENT,
2718	.ops = &clk_branch2_ops,
2719	},
2720	},
2721	};
2722
2723	static struct clk_branch vpu_cxo_clk = {
2724	.halt_reg = 0x1434,
2725	.clkr = {
2726	.enable_reg = 0x1434,
2727	.enable_mask = BIT(0),
2728	.hw.init = &(struct clk_init_data){
2729	.name = "vpu_cxo_clk",
2730	.parent_data = (const struct clk_parent_data[]){
2731	{ .fw_name = "xo", .name = "xo_board" },
2732	},
2733	.num_parents = 1,
2734	.flags = CLK_SET_RATE_PARENT,
2735	.ops = &clk_branch2_ops,
2736	},
2737	},
2738	};
2739
2740	static struct clk_branch vpu_maple_clk = {
2741	.halt_reg = 0x142c,
2742	.clkr = {
2743	.enable_reg = 0x142c,
2744	.enable_mask = BIT(0),
2745	.hw.init = &(struct clk_init_data){
2746	.name = "vpu_maple_clk",
2747	.parent_hws = (const struct clk_hw*[]){
2748	&maple_clk_src.clkr.hw
2749	},
2750	.num_parents = 1,
2751	.flags = CLK_SET_RATE_PARENT,
2752	.ops = &clk_branch2_ops,
2753	},
2754	},
2755	};
2756
2757	static struct clk_branch vpu_sleep_clk = {
2758	.halt_reg = 0x1438,
2759	.clkr = {
2760	.enable_reg = 0x1438,
2761	.enable_mask = BIT(0),
2762	.hw.init = &(struct clk_init_data){
2763	.name = "vpu_sleep_clk",
2764	.parent_data = (const struct clk_parent_data[]){
2765	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
2766	},
2767	.num_parents = 1,
2768	.flags = CLK_SET_RATE_PARENT,
2769	.ops = &clk_branch2_ops,
2770	},
2771	},
2772	};
2773
2774	static struct clk_branch vpu_vdp_clk = {
2775	.halt_reg = 0x1428,
2776	.clkr = {
2777	.enable_reg = 0x1428,
2778	.enable_mask = BIT(0),
2779	.hw.init = &(struct clk_init_data){
2780	.name = "vpu_vdp_clk",
2781	.parent_hws = (const struct clk_hw*[]){
2782	&vdp_clk_src.clkr.hw
2783	},
2784	.num_parents = 1,
2785	.flags = CLK_SET_RATE_PARENT,
2786	.ops = &clk_branch2_ops,
2787	},
2788	},
2789	};
2790
2791	static const struct pll_config mmpll1_config = {
2792	.l = 60,
2793	.m = 25,
2794	.n = 32,
2795	.vco_val = 0x0,
2796	.vco_mask = 0x3 << 20,
2797	.pre_div_val = 0x0,
2798	.pre_div_mask = 0x7 << 12,
2799	.post_div_val = 0x0,
2800	.post_div_mask = 0x3 << 8,
2801	.mn_ena_mask = BIT(24),
2802	.main_output_mask = BIT(0),
2803	};
2804
2805	static const struct pll_config mmpll3_config = {
2806	.l = 48,
2807	.m = 7,
2808	.n = 16,
2809	.vco_val = 0x0,
2810	.vco_mask = 0x3 << 20,
2811	.pre_div_val = 0x0,
2812	.pre_div_mask = 0x7 << 12,
2813	.post_div_val = 0x0,
2814	.post_div_mask = 0x3 << 8,
2815	.mn_ena_mask = BIT(24),
2816	.main_output_mask = BIT(0),
2817	.aux_output_mask = BIT(1),
2818	};
2819
2820	static struct gdsc venus0_gdsc = {
2821	.gdscr = 0x1024,
2822	.pd = {
2823	.name = "venus0",
2824	},
2825	.pwrsts = PWRSTS_OFF_ON,
2826	};
2827
2828	static struct gdsc venus0_core0_gdsc = {
2829	.gdscr = 0x1040,
2830	.pd = {
2831	.name = "venus0_core0",
2832	},
2833	.pwrsts = PWRSTS_OFF_ON,
2834	};
2835
2836	static struct gdsc venus0_core1_gdsc = {
2837	.gdscr = 0x1044,
2838	.pd = {
2839	.name = "venus0_core1",
2840	},
2841	.pwrsts = PWRSTS_OFF_ON,
2842	};
2843
2844	static struct gdsc mdss_gdsc = {
2845	.gdscr = 0x2304,
2846	.cxcs = (unsigned int []){ 0x231c, 0x2320 },
2847	.cxc_count = 2,
2848	.pd = {
2849	.name = "mdss",
2850	},
2851	.pwrsts = PWRSTS_OFF_ON,
2852	};
2853
2854	static struct gdsc camss_jpeg_gdsc = {
2855	.gdscr = 0x35a4,
2856	.pd = {
2857	.name = "camss_jpeg",
2858	},
2859	.pwrsts = PWRSTS_OFF_ON,
2860	};
2861
2862	static struct gdsc camss_vfe_gdsc = {
2863	.gdscr = 0x36a4,
2864	.cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
2865	.cxc_count = 3,
2866	.pd = {
2867	.name = "camss_vfe",
2868	},
2869	.pwrsts = PWRSTS_OFF_ON,
2870	};
2871
2872	static struct gdsc oxili_gdsc = {
2873	.gdscr = 0x4024,
2874	.cxcs = (unsigned int []){ 0x4028 },
2875	.cxc_count = 1,
2876	.pd = {
2877	.name = "oxili",
2878	},
2879	.pwrsts = PWRSTS_OFF_ON,
2880	};
2881
2882	static struct gdsc oxilicx_gdsc = {
2883	.gdscr = 0x4034,
2884	.pd = {
2885	.name = "oxilicx",
2886	},
2887	.pwrsts = PWRSTS_OFF_ON,
2888	};
2889
2890	static struct clk_regmap *mmcc_apq8084_clocks[] = {
2891	[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2892	[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2893	[MMPLL0] = &mmpll0.clkr,
2894	[MMPLL0_VOTE] = &mmpll0_vote,
2895	[MMPLL1] = &mmpll1.clkr,
2896	[MMPLL1_VOTE] = &mmpll1_vote,
2897	[MMPLL2] = &mmpll2.clkr,
2898	[MMPLL3] = &mmpll3.clkr,
2899	[MMPLL4] = &mmpll4.clkr,
2900	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2901	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2902	[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2903	[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2904	[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2905	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2906	[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2907	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
2908	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2909	[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2910	[OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2911	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2912	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2913	[JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2914	[JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2915	[EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2916	[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2917	[VP_CLK_SRC] = &vp_clk_src.clkr,
2918	[CCI_CLK_SRC] = &cci_clk_src.clkr,
2919	[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2920	[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2921	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2922	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2923	[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2924	[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2925	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2926	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2927	[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2928	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
2929	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2930	[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2931	[EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2932	[EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2933	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2934	[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2935	[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2936	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2937	[MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
2938	[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2939	[MAPLE_CLK_SRC] = &maple_clk_src.clkr,
2940	[VDP_CLK_SRC] = &vdp_clk_src.clkr,
2941	[VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
2942	[MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
2943	[MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
2944	[AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
2945	[AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
2946	[AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
2947	[AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
2948	[AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
2949	[AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
2950	[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2951	[CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2952	[CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2953	[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2954	[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2955	[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2956	[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2957	[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2958	[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2959	[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2960	[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2961	[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2962	[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2963	[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2964	[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2965	[CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2966	[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2967	[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2968	[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2969	[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2970	[CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2971	[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2972	[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2973	[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2974	[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2975	[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2976	[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2977	[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2978	[CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2979	[CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2980	[CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2981	[CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2982	[CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2983	[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2984	[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2985	[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2986	[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2987	[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2988	[CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2989	[CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2990	[CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2991	[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2992	[CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2993	[CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2994	[CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2995	[CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2996	[CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2997	[CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2998	[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2999	[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3000	[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3001	[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3002	[MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3003	[MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3004	[MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3005	[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3006	[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3007	[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3008	[MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3009	[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3010	[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3011	[MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3012	[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3013	[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3014	[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3015	[MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3016	[MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3017	[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3018	[MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3019	[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3020	[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3021	[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3022	[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3023	[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3024	[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3025	[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3026	[OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3027	[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3028	[VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3029	[VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3030	[VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3031	[VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3032	[VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3033	[VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3034	[VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3035	[VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3036	[VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3037	[VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3038	[VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3039	[VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3040	[VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3041	};
3042
3043	static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3044	[MMSS_SPDM_RESET] = { 0x0200 },
3045	[MMSS_SPDM_RM_RESET] = { 0x0300 },
3046	[VENUS0_RESET] = { 0x1020 },
3047	[VPU_RESET] = { 0x1400 },
3048	[MDSS_RESET] = { 0x2300 },
3049	[AVSYNC_RESET] = { 0x2400 },
3050	[CAMSS_PHY0_RESET] = { 0x3020 },
3051	[CAMSS_PHY1_RESET] = { 0x3050 },
3052	[CAMSS_PHY2_RESET] = { 0x3080 },
3053	[CAMSS_CSI0_RESET] = { 0x30b0 },
3054	[CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3055	[CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3056	[CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3057	[CAMSS_CSI1_RESET] = { 0x3120 },
3058	[CAMSS_CSI1PHY_RESET] = { 0x3130 },
3059	[CAMSS_CSI1RDI_RESET] = { 0x3140 },
3060	[CAMSS_CSI1PIX_RESET] = { 0x3150 },
3061	[CAMSS_CSI2_RESET] = { 0x3180 },
3062	[CAMSS_CSI2PHY_RESET] = { 0x3190 },
3063	[CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3064	[CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3065	[CAMSS_CSI3_RESET] = { 0x31e0 },
3066	[CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3067	[CAMSS_CSI3RDI_RESET] = { 0x3200 },
3068	[CAMSS_CSI3PIX_RESET] = { 0x3210 },
3069	[CAMSS_ISPIF_RESET] = { 0x3220 },
3070	[CAMSS_CCI_RESET] = { 0x3340 },
3071	[CAMSS_MCLK0_RESET] = { 0x3380 },
3072	[CAMSS_MCLK1_RESET] = { 0x33b0 },
3073	[CAMSS_MCLK2_RESET] = { 0x33e0 },
3074	[CAMSS_MCLK3_RESET] = { 0x3410 },
3075	[CAMSS_GP0_RESET] = { 0x3440 },
3076	[CAMSS_GP1_RESET] = { 0x3470 },
3077	[CAMSS_TOP_RESET] = { 0x3480 },
3078	[CAMSS_AHB_RESET] = { 0x3488 },
3079	[CAMSS_MICRO_RESET] = { 0x3490 },
3080	[CAMSS_JPEG_RESET] = { 0x35a0 },
3081	[CAMSS_VFE_RESET] = { 0x36a0 },
3082	[CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3083	[CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3084	[OXILI_RESET] = { 0x4020 },
3085	[OXILICX_RESET] = { 0x4030 },
3086	[OCMEMCX_RESET] = { 0x4050 },
3087	[MMSS_RBCRP_RESET] = { 0x4080 },
3088	[MMSSNOCAHB_RESET] = { 0x5020 },
3089	[MMSSNOCAXI_RESET] = { 0x5060 },
3090	};
3091
3092	static struct gdsc *mmcc_apq8084_gdscs[] = {
3093	[VENUS0_GDSC] = &venus0_gdsc,
3094	[VENUS0_CORE0_GDSC] = &venus0_core0_gdsc,
3095	[VENUS0_CORE1_GDSC] = &venus0_core1_gdsc,
3096	[MDSS_GDSC] = &mdss_gdsc,
3097	[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
3098	[CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
3099	[OXILI_GDSC] = &oxili_gdsc,
3100	[OXILICX_GDSC] = &oxilicx_gdsc,
3101	};
3102
3103	static const struct regmap_config mmcc_apq8084_regmap_config = {
3104	.reg_bits = 32,
3105	.reg_stride = 4,
3106	.val_bits = 32,
3107	.max_register = 0x5104,
3108	.fast_io = true,
3109	};
3110
3111	static const struct qcom_cc_desc mmcc_apq8084_desc = {
3112	.config = &mmcc_apq8084_regmap_config,
3113	.clks = mmcc_apq8084_clocks,
3114	.num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3115	.resets = mmcc_apq8084_resets,
3116	.num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3117	.gdscs = mmcc_apq8084_gdscs,
3118	.num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
3119	};
3120
3121	static const struct of_device_id mmcc_apq8084_match_table[] = {
3122	{ .compatible = "qcom,mmcc-apq8084" },
3123	{ }
3124	};
3125	MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3126
3127	static int mmcc_apq8084_probe(struct platform_device *pdev)
3128	{
3129	int ret;
3130	struct regmap *regmap;
3131
3132	ret = qcom_cc_probe(pdev, desc: &mmcc_apq8084_desc);
3133	if (ret)
3134	return ret;
3135
3136	regmap = dev_get_regmap(dev: &pdev->dev, NULL);
3137	clk_pll_configure_sr_hpm_lp(pll: &mmpll1, regmap, config: &mmpll1_config, fsm_mode: true);
3138	clk_pll_configure_sr_hpm_lp(pll: &mmpll3, regmap, config: &mmpll3_config, fsm_mode: false);
3139
3140	return 0;
3141	}
3142
3143	static struct platform_driver mmcc_apq8084_driver = {
3144	.probe = mmcc_apq8084_probe,
3145	.driver = {
3146	.name = "mmcc-apq8084",
3147	.of_match_table = mmcc_apq8084_match_table,
3148	},
3149	};
3150	module_platform_driver(mmcc_apq8084_driver);
3151
3152	MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3153	MODULE_LICENSE("GPL v2");
3154	MODULE_ALIAS("platform:mmcc-apq8084");
3155