1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * r8a73a4 Core CPG Clocks |
4 | * |
5 | * Copyright (C) 2014 Ulrich Hecht |
6 | */ |
7 | |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/clk/renesas.h> |
10 | #include <linux/init.h> |
11 | #include <linux/io.h> |
12 | #include <linux/kernel.h> |
13 | #include <linux/slab.h> |
14 | #include <linux/of.h> |
15 | #include <linux/of_address.h> |
16 | #include <linux/spinlock.h> |
17 | |
18 | struct r8a73a4_cpg { |
19 | struct clk_onecell_data data; |
20 | spinlock_t lock; |
21 | }; |
22 | |
23 | #define CPG_CKSCR 0xc0 |
24 | #define CPG_FRQCRA 0x00 |
25 | #define CPG_FRQCRB 0x04 |
26 | #define CPG_FRQCRC 0xe0 |
27 | #define CPG_PLL0CR 0xd8 |
28 | #define CPG_PLL1CR 0x28 |
29 | #define CPG_PLL2CR 0x2c |
30 | #define CPG_PLL2HCR 0xe4 |
31 | #define CPG_PLL2SCR 0xf4 |
32 | |
33 | #define CLK_ENABLE_ON_INIT BIT(0) |
34 | |
35 | struct div4_clk { |
36 | const char *name; |
37 | unsigned int reg; |
38 | unsigned int shift; |
39 | }; |
40 | |
41 | static struct div4_clk div4_clks[] = { |
42 | { "i" , CPG_FRQCRA, 20 }, |
43 | { "m3" , CPG_FRQCRA, 12 }, |
44 | { "b" , CPG_FRQCRA, 8 }, |
45 | { "m1" , CPG_FRQCRA, 4 }, |
46 | { "m2" , CPG_FRQCRA, 0 }, |
47 | { "zx" , CPG_FRQCRB, 12 }, |
48 | { "zs" , CPG_FRQCRB, 8 }, |
49 | { "hp" , CPG_FRQCRB, 4 }, |
50 | { NULL, 0, 0 }, |
51 | }; |
52 | |
53 | static const struct clk_div_table div4_div_table[] = { |
54 | { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, |
55 | { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, |
56 | { 12, 10 }, { 0, 0 } |
57 | }; |
58 | |
59 | static struct clk * __init |
60 | r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, |
61 | void __iomem *base, const char *name) |
62 | { |
63 | const struct clk_div_table *table = NULL; |
64 | const char *parent_name; |
65 | unsigned int shift, reg; |
66 | unsigned int mult = 1; |
67 | unsigned int div = 1; |
68 | |
69 | |
70 | if (!strcmp(name, "main" )) { |
71 | u32 ckscr = readl(addr: base + CPG_CKSCR); |
72 | |
73 | switch ((ckscr >> 28) & 3) { |
74 | case 0: /* extal1 */ |
75 | parent_name = of_clk_get_parent_name(np, index: 0); |
76 | break; |
77 | case 1: /* extal1 / 2 */ |
78 | parent_name = of_clk_get_parent_name(np, index: 0); |
79 | div = 2; |
80 | break; |
81 | case 2: /* extal2 */ |
82 | parent_name = of_clk_get_parent_name(np, index: 1); |
83 | break; |
84 | case 3: /* extal2 / 2 */ |
85 | parent_name = of_clk_get_parent_name(np, index: 1); |
86 | div = 2; |
87 | break; |
88 | } |
89 | } else if (!strcmp(name, "pll0" )) { |
90 | /* PLL0/1 are configurable multiplier clocks. Register them as |
91 | * fixed factor clocks for now as there's no generic multiplier |
92 | * clock implementation and we currently have no need to change |
93 | * the multiplier value. |
94 | */ |
95 | u32 value = readl(addr: base + CPG_PLL0CR); |
96 | |
97 | parent_name = "main" ; |
98 | mult = ((value >> 24) & 0x7f) + 1; |
99 | if (value & BIT(20)) |
100 | div = 2; |
101 | } else if (!strcmp(name, "pll1" )) { |
102 | u32 value = readl(addr: base + CPG_PLL1CR); |
103 | |
104 | parent_name = "main" ; |
105 | /* XXX: enable bit? */ |
106 | mult = ((value >> 24) & 0x7f) + 1; |
107 | if (value & BIT(7)) |
108 | div = 2; |
109 | } else if (!strncmp(name, "pll2" , 4)) { |
110 | u32 value, cr; |
111 | |
112 | switch (name[4]) { |
113 | case 0: |
114 | cr = CPG_PLL2CR; |
115 | break; |
116 | case 's': |
117 | cr = CPG_PLL2SCR; |
118 | break; |
119 | case 'h': |
120 | cr = CPG_PLL2HCR; |
121 | break; |
122 | default: |
123 | return ERR_PTR(error: -EINVAL); |
124 | } |
125 | value = readl(addr: base + cr); |
126 | switch ((value >> 5) & 7) { |
127 | case 0: |
128 | parent_name = "main" ; |
129 | div = 2; |
130 | break; |
131 | case 1: |
132 | parent_name = "extal2" ; |
133 | div = 2; |
134 | break; |
135 | case 3: |
136 | parent_name = "extal2" ; |
137 | div = 4; |
138 | break; |
139 | case 4: |
140 | parent_name = "main" ; |
141 | break; |
142 | case 5: |
143 | parent_name = "extal2" ; |
144 | break; |
145 | default: |
146 | pr_warn("%s: unexpected parent of %s\n" , __func__, |
147 | name); |
148 | return ERR_PTR(error: -EINVAL); |
149 | } |
150 | /* XXX: enable bit? */ |
151 | mult = ((value >> 24) & 0x7f) + 1; |
152 | } else if (!strcmp(name, "z" ) || !strcmp(name, "z2" )) { |
153 | u32 shift = 8; |
154 | |
155 | parent_name = "pll0" ; |
156 | if (name[1] == '2') { |
157 | div = 2; |
158 | shift = 0; |
159 | } |
160 | div *= 32; |
161 | mult = 0x20 - ((readl(addr: base + CPG_FRQCRC) >> shift) & 0x1f); |
162 | } else { |
163 | struct div4_clk *c; |
164 | |
165 | for (c = div4_clks; c->name; c++) { |
166 | if (!strcmp(name, c->name)) |
167 | break; |
168 | } |
169 | if (!c->name) |
170 | return ERR_PTR(error: -EINVAL); |
171 | |
172 | parent_name = "pll1" ; |
173 | table = div4_div_table; |
174 | reg = c->reg; |
175 | shift = c->shift; |
176 | } |
177 | |
178 | if (!table) { |
179 | return clk_register_fixed_factor(NULL, name, parent_name, flags: 0, |
180 | mult, div); |
181 | } else { |
182 | return clk_register_divider_table(NULL, name, parent_name, flags: 0, |
183 | reg: base + reg, shift, width: 4, clk_divider_flags: 0, |
184 | table, lock: &cpg->lock); |
185 | } |
186 | } |
187 | |
188 | static void __init r8a73a4_cpg_clocks_init(struct device_node *np) |
189 | { |
190 | struct r8a73a4_cpg *cpg; |
191 | void __iomem *base; |
192 | struct clk **clks; |
193 | unsigned int i; |
194 | int num_clks; |
195 | |
196 | num_clks = of_property_count_strings(np, propname: "clock-output-names" ); |
197 | if (num_clks < 0) { |
198 | pr_err("%s: failed to count clocks\n" , __func__); |
199 | return; |
200 | } |
201 | |
202 | cpg = kzalloc(size: sizeof(*cpg), GFP_KERNEL); |
203 | clks = kcalloc(n: num_clks, size: sizeof(*clks), GFP_KERNEL); |
204 | if (cpg == NULL || clks == NULL) { |
205 | /* We're leaking memory on purpose, there's no point in cleaning |
206 | * up as the system won't boot anyway. |
207 | */ |
208 | return; |
209 | } |
210 | |
211 | spin_lock_init(&cpg->lock); |
212 | |
213 | cpg->data.clks = clks; |
214 | cpg->data.clk_num = num_clks; |
215 | |
216 | base = of_iomap(node: np, index: 0); |
217 | if (WARN_ON(base == NULL)) |
218 | return; |
219 | |
220 | for (i = 0; i < num_clks; ++i) { |
221 | const char *name; |
222 | struct clk *clk; |
223 | |
224 | of_property_read_string_index(np, propname: "clock-output-names" , index: i, |
225 | output: &name); |
226 | |
227 | clk = r8a73a4_cpg_register_clock(np, cpg, base, name); |
228 | if (IS_ERR(ptr: clk)) |
229 | pr_err("%s: failed to register %pOFn %s clock (%ld)\n" , |
230 | __func__, np, name, PTR_ERR(clk)); |
231 | else |
232 | cpg->data.clks[i] = clk; |
233 | } |
234 | |
235 | of_clk_add_provider(np, clk_src_get: of_clk_src_onecell_get, data: &cpg->data); |
236 | } |
237 | CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks" , |
238 | r8a73a4_cpg_clocks_init); |
239 | |