1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * r8a7740 Core CPG Clocks |
4 | * |
5 | * Copyright (C) 2014 Ulrich Hecht |
6 | */ |
7 | |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/clk/renesas.h> |
10 | #include <linux/init.h> |
11 | #include <linux/io.h> |
12 | #include <linux/kernel.h> |
13 | #include <linux/slab.h> |
14 | #include <linux/of.h> |
15 | #include <linux/of_address.h> |
16 | #include <linux/spinlock.h> |
17 | |
18 | struct r8a7740_cpg { |
19 | struct clk_onecell_data data; |
20 | spinlock_t lock; |
21 | }; |
22 | |
23 | #define CPG_FRQCRA 0x00 |
24 | #define CPG_FRQCRB 0x04 |
25 | #define CPG_PLLC2CR 0x2c |
26 | #define CPG_USBCKCR 0x8c |
27 | #define CPG_FRQCRC 0xe0 |
28 | |
29 | #define CLK_ENABLE_ON_INIT BIT(0) |
30 | |
31 | struct div4_clk { |
32 | const char *name; |
33 | unsigned int reg; |
34 | unsigned int shift; |
35 | int flags; |
36 | }; |
37 | |
38 | static struct div4_clk div4_clks[] = { |
39 | { "i" , CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT }, |
40 | { "zg" , CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT }, |
41 | { "b" , CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT }, |
42 | { "m1" , CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT }, |
43 | { "hp" , CPG_FRQCRB, 4, 0 }, |
44 | { "hpp" , CPG_FRQCRC, 20, 0 }, |
45 | { "usbp" , CPG_FRQCRC, 16, 0 }, |
46 | { "s" , CPG_FRQCRC, 12, 0 }, |
47 | { "zb" , CPG_FRQCRC, 8, 0 }, |
48 | { "m3" , CPG_FRQCRC, 4, 0 }, |
49 | { "cp" , CPG_FRQCRC, 0, 0 }, |
50 | { NULL, 0, 0, 0 }, |
51 | }; |
52 | |
53 | static const struct clk_div_table div4_div_table[] = { |
54 | { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, |
55 | { 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 }, |
56 | { 13, 72 }, { 14, 96 }, { 0, 0 } |
57 | }; |
58 | |
59 | static u32 cpg_mode __initdata; |
60 | |
61 | static struct clk * __init |
62 | r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, |
63 | void __iomem *base, const char *name) |
64 | { |
65 | const struct clk_div_table *table = NULL; |
66 | const char *parent_name; |
67 | unsigned int shift, reg; |
68 | unsigned int mult = 1; |
69 | unsigned int div = 1; |
70 | |
71 | if (!strcmp(name, "r" )) { |
72 | switch (cpg_mode & (BIT(2) | BIT(1))) { |
73 | case BIT(1) | BIT(2): |
74 | /* extal1 */ |
75 | parent_name = of_clk_get_parent_name(np, index: 0); |
76 | div = 2048; |
77 | break; |
78 | case BIT(2): |
79 | /* extal1 */ |
80 | parent_name = of_clk_get_parent_name(np, index: 0); |
81 | div = 1024; |
82 | break; |
83 | default: |
84 | /* extalr */ |
85 | parent_name = of_clk_get_parent_name(np, index: 2); |
86 | break; |
87 | } |
88 | } else if (!strcmp(name, "system" )) { |
89 | parent_name = of_clk_get_parent_name(np, index: 0); |
90 | if (cpg_mode & BIT(1)) |
91 | div = 2; |
92 | } else if (!strcmp(name, "pllc0" )) { |
93 | /* PLLC0/1 are configurable multiplier clocks. Register them as |
94 | * fixed factor clocks for now as there's no generic multiplier |
95 | * clock implementation and we currently have no need to change |
96 | * the multiplier value. |
97 | */ |
98 | u32 value = readl(addr: base + CPG_FRQCRC); |
99 | parent_name = "system" ; |
100 | mult = ((value >> 24) & 0x7f) + 1; |
101 | } else if (!strcmp(name, "pllc1" )) { |
102 | u32 value = readl(addr: base + CPG_FRQCRA); |
103 | parent_name = "system" ; |
104 | mult = ((value >> 24) & 0x7f) + 1; |
105 | div = 2; |
106 | } else if (!strcmp(name, "pllc2" )) { |
107 | u32 value = readl(addr: base + CPG_PLLC2CR); |
108 | parent_name = "system" ; |
109 | mult = ((value >> 24) & 0x3f) + 1; |
110 | } else if (!strcmp(name, "usb24s" )) { |
111 | u32 value = readl(addr: base + CPG_USBCKCR); |
112 | if (value & BIT(7)) |
113 | /* extal2 */ |
114 | parent_name = of_clk_get_parent_name(np, index: 1); |
115 | else |
116 | parent_name = "system" ; |
117 | if (!(value & BIT(6))) |
118 | div = 2; |
119 | } else { |
120 | struct div4_clk *c; |
121 | for (c = div4_clks; c->name; c++) { |
122 | if (!strcmp(name, c->name)) { |
123 | parent_name = "pllc1" ; |
124 | table = div4_div_table; |
125 | reg = c->reg; |
126 | shift = c->shift; |
127 | break; |
128 | } |
129 | } |
130 | if (!c->name) |
131 | return ERR_PTR(error: -EINVAL); |
132 | } |
133 | |
134 | if (!table) { |
135 | return clk_register_fixed_factor(NULL, name, parent_name, flags: 0, |
136 | mult, div); |
137 | } else { |
138 | return clk_register_divider_table(NULL, name, parent_name, flags: 0, |
139 | reg: base + reg, shift, width: 4, clk_divider_flags: 0, |
140 | table, lock: &cpg->lock); |
141 | } |
142 | } |
143 | |
144 | static void __init r8a7740_cpg_clocks_init(struct device_node *np) |
145 | { |
146 | struct r8a7740_cpg *cpg; |
147 | void __iomem *base; |
148 | struct clk **clks; |
149 | unsigned int i; |
150 | int num_clks; |
151 | |
152 | if (of_property_read_u32(np, propname: "renesas,mode" , out_value: &cpg_mode)) |
153 | pr_warn("%s: missing renesas,mode property\n" , __func__); |
154 | |
155 | num_clks = of_property_count_strings(np, propname: "clock-output-names" ); |
156 | if (num_clks < 0) { |
157 | pr_err("%s: failed to count clocks\n" , __func__); |
158 | return; |
159 | } |
160 | |
161 | cpg = kzalloc(size: sizeof(*cpg), GFP_KERNEL); |
162 | clks = kcalloc(n: num_clks, size: sizeof(*clks), GFP_KERNEL); |
163 | if (cpg == NULL || clks == NULL) { |
164 | /* We're leaking memory on purpose, there's no point in cleaning |
165 | * up as the system won't boot anyway. |
166 | */ |
167 | return; |
168 | } |
169 | |
170 | spin_lock_init(&cpg->lock); |
171 | |
172 | cpg->data.clks = clks; |
173 | cpg->data.clk_num = num_clks; |
174 | |
175 | base = of_iomap(node: np, index: 0); |
176 | if (WARN_ON(base == NULL)) |
177 | return; |
178 | |
179 | for (i = 0; i < num_clks; ++i) { |
180 | const char *name; |
181 | struct clk *clk; |
182 | |
183 | of_property_read_string_index(np, propname: "clock-output-names" , index: i, |
184 | output: &name); |
185 | |
186 | clk = r8a7740_cpg_register_clock(np, cpg, base, name); |
187 | if (IS_ERR(ptr: clk)) |
188 | pr_err("%s: failed to register %pOFn %s clock (%ld)\n" , |
189 | __func__, np, name, PTR_ERR(clk)); |
190 | else |
191 | cpg->data.clks[i] = clk; |
192 | } |
193 | |
194 | of_clk_add_provider(np, clk_src_get: of_clk_src_onecell_get, data: &cpg->data); |
195 | } |
196 | CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks" , |
197 | r8a7740_cpg_clocks_init); |
198 | |