1// SPDX-License-Identifier: GPL-2.0
2/*
3 * sh73a0 Core CPG Clocks
4 *
5 * Copyright (C) 2014 Ulrich Hecht
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/clk/renesas.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17
18struct sh73a0_cpg {
19 struct clk_onecell_data data;
20 spinlock_t lock;
21};
22
23#define CPG_FRQCRA 0x00
24#define CPG_FRQCRB 0x04
25#define CPG_SD0CKCR 0x74
26#define CPG_SD1CKCR 0x78
27#define CPG_SD2CKCR 0x7c
28#define CPG_PLLECR 0xd0
29#define CPG_PLL0CR 0xd8
30#define CPG_PLL1CR 0x28
31#define CPG_PLL2CR 0x2c
32#define CPG_PLL3CR 0xdc
33#define CPG_CKSCR 0xc0
34#define CPG_DSI0PHYCR 0x6c
35#define CPG_DSI1PHYCR 0x70
36
37#define CLK_ENABLE_ON_INIT BIT(0)
38
39struct div4_clk {
40 const char *name;
41 const char *parent;
42 unsigned int reg;
43 unsigned int shift;
44};
45
46static const struct div4_clk div4_clks[] = {
47 { "zg", "pll0", CPG_FRQCRA, 16 },
48 { "m3", "pll1", CPG_FRQCRA, 12 },
49 { "b", "pll1", CPG_FRQCRA, 8 },
50 { "m1", "pll1", CPG_FRQCRA, 4 },
51 { "m2", "pll1", CPG_FRQCRA, 0 },
52 { "zx", "pll1", CPG_FRQCRB, 12 },
53 { "hp", "pll1", CPG_FRQCRB, 4 },
54 { NULL, NULL, 0, 0 },
55};
56
57static const struct clk_div_table div4_div_table[] = {
58 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
59 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
60 { 12, 7 }, { 0, 0 }
61};
62
63static const struct clk_div_table z_div_table[] = {
64 /* ZSEL == 0 */
65 { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
66 { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },
67 { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },
68 /* ZSEL == 1 */
69 { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },
70 { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
71};
72
73static struct clk * __init
74sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
75 void __iomem *base, const char *name)
76{
77 const struct clk_div_table *table = NULL;
78 unsigned int shift, reg, width;
79 const char *parent_name = NULL;
80 unsigned int mult = 1;
81 unsigned int div = 1;
82
83 if (!strcmp(name, "main")) {
84 /* extal1, extal1_div2, extal2, extal2_div2 */
85 u32 parent_idx = (readl(addr: base + CPG_CKSCR) >> 28) & 3;
86
87 parent_name = of_clk_get_parent_name(np, index: parent_idx >> 1);
88 div = (parent_idx & 1) + 1;
89 } else if (!strncmp(name, "pll", 3)) {
90 void __iomem *enable_reg = base;
91 u32 enable_bit = name[3] - '0';
92
93 parent_name = "main";
94 switch (enable_bit) {
95 case 0:
96 enable_reg += CPG_PLL0CR;
97 break;
98 case 1:
99 enable_reg += CPG_PLL1CR;
100 break;
101 case 2:
102 enable_reg += CPG_PLL2CR;
103 break;
104 case 3:
105 enable_reg += CPG_PLL3CR;
106 break;
107 default:
108 return ERR_PTR(error: -EINVAL);
109 }
110 if (readl(addr: base + CPG_PLLECR) & BIT(enable_bit)) {
111 mult = ((readl(addr: enable_reg) >> 24) & 0x3f) + 1;
112 /* handle CFG bit for PLL1 and PLL2 */
113 if (enable_bit == 1 || enable_bit == 2)
114 if (readl(addr: enable_reg) & BIT(20))
115 mult *= 2;
116 }
117 } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
118 u32 phy_no = name[3] - '0';
119 void __iomem *dsi_reg = base +
120 (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
121
122 parent_name = phy_no ? "dsi1pck" : "dsi0pck";
123 mult = readl(addr: dsi_reg);
124 if (!(mult & 0x8000))
125 mult = 1;
126 else
127 mult = (mult & 0x3f) + 1;
128 } else if (!strcmp(name, "z")) {
129 parent_name = "pll0";
130 table = z_div_table;
131 reg = CPG_FRQCRB;
132 shift = 24;
133 width = 5;
134 } else {
135 const struct div4_clk *c;
136
137 for (c = div4_clks; c->name; c++) {
138 if (!strcmp(name, c->name)) {
139 parent_name = c->parent;
140 table = div4_div_table;
141 reg = c->reg;
142 shift = c->shift;
143 width = 4;
144 break;
145 }
146 }
147 if (!c->name)
148 return ERR_PTR(error: -EINVAL);
149 }
150
151 if (!table) {
152 return clk_register_fixed_factor(NULL, name, parent_name, flags: 0,
153 mult, div);
154 } else {
155 return clk_register_divider_table(NULL, name, parent_name, flags: 0,
156 reg: base + reg, shift, width, clk_divider_flags: 0,
157 table, lock: &cpg->lock);
158 }
159}
160
161static void __init sh73a0_cpg_clocks_init(struct device_node *np)
162{
163 struct sh73a0_cpg *cpg;
164 void __iomem *base;
165 struct clk **clks;
166 unsigned int i;
167 int num_clks;
168
169 num_clks = of_property_count_strings(np, propname: "clock-output-names");
170 if (num_clks < 0) {
171 pr_err("%s: failed to count clocks\n", __func__);
172 return;
173 }
174
175 cpg = kzalloc(size: sizeof(*cpg), GFP_KERNEL);
176 clks = kcalloc(n: num_clks, size: sizeof(*clks), GFP_KERNEL);
177 if (cpg == NULL || clks == NULL) {
178 /* We're leaking memory on purpose, there's no point in cleaning
179 * up as the system won't boot anyway.
180 */
181 return;
182 }
183
184 spin_lock_init(&cpg->lock);
185
186 cpg->data.clks = clks;
187 cpg->data.clk_num = num_clks;
188
189 base = of_iomap(node: np, index: 0);
190 if (WARN_ON(base == NULL))
191 return;
192
193 /* Set SDHI clocks to a known state */
194 writel(val: 0x108, addr: base + CPG_SD0CKCR);
195 writel(val: 0x108, addr: base + CPG_SD1CKCR);
196 writel(val: 0x108, addr: base + CPG_SD2CKCR);
197
198 for (i = 0; i < num_clks; ++i) {
199 const char *name;
200 struct clk *clk;
201
202 of_property_read_string_index(np, propname: "clock-output-names", index: i,
203 output: &name);
204
205 clk = sh73a0_cpg_register_clock(np, cpg, base, name);
206 if (IS_ERR(ptr: clk))
207 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
208 __func__, np, name, PTR_ERR(clk));
209 else
210 cpg->data.clks[i] = clk;
211 }
212
213 of_clk_add_provider(np, clk_src_get: of_clk_src_onecell_get, data: &cpg->data);
214}
215CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",
216 sh73a0_cpg_clocks_init);
217

source code of linux/drivers/clk/renesas/clk-sh73a0.c