1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * r8a77990 Clock Pulse Generator / Module Standby and Software Reset |
4 | * |
5 | * Copyright (C) 2018-2019 Renesas Electronics Corp. |
6 | * |
7 | * Based on r8a7795-cpg-mssr.c |
8 | * |
9 | * Copyright (C) 2015 Glider bvba |
10 | * Copyright (C) 2015 Renesas Electronics Corp. |
11 | */ |
12 | |
13 | #include <linux/device.h> |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> |
16 | #include <linux/soc/renesas/rcar-rst.h> |
17 | |
18 | #include <dt-bindings/clock/r8a77990-cpg-mssr.h> |
19 | |
20 | #include "renesas-cpg-mssr.h" |
21 | #include "rcar-gen3-cpg.h" |
22 | |
23 | enum clk_ids { |
24 | /* Core Clock Outputs exported to DT */ |
25 | LAST_DT_CORE_CLK = R8A77990_CLK_CPEX, |
26 | |
27 | /* External Input Clocks */ |
28 | CLK_EXTAL, |
29 | |
30 | /* Internal Core Clocks */ |
31 | CLK_MAIN, |
32 | CLK_PLL0, |
33 | CLK_PLL1, |
34 | CLK_PLL3, |
35 | CLK_PLL0D4, |
36 | CLK_PLL0D6, |
37 | CLK_PLL0D8, |
38 | CLK_PLL0D20, |
39 | CLK_PLL0D24, |
40 | CLK_PLL1D2, |
41 | CLK_PE, |
42 | CLK_S0, |
43 | CLK_S1, |
44 | CLK_S2, |
45 | CLK_S3, |
46 | CLK_SDSRC, |
47 | CLK_RPCSRC, |
48 | CLK_RINT, |
49 | CLK_OCO, |
50 | |
51 | /* Module Clocks */ |
52 | MOD_CLK_BASE |
53 | }; |
54 | |
55 | static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { |
56 | /* External Clock Inputs */ |
57 | DEF_INPUT("extal" , CLK_EXTAL), |
58 | |
59 | /* Internal Core Clocks */ |
60 | DEF_BASE(".main" , CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), |
61 | DEF_BASE(".pll1" , CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), |
62 | DEF_BASE(".pll3" , CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), |
63 | |
64 | DEF_FIXED(".pll0" , CLK_PLL0, CLK_MAIN, 1, 100), |
65 | DEF_FIXED(".pll0d4" , CLK_PLL0D4, CLK_PLL0, 4, 1), |
66 | DEF_FIXED(".pll0d6" , CLK_PLL0D6, CLK_PLL0, 6, 1), |
67 | DEF_FIXED(".pll0d8" , CLK_PLL0D8, CLK_PLL0, 8, 1), |
68 | DEF_FIXED(".pll0d20" , CLK_PLL0D20, CLK_PLL0, 20, 1), |
69 | DEF_FIXED(".pll0d24" , CLK_PLL0D24, CLK_PLL0, 24, 1), |
70 | DEF_FIXED(".pll1d2" , CLK_PLL1D2, CLK_PLL1, 2, 1), |
71 | DEF_FIXED(".pe" , CLK_PE, CLK_PLL0D20, 1, 1), |
72 | DEF_FIXED(".s0" , CLK_S0, CLK_PLL1, 2, 1), |
73 | DEF_FIXED(".s1" , CLK_S1, CLK_PLL1, 3, 1), |
74 | DEF_FIXED(".s2" , CLK_S2, CLK_PLL1, 4, 1), |
75 | DEF_FIXED(".s3" , CLK_S3, CLK_PLL1, 6, 1), |
76 | DEF_FIXED(".sdsrc" , CLK_SDSRC, CLK_PLL1, 2, 1), |
77 | |
78 | DEF_FIXED_RPCSRC_E3(".rpcsrc" , CLK_RPCSRC, CLK_PLL0, CLK_PLL1), |
79 | |
80 | DEF_DIV6_RO(".r" , CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), |
81 | |
82 | DEF_RATE(".oco" , CLK_OCO, 8 * 1000 * 1000), |
83 | |
84 | /* Core Clock Outputs */ |
85 | DEF_FIXED("za2" , R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), |
86 | DEF_FIXED("za8" , R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), |
87 | DEF_GEN3_Z("z2" , R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), |
88 | DEF_FIXED("ztr" , R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), |
89 | DEF_FIXED("zt" , R8A77990_CLK_ZT, CLK_PLL1, 4, 1), |
90 | DEF_FIXED("zx" , R8A77990_CLK_ZX, CLK_PLL1, 3, 1), |
91 | DEF_FIXED("s0d1" , R8A77990_CLK_S0D1, CLK_S0, 1, 1), |
92 | DEF_FIXED("s0d3" , R8A77990_CLK_S0D3, CLK_S0, 3, 1), |
93 | DEF_FIXED("s0d6" , R8A77990_CLK_S0D6, CLK_S0, 6, 1), |
94 | DEF_FIXED("s0d12" , R8A77990_CLK_S0D12, CLK_S0, 12, 1), |
95 | DEF_FIXED("s0d24" , R8A77990_CLK_S0D24, CLK_S0, 24, 1), |
96 | DEF_FIXED("s1d1" , R8A77990_CLK_S1D1, CLK_S1, 1, 1), |
97 | DEF_FIXED("s1d2" , R8A77990_CLK_S1D2, CLK_S1, 2, 1), |
98 | DEF_FIXED("s1d4" , R8A77990_CLK_S1D4, CLK_S1, 4, 1), |
99 | DEF_FIXED("s2d1" , R8A77990_CLK_S2D1, CLK_S2, 1, 1), |
100 | DEF_FIXED("s2d2" , R8A77990_CLK_S2D2, CLK_S2, 2, 1), |
101 | DEF_FIXED("s2d4" , R8A77990_CLK_S2D4, CLK_S2, 4, 1), |
102 | DEF_FIXED("s3d1" , R8A77990_CLK_S3D1, CLK_S3, 1, 1), |
103 | DEF_FIXED("s3d2" , R8A77990_CLK_S3D2, CLK_S3, 2, 1), |
104 | DEF_FIXED("s3d4" , R8A77990_CLK_S3D4, CLK_S3, 4, 1), |
105 | |
106 | DEF_GEN3_SDH("sd0h" , R8A77990_CLK_SD0H, CLK_SDSRC, 0x0074), |
107 | DEF_GEN3_SDH("sd1h" , R8A77990_CLK_SD1H, CLK_SDSRC, 0x0078), |
108 | DEF_GEN3_SDH("sd3h" , R8A77990_CLK_SD3H, CLK_SDSRC, 0x026c), |
109 | DEF_GEN3_SD("sd0" , R8A77990_CLK_SD0, R8A77990_CLK_SD0H, 0x0074), |
110 | DEF_GEN3_SD("sd1" , R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078), |
111 | DEF_GEN3_SD("sd3" , R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c), |
112 | |
113 | DEF_BASE("rpc" , R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), |
114 | DEF_BASE("rpcd2" , R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77990_CLK_RPC), |
115 | |
116 | DEF_FIXED("cl" , R8A77990_CLK_CL, CLK_PLL1, 48, 1), |
117 | DEF_FIXED("cr" , R8A77990_CLK_CR, CLK_PLL1D2, 2, 1), |
118 | DEF_FIXED("cp" , R8A77990_CLK_CP, CLK_EXTAL, 2, 1), |
119 | DEF_FIXED("cpex" , R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1), |
120 | |
121 | DEF_DIV6_RO("osc" , R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), |
122 | |
123 | DEF_GEN3_PE("s0d6c" , R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2), |
124 | DEF_GEN3_PE("s3d1c" , R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), |
125 | DEF_GEN3_PE("s3d2c" , R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), |
126 | DEF_GEN3_PE("s3d4c" , R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), |
127 | |
128 | DEF_DIV6P1("canfd" , R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244), |
129 | DEF_DIV6P1("csi0" , R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c), |
130 | DEF_DIV6P1("mso" , R8A77990_CLK_MSO, CLK_PLL1D2, 0x014), |
131 | |
132 | DEF_GEN3_RCKSEL("r" , R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4), |
133 | }; |
134 | |
135 | static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { |
136 | DEF_MOD("tmu4" , 121, R8A77990_CLK_S0D6C), |
137 | DEF_MOD("tmu3" , 122, R8A77990_CLK_S3D2C), |
138 | DEF_MOD("tmu2" , 123, R8A77990_CLK_S3D2C), |
139 | DEF_MOD("tmu1" , 124, R8A77990_CLK_S3D2C), |
140 | DEF_MOD("tmu0" , 125, R8A77990_CLK_CP), |
141 | DEF_MOD("scif5" , 202, R8A77990_CLK_S3D4C), |
142 | DEF_MOD("scif4" , 203, R8A77990_CLK_S3D4C), |
143 | DEF_MOD("scif3" , 204, R8A77990_CLK_S3D4C), |
144 | DEF_MOD("scif1" , 206, R8A77990_CLK_S3D4C), |
145 | DEF_MOD("scif0" , 207, R8A77990_CLK_S3D4C), |
146 | DEF_MOD("msiof3" , 208, R8A77990_CLK_MSO), |
147 | DEF_MOD("msiof2" , 209, R8A77990_CLK_MSO), |
148 | DEF_MOD("msiof1" , 210, R8A77990_CLK_MSO), |
149 | DEF_MOD("msiof0" , 211, R8A77990_CLK_MSO), |
150 | DEF_MOD("sys-dmac2" , 217, R8A77990_CLK_S3D1), |
151 | DEF_MOD("sys-dmac1" , 218, R8A77990_CLK_S3D1), |
152 | DEF_MOD("sys-dmac0" , 219, R8A77990_CLK_S3D1), |
153 | DEF_MOD("sceg-pub" , 229, R8A77990_CLK_CR), |
154 | |
155 | DEF_MOD("cmt3" , 300, R8A77990_CLK_R), |
156 | DEF_MOD("cmt2" , 301, R8A77990_CLK_R), |
157 | DEF_MOD("cmt1" , 302, R8A77990_CLK_R), |
158 | DEF_MOD("cmt0" , 303, R8A77990_CLK_R), |
159 | DEF_MOD("scif2" , 310, R8A77990_CLK_S3D4C), |
160 | DEF_MOD("sdif3" , 311, R8A77990_CLK_SD3), |
161 | DEF_MOD("sdif1" , 313, R8A77990_CLK_SD1), |
162 | DEF_MOD("sdif0" , 314, R8A77990_CLK_SD0), |
163 | DEF_MOD("pcie0" , 319, R8A77990_CLK_S3D1), |
164 | DEF_MOD("usb3-if0" , 328, R8A77990_CLK_S3D1), |
165 | DEF_MOD("usb-dmac0" , 330, R8A77990_CLK_S3D1), |
166 | DEF_MOD("usb-dmac1" , 331, R8A77990_CLK_S3D1), |
167 | |
168 | DEF_MOD("rwdt" , 402, R8A77990_CLK_R), |
169 | DEF_MOD("intc-ex" , 407, R8A77990_CLK_CP), |
170 | DEF_MOD("intc-ap" , 408, R8A77990_CLK_S0D3), |
171 | |
172 | DEF_MOD("audmac0" , 502, R8A77990_CLK_S1D2), |
173 | DEF_MOD("drif31" , 508, R8A77990_CLK_S3D2), |
174 | DEF_MOD("drif30" , 509, R8A77990_CLK_S3D2), |
175 | DEF_MOD("drif21" , 510, R8A77990_CLK_S3D2), |
176 | DEF_MOD("drif20" , 511, R8A77990_CLK_S3D2), |
177 | DEF_MOD("drif11" , 512, R8A77990_CLK_S3D2), |
178 | DEF_MOD("drif10" , 513, R8A77990_CLK_S3D2), |
179 | DEF_MOD("drif01" , 514, R8A77990_CLK_S3D2), |
180 | DEF_MOD("drif00" , 515, R8A77990_CLK_S3D2), |
181 | DEF_MOD("hscif4" , 516, R8A77990_CLK_S3D1C), |
182 | DEF_MOD("hscif3" , 517, R8A77990_CLK_S3D1C), |
183 | DEF_MOD("hscif2" , 518, R8A77990_CLK_S3D1C), |
184 | DEF_MOD("hscif1" , 519, R8A77990_CLK_S3D1C), |
185 | DEF_MOD("hscif0" , 520, R8A77990_CLK_S3D1C), |
186 | DEF_MOD("thermal" , 522, R8A77990_CLK_CP), |
187 | DEF_MOD("pwm" , 523, R8A77990_CLK_S3D4C), |
188 | |
189 | DEF_MOD("fcpvd1" , 602, R8A77990_CLK_S1D2), |
190 | DEF_MOD("fcpvd0" , 603, R8A77990_CLK_S1D2), |
191 | DEF_MOD("fcpvb0" , 607, R8A77990_CLK_S0D1), |
192 | DEF_MOD("fcpvi0" , 611, R8A77990_CLK_S0D1), |
193 | DEF_MOD("fcpf0" , 615, R8A77990_CLK_S0D1), |
194 | DEF_MOD("fcpcs" , 619, R8A77990_CLK_S0D1), |
195 | DEF_MOD("vspd1" , 622, R8A77990_CLK_S1D2), |
196 | DEF_MOD("vspd0" , 623, R8A77990_CLK_S1D2), |
197 | DEF_MOD("vspb" , 626, R8A77990_CLK_S0D1), |
198 | DEF_MOD("vspi0" , 631, R8A77990_CLK_S0D1), |
199 | |
200 | DEF_MOD("ehci0" , 703, R8A77990_CLK_S3D2), |
201 | DEF_MOD("hsusb" , 704, R8A77990_CLK_S3D2), |
202 | DEF_MOD("cmm1" , 710, R8A77990_CLK_S1D1), |
203 | DEF_MOD("cmm0" , 711, R8A77990_CLK_S1D1), |
204 | DEF_MOD("csi40" , 716, R8A77990_CLK_CSI0), |
205 | DEF_MOD("du1" , 723, R8A77990_CLK_S1D1), |
206 | DEF_MOD("du0" , 724, R8A77990_CLK_S1D1), |
207 | DEF_MOD("lvds" , 727, R8A77990_CLK_S2D1), |
208 | |
209 | DEF_MOD("mlp" , 802, R8A77990_CLK_S2D1), |
210 | DEF_MOD("vin5" , 806, R8A77990_CLK_S1D2), |
211 | DEF_MOD("vin4" , 807, R8A77990_CLK_S1D2), |
212 | DEF_MOD("etheravb" , 812, R8A77990_CLK_S3D2), |
213 | |
214 | DEF_MOD("gpio6" , 906, R8A77990_CLK_S3D4), |
215 | DEF_MOD("gpio5" , 907, R8A77990_CLK_S3D4), |
216 | DEF_MOD("gpio4" , 908, R8A77990_CLK_S3D4), |
217 | DEF_MOD("gpio3" , 909, R8A77990_CLK_S3D4), |
218 | DEF_MOD("gpio2" , 910, R8A77990_CLK_S3D4), |
219 | DEF_MOD("gpio1" , 911, R8A77990_CLK_S3D4), |
220 | DEF_MOD("gpio0" , 912, R8A77990_CLK_S3D4), |
221 | DEF_MOD("can-fd" , 914, R8A77990_CLK_S3D2), |
222 | DEF_MOD("can-if1" , 915, R8A77990_CLK_S3D4), |
223 | DEF_MOD("can-if0" , 916, R8A77990_CLK_S3D4), |
224 | DEF_MOD("rpc-if" , 917, R8A77990_CLK_RPCD2), |
225 | DEF_MOD("i2c6" , 918, R8A77990_CLK_S3D2), |
226 | DEF_MOD("i2c5" , 919, R8A77990_CLK_S3D2), |
227 | DEF_MOD("adg" , 922, R8A77990_CLK_ZA2), |
228 | DEF_MOD("i2c-dvfs" , 926, R8A77990_CLK_CP), |
229 | DEF_MOD("i2c4" , 927, R8A77990_CLK_S3D2), |
230 | DEF_MOD("i2c3" , 928, R8A77990_CLK_S3D2), |
231 | DEF_MOD("i2c2" , 929, R8A77990_CLK_S3D2), |
232 | DEF_MOD("i2c1" , 930, R8A77990_CLK_S3D2), |
233 | DEF_MOD("i2c0" , 931, R8A77990_CLK_S3D2), |
234 | |
235 | DEF_MOD("i2c7" , 1003, R8A77990_CLK_S3D2), |
236 | DEF_MOD("ssi-all" , 1005, R8A77990_CLK_S3D4), |
237 | DEF_MOD("ssi9" , 1006, MOD_CLK_ID(1005)), |
238 | DEF_MOD("ssi8" , 1007, MOD_CLK_ID(1005)), |
239 | DEF_MOD("ssi7" , 1008, MOD_CLK_ID(1005)), |
240 | DEF_MOD("ssi6" , 1009, MOD_CLK_ID(1005)), |
241 | DEF_MOD("ssi5" , 1010, MOD_CLK_ID(1005)), |
242 | DEF_MOD("ssi4" , 1011, MOD_CLK_ID(1005)), |
243 | DEF_MOD("ssi3" , 1012, MOD_CLK_ID(1005)), |
244 | DEF_MOD("ssi2" , 1013, MOD_CLK_ID(1005)), |
245 | DEF_MOD("ssi1" , 1014, MOD_CLK_ID(1005)), |
246 | DEF_MOD("ssi0" , 1015, MOD_CLK_ID(1005)), |
247 | DEF_MOD("dab" , 1016, R8A77990_CLK_S3D1), |
248 | DEF_MOD("scu-all" , 1017, R8A77990_CLK_S3D4), |
249 | DEF_MOD("scu-dvc1" , 1018, MOD_CLK_ID(1017)), |
250 | DEF_MOD("scu-dvc0" , 1019, MOD_CLK_ID(1017)), |
251 | DEF_MOD("scu-ctu1-mix1" , 1020, MOD_CLK_ID(1017)), |
252 | DEF_MOD("scu-ctu0-mix0" , 1021, MOD_CLK_ID(1017)), |
253 | DEF_MOD("scu-src9" , 1022, MOD_CLK_ID(1017)), |
254 | DEF_MOD("scu-src8" , 1023, MOD_CLK_ID(1017)), |
255 | DEF_MOD("scu-src7" , 1024, MOD_CLK_ID(1017)), |
256 | DEF_MOD("scu-src6" , 1025, MOD_CLK_ID(1017)), |
257 | DEF_MOD("scu-src5" , 1026, MOD_CLK_ID(1017)), |
258 | DEF_MOD("scu-src4" , 1027, MOD_CLK_ID(1017)), |
259 | DEF_MOD("scu-src3" , 1028, MOD_CLK_ID(1017)), |
260 | DEF_MOD("scu-src2" , 1029, MOD_CLK_ID(1017)), |
261 | DEF_MOD("scu-src1" , 1030, MOD_CLK_ID(1017)), |
262 | DEF_MOD("scu-src0" , 1031, MOD_CLK_ID(1017)), |
263 | }; |
264 | |
265 | static const unsigned int r8a77990_crit_mod_clks[] __initconst = { |
266 | MOD_CLK_ID(402), /* RWDT */ |
267 | MOD_CLK_ID(408), /* INTC-AP (GIC) */ |
268 | }; |
269 | |
270 | /* |
271 | * CPG Clock Data |
272 | */ |
273 | |
274 | /* |
275 | * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 |
276 | *-------------------------------------------------------------------- |
277 | * 0 48 x 1 x100/1 x100/3 x100/3 |
278 | * 1 48 x 1 x100/1 x100/3 x58/3 |
279 | */ |
280 | #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) |
281 | |
282 | static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = { |
283 | /* EXTAL div PLL1 mult/div PLL3 mult/div */ |
284 | { 1, 100, 3, 100, 3, }, |
285 | { 1, 100, 3, 58, 3, }, |
286 | }; |
287 | |
288 | static int __init r8a77990_cpg_mssr_init(struct device *dev) |
289 | { |
290 | const struct rcar_gen3_cpg_pll_config *cpg_pll_config; |
291 | u32 cpg_mode; |
292 | int error; |
293 | |
294 | error = rcar_rst_read_mode_pins(mode: &cpg_mode); |
295 | if (error) |
296 | return error; |
297 | |
298 | cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; |
299 | |
300 | return rcar_gen3_cpg_init(config: cpg_pll_config, clk_extalr: 0, mode: cpg_mode); |
301 | } |
302 | |
303 | const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = { |
304 | /* Core Clocks */ |
305 | .core_clks = r8a77990_core_clks, |
306 | .num_core_clks = ARRAY_SIZE(r8a77990_core_clks), |
307 | .last_dt_core_clk = LAST_DT_CORE_CLK, |
308 | .num_total_core_clks = MOD_CLK_BASE, |
309 | |
310 | /* Module Clocks */ |
311 | .mod_clks = r8a77990_mod_clks, |
312 | .num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks), |
313 | .num_hw_mod_clks = 12 * 32, |
314 | |
315 | /* Critical Module Clocks */ |
316 | .crit_mod_clks = r8a77990_crit_mod_clks, |
317 | .num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks), |
318 | |
319 | /* Callbacks */ |
320 | .init = r8a77990_cpg_mssr_init, |
321 | .cpg_clk_register = rcar_gen3_cpg_clk_register, |
322 | }; |
323 | |