1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright (c) 2014 MundoReader S.L. |
4 | * Author: Heiko Stuebner <heiko@sntech.de> |
5 | */ |
6 | |
7 | #include <linux/clk.h> |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/io.h> |
10 | #include <linux/of.h> |
11 | #include <linux/of_address.h> |
12 | #include <dt-bindings/clock/rk3188-cru-common.h> |
13 | #include "clk.h" |
14 | |
15 | #define RK3066_GRF_SOC_STATUS 0x15c |
16 | #define RK3188_GRF_SOC_STATUS 0xac |
17 | |
18 | enum rk3188_plls { |
19 | apll, cpll, dpll, gpll, |
20 | }; |
21 | |
22 | static struct rockchip_pll_rate_table rk3188_pll_rates[] = { |
23 | RK3066_PLL_RATE(2208000000, 1, 92, 1), |
24 | RK3066_PLL_RATE(2184000000, 1, 91, 1), |
25 | RK3066_PLL_RATE(2160000000, 1, 90, 1), |
26 | RK3066_PLL_RATE(2136000000, 1, 89, 1), |
27 | RK3066_PLL_RATE(2112000000, 1, 88, 1), |
28 | RK3066_PLL_RATE(2088000000, 1, 87, 1), |
29 | RK3066_PLL_RATE(2064000000, 1, 86, 1), |
30 | RK3066_PLL_RATE(2040000000, 1, 85, 1), |
31 | RK3066_PLL_RATE(2016000000, 1, 84, 1), |
32 | RK3066_PLL_RATE(1992000000, 1, 83, 1), |
33 | RK3066_PLL_RATE(1968000000, 1, 82, 1), |
34 | RK3066_PLL_RATE(1944000000, 1, 81, 1), |
35 | RK3066_PLL_RATE(1920000000, 1, 80, 1), |
36 | RK3066_PLL_RATE(1896000000, 1, 79, 1), |
37 | RK3066_PLL_RATE(1872000000, 1, 78, 1), |
38 | RK3066_PLL_RATE(1848000000, 1, 77, 1), |
39 | RK3066_PLL_RATE(1824000000, 1, 76, 1), |
40 | RK3066_PLL_RATE(1800000000, 1, 75, 1), |
41 | RK3066_PLL_RATE(1776000000, 1, 74, 1), |
42 | RK3066_PLL_RATE(1752000000, 1, 73, 1), |
43 | RK3066_PLL_RATE(1728000000, 1, 72, 1), |
44 | RK3066_PLL_RATE(1704000000, 1, 71, 1), |
45 | RK3066_PLL_RATE(1680000000, 1, 70, 1), |
46 | RK3066_PLL_RATE(1656000000, 1, 69, 1), |
47 | RK3066_PLL_RATE(1632000000, 1, 68, 1), |
48 | RK3066_PLL_RATE(1608000000, 1, 67, 1), |
49 | RK3066_PLL_RATE(1560000000, 1, 65, 1), |
50 | RK3066_PLL_RATE(1512000000, 1, 63, 1), |
51 | RK3066_PLL_RATE(1488000000, 1, 62, 1), |
52 | RK3066_PLL_RATE(1464000000, 1, 61, 1), |
53 | RK3066_PLL_RATE(1440000000, 1, 60, 1), |
54 | RK3066_PLL_RATE(1416000000, 1, 59, 1), |
55 | RK3066_PLL_RATE(1392000000, 1, 58, 1), |
56 | RK3066_PLL_RATE(1368000000, 1, 57, 1), |
57 | RK3066_PLL_RATE(1344000000, 1, 56, 1), |
58 | RK3066_PLL_RATE(1320000000, 1, 55, 1), |
59 | RK3066_PLL_RATE(1296000000, 1, 54, 1), |
60 | RK3066_PLL_RATE(1272000000, 1, 53, 1), |
61 | RK3066_PLL_RATE(1248000000, 1, 52, 1), |
62 | RK3066_PLL_RATE(1224000000, 1, 51, 1), |
63 | RK3066_PLL_RATE(1200000000, 1, 50, 1), |
64 | RK3066_PLL_RATE(1188000000, 2, 99, 1), |
65 | RK3066_PLL_RATE(1176000000, 1, 49, 1), |
66 | RK3066_PLL_RATE(1128000000, 1, 47, 1), |
67 | RK3066_PLL_RATE(1104000000, 1, 46, 1), |
68 | RK3066_PLL_RATE(1008000000, 1, 84, 2), |
69 | RK3066_PLL_RATE( 912000000, 1, 76, 2), |
70 | RK3066_PLL_RATE( 891000000, 8, 594, 2), |
71 | RK3066_PLL_RATE( 888000000, 1, 74, 2), |
72 | RK3066_PLL_RATE( 816000000, 1, 68, 2), |
73 | RK3066_PLL_RATE( 798000000, 2, 133, 2), |
74 | RK3066_PLL_RATE( 792000000, 1, 66, 2), |
75 | RK3066_PLL_RATE( 768000000, 1, 64, 2), |
76 | RK3066_PLL_RATE( 742500000, 8, 495, 2), |
77 | RK3066_PLL_RATE( 696000000, 1, 58, 2), |
78 | RK3066_PLL_RATE( 600000000, 1, 50, 2), |
79 | RK3066_PLL_RATE( 594000000, 2, 198, 4), |
80 | RK3066_PLL_RATE( 552000000, 1, 46, 2), |
81 | RK3066_PLL_RATE( 504000000, 1, 84, 4), |
82 | RK3066_PLL_RATE( 456000000, 1, 76, 4), |
83 | RK3066_PLL_RATE( 408000000, 1, 68, 4), |
84 | RK3066_PLL_RATE( 400000000, 3, 100, 2), |
85 | RK3066_PLL_RATE( 384000000, 2, 128, 4), |
86 | RK3066_PLL_RATE( 360000000, 1, 60, 4), |
87 | RK3066_PLL_RATE( 312000000, 1, 52, 4), |
88 | RK3066_PLL_RATE( 300000000, 1, 50, 4), |
89 | RK3066_PLL_RATE( 297000000, 2, 198, 8), |
90 | RK3066_PLL_RATE( 252000000, 1, 84, 8), |
91 | RK3066_PLL_RATE( 216000000, 1, 72, 8), |
92 | RK3066_PLL_RATE( 148500000, 2, 99, 8), |
93 | RK3066_PLL_RATE( 126000000, 1, 84, 16), |
94 | RK3066_PLL_RATE( 48000000, 1, 64, 32), |
95 | { /* sentinel */ }, |
96 | }; |
97 | |
98 | #define RK3066_DIV_CORE_PERIPH_MASK 0x3 |
99 | #define RK3066_DIV_CORE_PERIPH_SHIFT 6 |
100 | #define RK3066_DIV_ACLK_CORE_MASK 0x7 |
101 | #define RK3066_DIV_ACLK_CORE_SHIFT 0 |
102 | #define RK3066_DIV_ACLK_HCLK_MASK 0x3 |
103 | #define RK3066_DIV_ACLK_HCLK_SHIFT 8 |
104 | #define RK3066_DIV_ACLK_PCLK_MASK 0x3 |
105 | #define RK3066_DIV_ACLK_PCLK_SHIFT 12 |
106 | #define RK3066_DIV_AHB2APB_MASK 0x3 |
107 | #define RK3066_DIV_AHB2APB_SHIFT 14 |
108 | |
109 | #define RK3066_CLKSEL0(_core_peri) \ |
110 | { \ |
111 | .reg = RK2928_CLKSEL_CON(0), \ |
112 | .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \ |
113 | RK3066_DIV_CORE_PERIPH_SHIFT) \ |
114 | } |
115 | #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \ |
116 | { \ |
117 | .reg = RK2928_CLKSEL_CON(1), \ |
118 | .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \ |
119 | RK3066_DIV_ACLK_CORE_SHIFT) | \ |
120 | HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \ |
121 | RK3066_DIV_ACLK_HCLK_SHIFT) | \ |
122 | HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \ |
123 | RK3066_DIV_ACLK_PCLK_SHIFT) | \ |
124 | HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \ |
125 | RK3066_DIV_AHB2APB_SHIFT), \ |
126 | } |
127 | |
128 | #define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \ |
129 | { \ |
130 | .prate = _prate, \ |
131 | .divs = { \ |
132 | RK3066_CLKSEL0(_core_peri), \ |
133 | RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \ |
134 | }, \ |
135 | } |
136 | |
137 | static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = { |
138 | RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1), |
139 | RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1), |
140 | RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1), |
141 | RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1), |
142 | RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1), |
143 | RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1), |
144 | RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0), |
145 | }; |
146 | |
147 | static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = { |
148 | .core_reg[0] = RK2928_CLKSEL_CON(0), |
149 | .div_core_shift[0] = 0, |
150 | .div_core_mask[0] = 0x1f, |
151 | .num_cores = 1, |
152 | .mux_core_alt = 1, |
153 | .mux_core_main = 0, |
154 | .mux_core_shift = 8, |
155 | .mux_core_mask = 0x1, |
156 | }; |
157 | |
158 | #define RK3188_DIV_ACLK_CORE_MASK 0x7 |
159 | #define RK3188_DIV_ACLK_CORE_SHIFT 3 |
160 | |
161 | #define RK3188_CLKSEL1(_aclk_core) \ |
162 | { \ |
163 | .reg = RK2928_CLKSEL_CON(1), \ |
164 | .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\ |
165 | RK3188_DIV_ACLK_CORE_SHIFT) \ |
166 | } |
167 | #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \ |
168 | { \ |
169 | .prate = _prate, \ |
170 | .divs = { \ |
171 | RK3066_CLKSEL0(_core_peri), \ |
172 | RK3188_CLKSEL1(_aclk_core), \ |
173 | }, \ |
174 | } |
175 | |
176 | static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = { |
177 | RK3188_CPUCLK_RATE(1608000000, 2, 3), |
178 | RK3188_CPUCLK_RATE(1416000000, 2, 3), |
179 | RK3188_CPUCLK_RATE(1200000000, 2, 3), |
180 | RK3188_CPUCLK_RATE(1008000000, 2, 3), |
181 | RK3188_CPUCLK_RATE( 816000000, 2, 3), |
182 | RK3188_CPUCLK_RATE( 600000000, 1, 3), |
183 | RK3188_CPUCLK_RATE( 504000000, 1, 3), |
184 | RK3188_CPUCLK_RATE( 312000000, 0, 1), |
185 | }; |
186 | |
187 | static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = { |
188 | .core_reg[0] = RK2928_CLKSEL_CON(0), |
189 | .div_core_shift[0] = 9, |
190 | .div_core_mask[0] = 0x1f, |
191 | .num_cores = 1, |
192 | .mux_core_alt = 1, |
193 | .mux_core_main = 0, |
194 | .mux_core_shift = 8, |
195 | .mux_core_mask = 0x1, |
196 | }; |
197 | |
198 | PNAME(mux_pll_p) = { "xin24m" , "xin32k" }; |
199 | PNAME(mux_armclk_p) = { "apll" , "gpll_armclk" }; |
200 | PNAME(mux_ddrphy_p) = { "dpll" , "gpll_ddr" }; |
201 | PNAME(mux_pll_src_gpll_cpll_p) = { "gpll" , "cpll" }; |
202 | PNAME(mux_pll_src_cpll_gpll_p) = { "cpll" , "gpll" }; |
203 | PNAME(mux_aclk_cpu_p) = { "apll" , "gpll" }; |
204 | PNAME(mux_sclk_cif0_p) = { "cif0_pre" , "xin24m" }; |
205 | PNAME(mux_sclk_i2s0_p) = { "i2s0_pre" , "i2s0_frac" , "xin12m" }; |
206 | PNAME(mux_sclk_spdif_p) = { "spdif_pre" , "spdif_frac" , "xin12m" }; |
207 | PNAME(mux_sclk_uart0_p) = { "uart0_pre" , "uart0_frac" , "xin24m" }; |
208 | PNAME(mux_sclk_uart1_p) = { "uart1_pre" , "uart1_frac" , "xin24m" }; |
209 | PNAME(mux_sclk_uart2_p) = { "uart2_pre" , "uart2_frac" , "xin24m" }; |
210 | PNAME(mux_sclk_uart3_p) = { "uart3_pre" , "uart3_frac" , "xin24m" }; |
211 | PNAME(mux_sclk_hsadc_p) = { "hsadc_src" , "hsadc_frac" , "ext_hsadc" }; |
212 | PNAME(mux_mac_p) = { "gpll" , "dpll" }; |
213 | PNAME(mux_sclk_macref_p) = { "mac_src" , "ext_rmii" }; |
214 | |
215 | static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = { |
216 | [apll] = PLL(pll_rk3066, PLL_APLL, "apll" , mux_pll_p, 0, RK2928_PLL_CON(0), |
217 | RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates), |
218 | [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll" , mux_pll_p, 0, RK2928_PLL_CON(4), |
219 | RK2928_MODE_CON, 4, 4, 0, NULL), |
220 | [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll" , mux_pll_p, 0, RK2928_PLL_CON(8), |
221 | RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), |
222 | [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll" , mux_pll_p, 0, RK2928_PLL_CON(12), |
223 | RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), |
224 | }; |
225 | |
226 | static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { |
227 | [apll] = PLL(pll_rk3066, PLL_APLL, "apll" , mux_pll_p, 0, RK2928_PLL_CON(0), |
228 | RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates), |
229 | [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll" , mux_pll_p, 0, RK2928_PLL_CON(4), |
230 | RK2928_MODE_CON, 4, 5, 0, NULL), |
231 | [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll" , mux_pll_p, 0, RK2928_PLL_CON(8), |
232 | RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), |
233 | [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll" , mux_pll_p, 0, RK2928_PLL_CON(12), |
234 | RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), |
235 | }; |
236 | |
237 | #define MFLAGS CLK_MUX_HIWORD_MASK |
238 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK |
239 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) |
240 | #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK |
241 | |
242 | /* 2 ^ (val + 1) */ |
243 | static struct clk_div_table div_core_peri_t[] = { |
244 | { .val = 0, .div = 2 }, |
245 | { .val = 1, .div = 4 }, |
246 | { .val = 2, .div = 8 }, |
247 | { .val = 3, .div = 16 }, |
248 | { /* sentinel */ }, |
249 | }; |
250 | |
251 | static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata = |
252 | MUX(0, "sclk_hsadc_out" , mux_sclk_hsadc_p, 0, |
253 | RK2928_CLKSEL_CON(22), 4, 2, MFLAGS); |
254 | |
255 | static struct rockchip_clk_branch common_spdif_fracmux __initdata = |
256 | MUX(SCLK_SPDIF, "sclk_spdif" , mux_sclk_spdif_p, CLK_SET_RATE_PARENT, |
257 | RK2928_CLKSEL_CON(5), 8, 2, MFLAGS); |
258 | |
259 | static struct rockchip_clk_branch common_uart0_fracmux __initdata = |
260 | MUX(SCLK_UART0, "sclk_uart0" , mux_sclk_uart0_p, CLK_SET_RATE_PARENT, |
261 | RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); |
262 | |
263 | static struct rockchip_clk_branch common_uart1_fracmux __initdata = |
264 | MUX(SCLK_UART1, "sclk_uart1" , mux_sclk_uart1_p, CLK_SET_RATE_PARENT, |
265 | RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); |
266 | |
267 | static struct rockchip_clk_branch common_uart2_fracmux __initdata = |
268 | MUX(SCLK_UART2, "sclk_uart2" , mux_sclk_uart2_p, CLK_SET_RATE_PARENT, |
269 | RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); |
270 | |
271 | static struct rockchip_clk_branch common_uart3_fracmux __initdata = |
272 | MUX(SCLK_UART3, "sclk_uart3" , mux_sclk_uart3_p, CLK_SET_RATE_PARENT, |
273 | RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); |
274 | |
275 | static struct rockchip_clk_branch common_clk_branches[] __initdata = { |
276 | /* |
277 | * Clock-Architecture Diagram 2 |
278 | */ |
279 | |
280 | GATE(0, "gpll_armclk" , "gpll" , 0, RK2928_CLKGATE_CON(0), 1, GFLAGS), |
281 | |
282 | /* these two are set by the cpuclk and should not be changed */ |
283 | COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri" , "armclk" , 0, |
284 | RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, |
285 | div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS), |
286 | |
287 | COMPOSITE(ACLK_VEPU, "aclk_vepu" , mux_pll_src_cpll_gpll_p, 0, |
288 | RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS, |
289 | RK2928_CLKGATE_CON(3), 9, GFLAGS), |
290 | GATE(HCLK_VEPU, "hclk_vepu" , "aclk_vepu" , 0, |
291 | RK2928_CLKGATE_CON(3), 10, GFLAGS), |
292 | COMPOSITE(ACLK_VDPU, "aclk_vdpu" , mux_pll_src_cpll_gpll_p, 0, |
293 | RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, |
294 | RK2928_CLKGATE_CON(3), 11, GFLAGS), |
295 | GATE(HCLK_VDPU, "hclk_vdpu" , "aclk_vdpu" , 0, |
296 | RK2928_CLKGATE_CON(3), 12, GFLAGS), |
297 | |
298 | GATE(0, "gpll_ddr" , "gpll" , CLK_IGNORE_UNUSED, |
299 | RK2928_CLKGATE_CON(1), 7, GFLAGS), |
300 | COMPOSITE(0, "ddrphy" , mux_ddrphy_p, CLK_IGNORE_UNUSED, |
301 | RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, |
302 | RK2928_CLKGATE_CON(0), 2, GFLAGS), |
303 | |
304 | GATE(ACLK_CPU, "aclk_cpu" , "aclk_cpu_pre" , 0, |
305 | RK2928_CLKGATE_CON(0), 3, GFLAGS), |
306 | |
307 | GATE(0, "atclk_cpu" , "pclk_cpu_pre" , 0, |
308 | RK2928_CLKGATE_CON(0), 6, GFLAGS), |
309 | GATE(PCLK_CPU, "pclk_cpu" , "pclk_cpu_pre" , 0, |
310 | RK2928_CLKGATE_CON(0), 5, GFLAGS), |
311 | GATE(HCLK_CPU, "hclk_cpu" , "hclk_cpu_pre" , CLK_IGNORE_UNUSED, |
312 | RK2928_CLKGATE_CON(0), 4, GFLAGS), |
313 | |
314 | COMPOSITE(0, "aclk_lcdc0_pre" , mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, |
315 | RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS, |
316 | RK2928_CLKGATE_CON(3), 0, GFLAGS), |
317 | COMPOSITE(0, "aclk_lcdc1_pre" , mux_pll_src_cpll_gpll_p, 0, |
318 | RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, |
319 | RK2928_CLKGATE_CON(1), 4, GFLAGS), |
320 | |
321 | GATE(ACLK_PERI, "aclk_peri" , "aclk_peri_pre" , 0, |
322 | RK2928_CLKGATE_CON(2), 1, GFLAGS), |
323 | COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri" , "aclk_peri_pre" , 0, |
324 | RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, |
325 | RK2928_CLKGATE_CON(2), 2, GFLAGS), |
326 | COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri" , "aclk_peri_pre" , 0, |
327 | RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, |
328 | RK2928_CLKGATE_CON(2), 3, GFLAGS), |
329 | |
330 | MUX(0, "cif_src" , mux_pll_src_cpll_gpll_p, 0, |
331 | RK2928_CLKSEL_CON(29), 0, 1, MFLAGS), |
332 | COMPOSITE_NOMUX(0, "cif0_pre" , "cif_src" , 0, |
333 | RK2928_CLKSEL_CON(29), 1, 5, DFLAGS, |
334 | RK2928_CLKGATE_CON(3), 7, GFLAGS), |
335 | MUX(SCLK_CIF0, "sclk_cif0" , mux_sclk_cif0_p, 0, |
336 | RK2928_CLKSEL_CON(29), 7, 1, MFLAGS), |
337 | |
338 | GATE(0, "pclkin_cif0" , "ext_cif0" , 0, |
339 | RK2928_CLKGATE_CON(3), 3, GFLAGS), |
340 | INVERTER(0, "pclk_cif0" , "pclkin_cif0" , |
341 | RK2928_CLKSEL_CON(30), 8, IFLAGS), |
342 | |
343 | FACTOR(0, "xin12m" , "xin24m" , 0, 1, 2), |
344 | |
345 | /* |
346 | * the 480m are generated inside the usb block from these clocks, |
347 | * but they are also a source for the hsicphy clock. |
348 | */ |
349 | GATE(SCLK_OTGPHY0, "sclk_otgphy0" , "xin24m" , CLK_IGNORE_UNUSED, |
350 | RK2928_CLKGATE_CON(1), 5, GFLAGS), |
351 | GATE(SCLK_OTGPHY1, "sclk_otgphy1" , "xin24m" , CLK_IGNORE_UNUSED, |
352 | RK2928_CLKGATE_CON(1), 6, GFLAGS), |
353 | |
354 | COMPOSITE(0, "mac_src" , mux_mac_p, 0, |
355 | RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS, |
356 | RK2928_CLKGATE_CON(2), 5, GFLAGS), |
357 | MUX(SCLK_MAC, "sclk_macref" , mux_sclk_macref_p, CLK_SET_RATE_PARENT, |
358 | RK2928_CLKSEL_CON(21), 4, 1, MFLAGS), |
359 | GATE(0, "sclk_mac_lbtest" , "sclk_macref" , 0, |
360 | RK2928_CLKGATE_CON(2), 12, GFLAGS), |
361 | |
362 | COMPOSITE(0, "hsadc_src" , mux_pll_src_gpll_cpll_p, 0, |
363 | RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, |
364 | RK2928_CLKGATE_CON(2), 6, GFLAGS), |
365 | COMPOSITE_FRACMUX(0, "hsadc_frac" , "hsadc_src" , 0, |
366 | RK2928_CLKSEL_CON(23), 0, |
367 | RK2928_CLKGATE_CON(2), 7, GFLAGS, |
368 | &common_hsadc_out_fracmux), |
369 | INVERTER(SCLK_HSADC, "sclk_hsadc" , "sclk_hsadc_out" , |
370 | RK2928_CLKSEL_CON(22), 7, IFLAGS), |
371 | |
372 | COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc" , "xin24m" , 0, |
373 | RK2928_CLKSEL_CON(24), 8, 8, DFLAGS, |
374 | RK2928_CLKGATE_CON(2), 8, GFLAGS), |
375 | |
376 | COMPOSITE_NOMUX(0, "spdif_pre" , "i2s_src" , 0, |
377 | RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, |
378 | RK2928_CLKGATE_CON(0), 13, GFLAGS), |
379 | COMPOSITE_FRACMUX(0, "spdif_frac" , "spdif_pre" , CLK_SET_RATE_PARENT, |
380 | RK2928_CLKSEL_CON(9), 0, |
381 | RK2928_CLKGATE_CON(0), 14, GFLAGS, |
382 | &common_spdif_fracmux), |
383 | |
384 | /* |
385 | * Clock-Architecture Diagram 4 |
386 | */ |
387 | |
388 | GATE(SCLK_SMC, "sclk_smc" , "hclk_peri" , 0, |
389 | RK2928_CLKGATE_CON(2), 4, GFLAGS), |
390 | |
391 | COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0" , "pclk_peri" , 0, |
392 | RK2928_CLKSEL_CON(25), 0, 7, DFLAGS, |
393 | RK2928_CLKGATE_CON(2), 9, GFLAGS), |
394 | COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1" , "pclk_peri" , 0, |
395 | RK2928_CLKSEL_CON(25), 8, 7, DFLAGS, |
396 | RK2928_CLKGATE_CON(2), 10, GFLAGS), |
397 | |
398 | COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc" , "hclk_peri" , 0, |
399 | RK2928_CLKSEL_CON(11), 0, 6, DFLAGS, |
400 | RK2928_CLKGATE_CON(2), 11, GFLAGS), |
401 | COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio" , "hclk_peri" , 0, |
402 | RK2928_CLKSEL_CON(12), 0, 6, DFLAGS, |
403 | RK2928_CLKGATE_CON(2), 13, GFLAGS), |
404 | COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc" , "hclk_peri" , 0, |
405 | RK2928_CLKSEL_CON(12), 8, 6, DFLAGS, |
406 | RK2928_CLKGATE_CON(2), 14, GFLAGS), |
407 | |
408 | MUX(0, "uart_src" , mux_pll_src_gpll_cpll_p, 0, |
409 | RK2928_CLKSEL_CON(12), 15, 1, MFLAGS), |
410 | COMPOSITE_NOMUX(0, "uart0_pre" , "uart_src" , 0, |
411 | RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, |
412 | RK2928_CLKGATE_CON(1), 8, GFLAGS), |
413 | COMPOSITE_FRACMUX(0, "uart0_frac" , "uart0_pre" , CLK_SET_RATE_PARENT, |
414 | RK2928_CLKSEL_CON(17), 0, |
415 | RK2928_CLKGATE_CON(1), 9, GFLAGS, |
416 | &common_uart0_fracmux), |
417 | COMPOSITE_NOMUX(0, "uart1_pre" , "uart_src" , 0, |
418 | RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, |
419 | RK2928_CLKGATE_CON(1), 10, GFLAGS), |
420 | COMPOSITE_FRACMUX(0, "uart1_frac" , "uart1_pre" , CLK_SET_RATE_PARENT, |
421 | RK2928_CLKSEL_CON(18), 0, |
422 | RK2928_CLKGATE_CON(1), 11, GFLAGS, |
423 | &common_uart1_fracmux), |
424 | COMPOSITE_NOMUX(0, "uart2_pre" , "uart_src" , 0, |
425 | RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, |
426 | RK2928_CLKGATE_CON(1), 12, GFLAGS), |
427 | COMPOSITE_FRACMUX(0, "uart2_frac" , "uart2_pre" , CLK_SET_RATE_PARENT, |
428 | RK2928_CLKSEL_CON(19), 0, |
429 | RK2928_CLKGATE_CON(1), 13, GFLAGS, |
430 | &common_uart2_fracmux), |
431 | COMPOSITE_NOMUX(0, "uart3_pre" , "uart_src" , 0, |
432 | RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, |
433 | RK2928_CLKGATE_CON(1), 14, GFLAGS), |
434 | COMPOSITE_FRACMUX(0, "uart3_frac" , "uart3_pre" , CLK_SET_RATE_PARENT, |
435 | RK2928_CLKSEL_CON(20), 0, |
436 | RK2928_CLKGATE_CON(1), 15, GFLAGS, |
437 | &common_uart3_fracmux), |
438 | |
439 | GATE(SCLK_JTAG, "jtag" , "ext_jtag" , 0, RK2928_CLKGATE_CON(1), 3, GFLAGS), |
440 | |
441 | GATE(SCLK_TIMER0, "timer0" , "xin24m" , 0, RK2928_CLKGATE_CON(1), 0, GFLAGS), |
442 | GATE(SCLK_TIMER1, "timer1" , "xin24m" , 0, RK2928_CLKGATE_CON(1), 1, GFLAGS), |
443 | |
444 | /* clk_core_pre gates */ |
445 | GATE(0, "core_dbg" , "armclk" , 0, RK2928_CLKGATE_CON(9), 0, GFLAGS), |
446 | |
447 | /* aclk_cpu gates */ |
448 | GATE(ACLK_DMA1, "aclk_dma1" , "aclk_cpu" , 0, RK2928_CLKGATE_CON(5), 0, GFLAGS), |
449 | GATE(0, "aclk_intmem" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS), |
450 | GATE(0, "aclk_strc_sys" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS), |
451 | |
452 | /* hclk_cpu gates */ |
453 | GATE(HCLK_ROM, "hclk_rom" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), |
454 | GATE(HCLK_SPDIF, "hclk_spdif" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), |
455 | GATE(0, "hclk_cpubus" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(4), 8, GFLAGS), |
456 | /* hclk_ahb2apb is part of a clk branch */ |
457 | GATE(0, "hclk_vio_bus" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(6), 12, GFLAGS), |
458 | GATE(HCLK_LCDC0, "hclk_lcdc0" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(6), 1, GFLAGS), |
459 | GATE(HCLK_LCDC1, "hclk_lcdc1" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(6), 2, GFLAGS), |
460 | GATE(HCLK_CIF0, "hclk_cif0" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(6), 4, GFLAGS), |
461 | GATE(HCLK_IPP, "hclk_ipp" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(6), 9, GFLAGS), |
462 | GATE(HCLK_RGA, "hclk_rga" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(6), 10, GFLAGS), |
463 | |
464 | /* hclk_peri gates */ |
465 | GATE(0, "hclk_peri_axi_matrix" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), |
466 | GATE(0, "hclk_peri_ahb_arbi" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS), |
467 | GATE(0, "hclk_emem_peri" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS), |
468 | GATE(HCLK_EMAC, "hclk_emac" , "hclk_peri" , 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), |
469 | GATE(HCLK_NANDC0, "hclk_nandc0" , "hclk_peri" , 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), |
470 | GATE(0, "hclk_usb_peri" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS), |
471 | GATE(HCLK_OTG0, "hclk_usbotg0" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), |
472 | GATE(HCLK_HSADC, "hclk_hsadc" , "hclk_peri" , 0, RK2928_CLKGATE_CON(7), 5, GFLAGS), |
473 | GATE(HCLK_PIDF, "hclk_pidfilter" , "hclk_peri" , 0, RK2928_CLKGATE_CON(7), 6, GFLAGS), |
474 | GATE(HCLK_SDMMC, "hclk_sdmmc" , "hclk_peri" , 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), |
475 | GATE(HCLK_SDIO, "hclk_sdio" , "hclk_peri" , 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), |
476 | GATE(HCLK_EMMC, "hclk_emmc" , "hclk_peri" , 0, RK2928_CLKGATE_CON(5), 12, GFLAGS), |
477 | |
478 | /* aclk_lcdc0_pre gates */ |
479 | GATE(0, "aclk_vio0" , "aclk_lcdc0_pre" , 0, RK2928_CLKGATE_CON(6), 13, GFLAGS), |
480 | GATE(ACLK_LCDC0, "aclk_lcdc0" , "aclk_vio0" , 0, RK2928_CLKGATE_CON(6), 0, GFLAGS), |
481 | GATE(ACLK_CIF0, "aclk_cif0" , "aclk_vio0" , 0, RK2928_CLKGATE_CON(6), 5, GFLAGS), |
482 | GATE(ACLK_IPP, "aclk_ipp" , "aclk_vio0" , 0, RK2928_CLKGATE_CON(6), 8, GFLAGS), |
483 | |
484 | /* aclk_lcdc1_pre gates */ |
485 | GATE(0, "aclk_vio1" , "aclk_lcdc1_pre" , 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), |
486 | GATE(ACLK_LCDC1, "aclk_lcdc1" , "aclk_vio1" , 0, RK2928_CLKGATE_CON(6), 3, GFLAGS), |
487 | GATE(ACLK_RGA, "aclk_rga" , "aclk_vio1" , 0, RK2928_CLKGATE_CON(6), 11, GFLAGS), |
488 | |
489 | /* atclk_cpu gates */ |
490 | GATE(0, "atclk" , "atclk_cpu" , 0, RK2928_CLKGATE_CON(9), 3, GFLAGS), |
491 | GATE(0, "trace" , "atclk_cpu" , 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), |
492 | |
493 | /* pclk_cpu gates */ |
494 | GATE(PCLK_PWM01, "pclk_pwm01" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), |
495 | GATE(PCLK_TIMER0, "pclk_timer0" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), |
496 | GATE(PCLK_I2C0, "pclk_i2c0" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), |
497 | GATE(PCLK_I2C1, "pclk_i2c1" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), |
498 | GATE(PCLK_GPIO0, "pclk_gpio0" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), |
499 | GATE(PCLK_GPIO1, "pclk_gpio1" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), |
500 | GATE(PCLK_GPIO2, "pclk_gpio2" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), |
501 | GATE(PCLK_EFUSE, "pclk_efuse" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(5), 2, GFLAGS), |
502 | GATE(PCLK_TZPC, "pclk_tzpc" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(5), 3, GFLAGS), |
503 | GATE(PCLK_DDRUPCTL, "pclk_ddrupctl" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), |
504 | GATE(PCLK_PUBL, "pclk_ddrpubl" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), |
505 | GATE(0, "pclk_dbg" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), |
506 | GATE(PCLK_GRF, "pclk_grf" , "pclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), |
507 | GATE(PCLK_PMU, "pclk_pmu" , "pclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS), |
508 | |
509 | /* aclk_peri */ |
510 | GATE(ACLK_DMA2, "aclk_dma2" , "aclk_peri" , 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), |
511 | GATE(ACLK_SMC, "aclk_smc" , "aclk_peri" , 0, RK2928_CLKGATE_CON(5), 8, GFLAGS), |
512 | GATE(0, "aclk_peri_niu" , "aclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS), |
513 | GATE(0, "aclk_cpu_peri" , "aclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), |
514 | GATE(0, "aclk_peri_axi_matrix" , "aclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS), |
515 | |
516 | /* pclk_peri gates */ |
517 | GATE(0, "pclk_peri_axi_matrix" , "pclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), |
518 | GATE(PCLK_PWM23, "pclk_pwm23" , "pclk_peri" , 0, RK2928_CLKGATE_CON(7), 11, GFLAGS), |
519 | GATE(PCLK_WDT, "pclk_wdt" , "pclk_peri" , 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), |
520 | GATE(PCLK_SPI0, "pclk_spi0" , "pclk_peri" , 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), |
521 | GATE(PCLK_SPI1, "pclk_spi1" , "pclk_peri" , 0, RK2928_CLKGATE_CON(7), 13, GFLAGS), |
522 | GATE(PCLK_UART2, "pclk_uart2" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), |
523 | GATE(PCLK_UART3, "pclk_uart3" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), |
524 | GATE(PCLK_I2C2, "pclk_i2c2" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), |
525 | GATE(PCLK_I2C3, "pclk_i2c3" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), |
526 | GATE(PCLK_I2C4, "pclk_i2c4" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), |
527 | GATE(PCLK_GPIO3, "pclk_gpio3" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), |
528 | GATE(PCLK_SARADC, "pclk_saradc" , "pclk_peri" , 0, RK2928_CLKGATE_CON(7), 14, GFLAGS), |
529 | }; |
530 | |
531 | PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src" , "xin27m" }; |
532 | PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src" , "xin27m" }; |
533 | PNAME(mux_sclk_cif1_p) = { "cif1_pre" , "xin24m" }; |
534 | PNAME(mux_sclk_i2s1_p) = { "i2s1_pre" , "i2s1_frac" , "xin12m" }; |
535 | PNAME(mux_sclk_i2s2_p) = { "i2s2_pre" , "i2s2_frac" , "xin12m" }; |
536 | |
537 | static struct clk_div_table div_aclk_cpu_t[] = { |
538 | { .val = 0, .div = 1 }, |
539 | { .val = 1, .div = 2 }, |
540 | { .val = 2, .div = 3 }, |
541 | { .val = 3, .div = 4 }, |
542 | { .val = 4, .div = 8 }, |
543 | { /* sentinel */ }, |
544 | }; |
545 | |
546 | static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata = |
547 | MUX(SCLK_I2S0, "sclk_i2s0" , mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, |
548 | RK2928_CLKSEL_CON(2), 8, 2, MFLAGS); |
549 | |
550 | static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata = |
551 | MUX(SCLK_I2S1, "sclk_i2s1" , mux_sclk_i2s1_p, CLK_SET_RATE_PARENT, |
552 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); |
553 | |
554 | static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata = |
555 | MUX(SCLK_I2S2, "sclk_i2s2" , mux_sclk_i2s2_p, CLK_SET_RATE_PARENT, |
556 | RK2928_CLKSEL_CON(4), 8, 2, MFLAGS); |
557 | |
558 | static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { |
559 | DIVTBL(0, "aclk_cpu_pre" , "armclk" , 0, |
560 | RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t), |
561 | DIV(0, "pclk_cpu_pre" , "aclk_cpu_pre" , 0, |
562 | RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO |
563 | | CLK_DIVIDER_READ_ONLY), |
564 | DIV(0, "hclk_cpu_pre" , "aclk_cpu_pre" , 0, |
565 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO |
566 | | CLK_DIVIDER_READ_ONLY), |
567 | COMPOSITE_NOMUX(0, "hclk_ahb2apb" , "hclk_cpu_pre" , 0, |
568 | RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO |
569 | | CLK_DIVIDER_READ_ONLY, |
570 | RK2928_CLKGATE_CON(4), 9, GFLAGS), |
571 | |
572 | GATE(CORE_L2C, "core_l2c" , "aclk_cpu" , CLK_IGNORE_UNUSED, |
573 | RK2928_CLKGATE_CON(9), 4, GFLAGS), |
574 | |
575 | COMPOSITE(0, "aclk_peri_pre" , mux_pll_src_gpll_cpll_p, 0, |
576 | RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, |
577 | RK2928_CLKGATE_CON(2), 0, GFLAGS), |
578 | |
579 | COMPOSITE(0, "dclk_lcdc0_src" , mux_pll_src_cpll_gpll_p, 0, |
580 | RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, |
581 | RK2928_CLKGATE_CON(3), 1, GFLAGS), |
582 | MUX(DCLK_LCDC0, "dclk_lcdc0" , mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT, |
583 | RK2928_CLKSEL_CON(27), 4, 1, MFLAGS), |
584 | COMPOSITE(0, "dclk_lcdc1_src" , mux_pll_src_cpll_gpll_p, 0, |
585 | RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, |
586 | RK2928_CLKGATE_CON(3), 2, GFLAGS), |
587 | MUX(DCLK_LCDC1, "dclk_lcdc1" , mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT, |
588 | RK2928_CLKSEL_CON(28), 4, 1, MFLAGS), |
589 | |
590 | COMPOSITE_NOMUX(0, "cif1_pre" , "cif_src" , 0, |
591 | RK2928_CLKSEL_CON(29), 8, 5, DFLAGS, |
592 | RK2928_CLKGATE_CON(3), 8, GFLAGS), |
593 | MUX(SCLK_CIF1, "sclk_cif1" , mux_sclk_cif1_p, 0, |
594 | RK2928_CLKSEL_CON(29), 15, 1, MFLAGS), |
595 | |
596 | GATE(0, "pclkin_cif1" , "ext_cif1" , 0, |
597 | RK2928_CLKGATE_CON(3), 4, GFLAGS), |
598 | INVERTER(0, "pclk_cif1" , "pclkin_cif1" , |
599 | RK2928_CLKSEL_CON(30), 12, IFLAGS), |
600 | |
601 | COMPOSITE(0, "aclk_gpu_src" , mux_pll_src_cpll_gpll_p, 0, |
602 | RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS, |
603 | RK2928_CLKGATE_CON(3), 13, GFLAGS), |
604 | GATE(ACLK_GPU, "aclk_gpu" , "aclk_gpu_src" , 0, |
605 | RK2928_CLKGATE_CON(5), 15, GFLAGS), |
606 | |
607 | GATE(SCLK_TIMER2, "timer2" , "xin24m" , 0, |
608 | RK2928_CLKGATE_CON(3), 2, GFLAGS), |
609 | |
610 | COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc" , "xin24m" , 0, |
611 | RK2928_CLKSEL_CON(34), 0, 16, DFLAGS, |
612 | RK2928_CLKGATE_CON(2), 15, GFLAGS), |
613 | |
614 | MUX(0, "i2s_src" , mux_pll_src_gpll_cpll_p, 0, |
615 | RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), |
616 | COMPOSITE_NOMUX(0, "i2s0_pre" , "i2s_src" , 0, |
617 | RK2928_CLKSEL_CON(2), 0, 7, DFLAGS, |
618 | RK2928_CLKGATE_CON(0), 7, GFLAGS), |
619 | COMPOSITE_FRACMUX(0, "i2s0_frac" , "i2s0_pre" , CLK_SET_RATE_PARENT, |
620 | RK2928_CLKSEL_CON(6), 0, |
621 | RK2928_CLKGATE_CON(0), 8, GFLAGS, |
622 | &rk3066a_i2s0_fracmux), |
623 | COMPOSITE_NOMUX(0, "i2s1_pre" , "i2s_src" , 0, |
624 | RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, |
625 | RK2928_CLKGATE_CON(0), 9, GFLAGS), |
626 | COMPOSITE_FRACMUX(0, "i2s1_frac" , "i2s1_pre" , CLK_SET_RATE_PARENT, |
627 | RK2928_CLKSEL_CON(7), 0, |
628 | RK2928_CLKGATE_CON(0), 10, GFLAGS, |
629 | &rk3066a_i2s1_fracmux), |
630 | COMPOSITE_NOMUX(0, "i2s2_pre" , "i2s_src" , 0, |
631 | RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, |
632 | RK2928_CLKGATE_CON(0), 11, GFLAGS), |
633 | COMPOSITE_FRACMUX(0, "i2s2_frac" , "i2s2_pre" , CLK_SET_RATE_PARENT, |
634 | RK2928_CLKSEL_CON(8), 0, |
635 | RK2928_CLKGATE_CON(0), 12, GFLAGS, |
636 | &rk3066a_i2s2_fracmux), |
637 | |
638 | GATE(HCLK_I2S0, "hclk_i2s0" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), |
639 | GATE(HCLK_I2S1, "hclk_i2s1" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), |
640 | GATE(HCLK_I2S2, "hclk_i2s2" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), |
641 | GATE(HCLK_CIF1, "hclk_cif1" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), |
642 | GATE(HCLK_HDMI, "hclk_hdmi" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), |
643 | |
644 | GATE(HCLK_OTG1, "hclk_usbotg1" , "hclk_peri" , CLK_IGNORE_UNUSED, |
645 | RK2928_CLKGATE_CON(5), 14, GFLAGS), |
646 | |
647 | GATE(ACLK_CIF1, "aclk_cif1" , "aclk_vio1" , 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), |
648 | |
649 | GATE(PCLK_TIMER1, "pclk_timer1" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(7), 8, GFLAGS), |
650 | GATE(PCLK_TIMER2, "pclk_timer2" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), |
651 | GATE(PCLK_GPIO6, "pclk_gpio6" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), |
652 | GATE(PCLK_UART0, "pclk_uart0" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), |
653 | GATE(PCLK_UART1, "pclk_uart1" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), |
654 | |
655 | GATE(PCLK_GPIO4, "pclk_gpio4" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), |
656 | GATE(PCLK_TSADC, "pclk_tsadc" , "pclk_peri" , 0, RK2928_CLKGATE_CON(4), 13, GFLAGS), |
657 | }; |
658 | |
659 | static struct clk_div_table div_rk3188_aclk_core_t[] = { |
660 | { .val = 0, .div = 1 }, |
661 | { .val = 1, .div = 2 }, |
662 | { .val = 2, .div = 3 }, |
663 | { .val = 3, .div = 4 }, |
664 | { .val = 4, .div = 8 }, |
665 | { /* sentinel */ }, |
666 | }; |
667 | |
668 | PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m" , "sclk_otgphy1_480m" , |
669 | "gpll" , "cpll" }; |
670 | |
671 | static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata = |
672 | MUX(SCLK_I2S0, "sclk_i2s0" , mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, |
673 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); |
674 | |
675 | static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { |
676 | COMPOSITE_NOMUX_DIVTBL(0, "aclk_core" , "armclk" , CLK_IGNORE_UNUSED, |
677 | RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, |
678 | div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS), |
679 | |
680 | /* do not source aclk_cpu_pre from the apll, to keep complexity down */ |
681 | COMPOSITE_NOGATE(0, "aclk_cpu_pre" , mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT, |
682 | RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS), |
683 | DIV(0, "pclk_cpu_pre" , "aclk_cpu_pre" , 0, |
684 | RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), |
685 | DIV(0, "hclk_cpu_pre" , "aclk_cpu_pre" , 0, |
686 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), |
687 | COMPOSITE_NOMUX(0, "hclk_ahb2apb" , "hclk_cpu_pre" , 0, |
688 | RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, |
689 | RK2928_CLKGATE_CON(4), 9, GFLAGS), |
690 | |
691 | GATE(CORE_L2C, "core_l2c" , "armclk" , CLK_IGNORE_UNUSED, |
692 | RK2928_CLKGATE_CON(9), 4, GFLAGS), |
693 | |
694 | COMPOSITE(0, "aclk_peri_pre" , mux_pll_src_cpll_gpll_p, 0, |
695 | RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, |
696 | RK2928_CLKGATE_CON(2), 0, GFLAGS), |
697 | |
698 | COMPOSITE(DCLK_LCDC0, "dclk_lcdc0" , mux_pll_src_cpll_gpll_p, 0, |
699 | RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, |
700 | RK2928_CLKGATE_CON(3), 1, GFLAGS), |
701 | COMPOSITE(DCLK_LCDC1, "dclk_lcdc1" , mux_pll_src_cpll_gpll_p, 0, |
702 | RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, |
703 | RK2928_CLKGATE_CON(3), 2, GFLAGS), |
704 | |
705 | COMPOSITE(0, "aclk_gpu_src" , mux_pll_src_cpll_gpll_p, 0, |
706 | RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS, |
707 | RK2928_CLKGATE_CON(3), 15, GFLAGS), |
708 | GATE(ACLK_GPU, "aclk_gpu" , "aclk_gpu_src" , 0, |
709 | RK2928_CLKGATE_CON(9), 7, GFLAGS), |
710 | |
711 | GATE(SCLK_TIMER2, "timer2" , "xin24m" , 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), |
712 | GATE(SCLK_TIMER3, "timer3" , "xin24m" , 0, RK2928_CLKGATE_CON(1), 2, GFLAGS), |
713 | GATE(SCLK_TIMER4, "timer4" , "xin24m" , 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), |
714 | GATE(SCLK_TIMER5, "timer5" , "xin24m" , 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), |
715 | GATE(SCLK_TIMER6, "timer6" , "xin24m" , 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), |
716 | |
717 | COMPOSITE_NODIV(0, "sclk_hsicphy_480m" , mux_hsicphy_p, 0, |
718 | RK2928_CLKSEL_CON(30), 0, 2, DFLAGS, |
719 | RK2928_CLKGATE_CON(3), 6, GFLAGS), |
720 | DIV(0, "sclk_hsicphy_12m" , "sclk_hsicphy_480m" , 0, |
721 | RK2928_CLKSEL_CON(11), 8, 6, DFLAGS), |
722 | |
723 | MUX(0, "i2s_src" , mux_pll_src_gpll_cpll_p, 0, |
724 | RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), |
725 | COMPOSITE_NOMUX(0, "i2s0_pre" , "i2s_src" , 0, |
726 | RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, |
727 | RK2928_CLKGATE_CON(0), 9, GFLAGS), |
728 | COMPOSITE_FRACMUX(0, "i2s0_frac" , "i2s0_pre" , CLK_SET_RATE_PARENT, |
729 | RK2928_CLKSEL_CON(7), 0, |
730 | RK2928_CLKGATE_CON(0), 10, GFLAGS, |
731 | &rk3188_i2s0_fracmux), |
732 | |
733 | GATE(HCLK_I2S0, "hclk_i2s0" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), |
734 | GATE(0, "hclk_imem0" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), |
735 | GATE(0, "hclk_imem1" , "hclk_cpu" , 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), |
736 | |
737 | GATE(HCLK_OTG1, "hclk_usbotg1" , "hclk_peri" , CLK_IGNORE_UNUSED, |
738 | RK2928_CLKGATE_CON(7), 3, GFLAGS), |
739 | GATE(HCLK_HSIC, "hclk_hsic" , "hclk_peri" , 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), |
740 | |
741 | GATE(PCLK_TIMER3, "pclk_timer3" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), |
742 | |
743 | GATE(PCLK_UART0, "pclk_uart0" , "hclk_ahb2apb" , 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), |
744 | GATE(PCLK_UART1, "pclk_uart1" , "hclk_ahb2apb" , 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), |
745 | |
746 | GATE(ACLK_GPS, "aclk_gps" , "aclk_peri" , 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), |
747 | }; |
748 | |
749 | static const char *const rk3188_critical_clocks[] __initconst = { |
750 | "aclk_cpu" , |
751 | "aclk_peri" , |
752 | "hclk_peri" , |
753 | "pclk_cpu" , |
754 | "pclk_peri" , |
755 | "hclk_cpubus" , |
756 | "hclk_vio_bus" , |
757 | "sclk_mac_lbtest" , |
758 | }; |
759 | |
760 | static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np) |
761 | { |
762 | struct rockchip_clk_provider *ctx; |
763 | void __iomem *reg_base; |
764 | |
765 | reg_base = of_iomap(node: np, index: 0); |
766 | if (!reg_base) { |
767 | pr_err("%s: could not map cru region\n" , __func__); |
768 | return ERR_PTR(error: -ENOMEM); |
769 | } |
770 | |
771 | ctx = rockchip_clk_init(np, base: reg_base, CLK_NR_CLKS); |
772 | if (IS_ERR(ptr: ctx)) { |
773 | pr_err("%s: rockchip clk init failed\n" , __func__); |
774 | iounmap(addr: reg_base); |
775 | return ERR_PTR(error: -ENOMEM); |
776 | } |
777 | |
778 | rockchip_clk_register_branches(ctx, list: common_clk_branches, |
779 | ARRAY_SIZE(common_clk_branches)); |
780 | |
781 | rockchip_register_softrst(np, num_regs: 9, base: reg_base + RK2928_SOFTRST_CON(0), |
782 | ROCKCHIP_SOFTRST_HIWORD_MASK); |
783 | |
784 | rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); |
785 | |
786 | return ctx; |
787 | } |
788 | |
789 | static void __init rk3066a_clk_init(struct device_node *np) |
790 | { |
791 | struct rockchip_clk_provider *ctx; |
792 | |
793 | ctx = rk3188_common_clk_init(np); |
794 | if (IS_ERR(ptr: ctx)) |
795 | return; |
796 | |
797 | rockchip_clk_register_plls(ctx, pll_list: rk3066_pll_clks, |
798 | ARRAY_SIZE(rk3066_pll_clks), |
799 | RK3066_GRF_SOC_STATUS); |
800 | rockchip_clk_register_branches(ctx, list: rk3066a_clk_branches, |
801 | ARRAY_SIZE(rk3066a_clk_branches)); |
802 | rockchip_clk_register_armclk(ctx, ARMCLK, name: "armclk" , |
803 | parent_names: mux_armclk_p, ARRAY_SIZE(mux_armclk_p), |
804 | reg_data: &rk3066_cpuclk_data, rates: rk3066_cpuclk_rates, |
805 | ARRAY_SIZE(rk3066_cpuclk_rates)); |
806 | rockchip_clk_protect_critical(clocks: rk3188_critical_clocks, |
807 | ARRAY_SIZE(rk3188_critical_clocks)); |
808 | rockchip_clk_of_add_provider(np, ctx); |
809 | } |
810 | CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru" , rk3066a_clk_init); |
811 | |
812 | static void __init rk3188a_clk_init(struct device_node *np) |
813 | { |
814 | struct rockchip_clk_provider *ctx; |
815 | struct clk *clk1, *clk2; |
816 | unsigned long rate; |
817 | int ret; |
818 | |
819 | ctx = rk3188_common_clk_init(np); |
820 | if (IS_ERR(ptr: ctx)) |
821 | return; |
822 | |
823 | rockchip_clk_register_plls(ctx, pll_list: rk3188_pll_clks, |
824 | ARRAY_SIZE(rk3188_pll_clks), |
825 | RK3188_GRF_SOC_STATUS); |
826 | rockchip_clk_register_branches(ctx, list: rk3188_clk_branches, |
827 | ARRAY_SIZE(rk3188_clk_branches)); |
828 | rockchip_clk_register_armclk(ctx, ARMCLK, name: "armclk" , |
829 | parent_names: mux_armclk_p, ARRAY_SIZE(mux_armclk_p), |
830 | reg_data: &rk3188_cpuclk_data, rates: rk3188_cpuclk_rates, |
831 | ARRAY_SIZE(rk3188_cpuclk_rates)); |
832 | |
833 | /* reparent aclk_cpu_pre from apll */ |
834 | clk1 = __clk_lookup(name: "aclk_cpu_pre" ); |
835 | clk2 = __clk_lookup(name: "gpll" ); |
836 | if (clk1 && clk2) { |
837 | rate = clk_get_rate(clk: clk1); |
838 | |
839 | ret = clk_set_parent(clk: clk1, parent: clk2); |
840 | if (ret < 0) |
841 | pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n" , |
842 | __func__); |
843 | |
844 | clk_set_rate(clk: clk1, rate); |
845 | } else { |
846 | pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n" , |
847 | __func__); |
848 | } |
849 | |
850 | rockchip_clk_protect_critical(clocks: rk3188_critical_clocks, |
851 | ARRAY_SIZE(rk3188_critical_clocks)); |
852 | rockchip_clk_of_add_provider(np, ctx); |
853 | } |
854 | CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru" , rk3188a_clk_init); |
855 | |
856 | static void __init rk3188_clk_init(struct device_node *np) |
857 | { |
858 | int i; |
859 | |
860 | for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) { |
861 | struct rockchip_pll_clock *pll = &rk3188_pll_clks[i]; |
862 | struct rockchip_pll_rate_table *rate; |
863 | |
864 | if (!pll->rate_table) |
865 | continue; |
866 | |
867 | rate = pll->rate_table; |
868 | while (rate->rate > 0) { |
869 | rate->nb = 1; |
870 | rate++; |
871 | } |
872 | } |
873 | |
874 | rk3188a_clk_init(np); |
875 | } |
876 | CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru" , rk3188_clk_init); |
877 | |