| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. |
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| 4 | * Author: Rahul Sharma <rahul.sharma@samsung.com> |
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| 5 | * |
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| 6 | * Common Clock Framework support for Exynos5260 SoC. |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __CLK_EXYNOS5260_H |
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| 10 | #define __CLK_EXYNOS5260_H |
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| 11 | |
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| 12 | /* |
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| 13 | *Registers for CMU_AUD |
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| 14 | */ |
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| 15 | #define MUX_SEL_AUD 0x0200 |
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| 16 | #define MUX_ENABLE_AUD 0x0300 |
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| 17 | #define MUX_STAT_AUD 0x0400 |
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| 18 | #define MUX_IGNORE_AUD 0x0500 |
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| 19 | #define DIV_AUD0 0x0600 |
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| 20 | #define DIV_AUD1 0x0604 |
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| 21 | #define DIV_STAT_AUD0 0x0700 |
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| 22 | #define DIV_STAT_AUD1 0x0704 |
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| 23 | #define EN_ACLK_AUD 0x0800 |
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| 24 | #define EN_PCLK_AUD 0x0900 |
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| 25 | #define EN_SCLK_AUD 0x0a00 |
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| 26 | #define EN_IP_AUD 0x0b00 |
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| 27 | |
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| 28 | /* |
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| 29 | *Registers for CMU_DISP |
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| 30 | */ |
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| 31 | #define MUX_SEL_DISP0 0x0200 |
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| 32 | #define MUX_SEL_DISP1 0x0204 |
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| 33 | #define MUX_SEL_DISP2 0x0208 |
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| 34 | #define MUX_SEL_DISP3 0x020C |
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| 35 | #define MUX_SEL_DISP4 0x0210 |
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| 36 | #define MUX_ENABLE_DISP0 0x0300 |
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| 37 | #define MUX_ENABLE_DISP1 0x0304 |
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| 38 | #define MUX_ENABLE_DISP2 0x0308 |
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| 39 | #define MUX_ENABLE_DISP3 0x030c |
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| 40 | #define MUX_ENABLE_DISP4 0x0310 |
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| 41 | #define MUX_STAT_DISP0 0x0400 |
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| 42 | #define MUX_STAT_DISP1 0x0404 |
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| 43 | #define MUX_STAT_DISP2 0x0408 |
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| 44 | #define MUX_STAT_DISP3 0x040c |
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| 45 | #define MUX_STAT_DISP4 0x0410 |
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| 46 | #define MUX_IGNORE_DISP0 0x0500 |
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| 47 | #define MUX_IGNORE_DISP1 0x0504 |
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| 48 | #define MUX_IGNORE_DISP2 0x0508 |
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| 49 | #define MUX_IGNORE_DISP3 0x050c |
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| 50 | #define MUX_IGNORE_DISP4 0x0510 |
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| 51 | #define DIV_DISP 0x0600 |
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| 52 | #define DIV_STAT_DISP 0x0700 |
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| 53 | #define EN_ACLK_DISP 0x0800 |
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| 54 | #define EN_PCLK_DISP 0x0900 |
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| 55 | #define EN_SCLK_DISP0 0x0a00 |
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| 56 | #define EN_SCLK_DISP1 0x0a04 |
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| 57 | #define EN_IP_DISP 0x0b00 |
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| 58 | #define EN_IP_DISP_BUS 0x0b04 |
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| 59 | |
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| 60 | |
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| 61 | /* |
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| 62 | *Registers for CMU_EGL |
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| 63 | */ |
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| 64 | #define EGL_PLL_LOCK 0x0000 |
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| 65 | #define EGL_DPLL_LOCK 0x0004 |
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| 66 | #define EGL_PLL_CON0 0x0100 |
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| 67 | #define EGL_PLL_CON1 0x0104 |
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| 68 | #define EGL_PLL_FREQ_DET 0x010c |
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| 69 | #define EGL_DPLL_CON0 0x0110 |
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| 70 | #define EGL_DPLL_CON1 0x0114 |
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| 71 | #define EGL_DPLL_FREQ_DET 0x011c |
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| 72 | #define MUX_SEL_EGL 0x0200 |
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| 73 | #define MUX_ENABLE_EGL 0x0300 |
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| 74 | #define MUX_STAT_EGL 0x0400 |
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| 75 | #define DIV_EGL 0x0600 |
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| 76 | #define DIV_EGL_PLL_FDET 0x0604 |
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| 77 | #define DIV_STAT_EGL 0x0700 |
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| 78 | #define DIV_STAT_EGL_PLL_FDET 0x0704 |
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| 79 | #define EN_ACLK_EGL 0x0800 |
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| 80 | #define EN_PCLK_EGL 0x0900 |
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| 81 | #define EN_SCLK_EGL 0x0a00 |
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| 82 | #define EN_IP_EGL 0x0b00 |
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| 83 | #define CLKOUT_CMU_EGL 0x0c00 |
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| 84 | #define CLKOUT_CMU_EGL_DIV_STAT 0x0c04 |
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| 85 | #define ARMCLK_STOPCTRL 0x1000 |
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| 86 | #define EAGLE_EMA_CTRL 0x1008 |
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| 87 | #define EAGLE_EMA_STATUS 0x100c |
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| 88 | #define PWR_CTRL 0x1020 |
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| 89 | #define PWR_CTRL2 0x1024 |
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| 90 | #define CLKSTOP_CTRL 0x1028 |
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| 91 | #define INTR_SPREAD_EN 0x1080 |
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| 92 | #define INTR_SPREAD_USE_STANDBYWFI 0x1084 |
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| 93 | #define INTR_SPREAD_BLOCKING_DURATION 0x1088 |
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| 94 | #define CMU_EGL_SPARE0 0x2000 |
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| 95 | #define CMU_EGL_SPARE1 0x2004 |
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| 96 | #define CMU_EGL_SPARE2 0x2008 |
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| 97 | #define CMU_EGL_SPARE3 0x200c |
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| 98 | #define CMU_EGL_SPARE4 0x2010 |
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| 99 | |
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| 100 | /* |
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| 101 | *Registers for CMU_FSYS |
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| 102 | */ |
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| 103 | |
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| 104 | #define MUX_SEL_FSYS0 0x0200 |
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| 105 | #define MUX_SEL_FSYS1 0x0204 |
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| 106 | #define MUX_ENABLE_FSYS0 0x0300 |
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| 107 | #define MUX_ENABLE_FSYS1 0x0304 |
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| 108 | #define MUX_STAT_FSYS0 0x0400 |
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| 109 | #define MUX_STAT_FSYS1 0x0404 |
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| 110 | #define MUX_IGNORE_FSYS0 0x0500 |
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| 111 | #define MUX_IGNORE_FSYS1 0x0504 |
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| 112 | #define EN_ACLK_FSYS 0x0800 |
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| 113 | #define EN_ACLK_FSYS_SECURE_RTIC 0x0804 |
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| 114 | #define EN_ACLK_FSYS_SECURE_SMMU_RTIC 0x0808 |
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| 115 | #define EN_PCLK_FSYS 0x0900 |
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| 116 | #define EN_SCLK_FSYS 0x0a00 |
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| 117 | #define EN_IP_FSYS 0x0b00 |
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| 118 | #define EN_IP_FSYS_SECURE_RTIC 0x0b04 |
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| 119 | #define EN_IP_FSYS_SECURE_SMMU_RTIC 0x0b08 |
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| 120 | |
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| 121 | /* |
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| 122 | *Registers for CMU_G2D |
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| 123 | */ |
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| 124 | |
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| 125 | #define MUX_SEL_G2D 0x0200 |
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| 126 | #define MUX_ENABLE_G2D 0x0300 |
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| 127 | #define MUX_STAT_G2D 0x0400 |
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| 128 | #define DIV_G2D 0x0600 |
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| 129 | #define DIV_STAT_G2D 0x0700 |
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| 130 | #define EN_ACLK_G2D 0x0800 |
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| 131 | #define EN_ACLK_G2D_SECURE_SSS 0x0804 |
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| 132 | #define EN_ACLK_G2D_SECURE_SLIM_SSS 0x0808 |
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| 133 | #define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS 0x080c |
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| 134 | #define EN_ACLK_G2D_SECURE_SMMU_SSS 0x0810 |
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| 135 | #define EN_ACLK_G2D_SECURE_SMMU_MDMA 0x0814 |
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| 136 | #define EN_ACLK_G2D_SECURE_SMMU_G2D 0x0818 |
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| 137 | #define EN_PCLK_G2D 0x0900 |
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| 138 | #define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS 0x0904 |
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| 139 | #define EN_PCLK_G2D_SECURE_SMMU_SSS 0x0908 |
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| 140 | #define EN_PCLK_G2D_SECURE_SMMU_MDMA 0x090c |
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| 141 | #define EN_PCLK_G2D_SECURE_SMMU_G2D 0x0910 |
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| 142 | #define EN_IP_G2D 0x0b00 |
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| 143 | #define EN_IP_G2D_SECURE_SSS 0x0b04 |
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| 144 | #define EN_IP_G2D_SECURE_SLIM_SSS 0x0b08 |
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| 145 | #define EN_IP_G2D_SECURE_SMMU_SLIM_SSS 0x0b0c |
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| 146 | #define EN_IP_G2D_SECURE_SMMU_SSS 0x0b10 |
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| 147 | #define EN_IP_G2D_SECURE_SMMU_MDMA 0x0b14 |
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| 148 | #define EN_IP_G2D_SECURE_SMMU_G2D 0x0b18 |
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| 149 | |
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| 150 | /* |
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| 151 | *Registers for CMU_G3D |
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| 152 | */ |
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| 153 | |
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| 154 | #define G3D_PLL_LOCK 0x0000 |
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| 155 | #define G3D_PLL_CON0 0x0100 |
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| 156 | #define G3D_PLL_CON1 0x0104 |
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| 157 | #define G3D_PLL_FDET 0x010c |
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| 158 | #define MUX_SEL_G3D 0x0200 |
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| 159 | #define MUX_EN_G3D 0x0300 |
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| 160 | #define MUX_STAT_G3D 0x0400 |
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| 161 | #define MUX_IGNORE_G3D 0x0500 |
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| 162 | #define DIV_G3D 0x0600 |
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| 163 | #define DIV_G3D_PLL_FDET 0x0604 |
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| 164 | #define DIV_STAT_G3D 0x0700 |
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| 165 | #define DIV_STAT_G3D_PLL_FDET 0x0704 |
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| 166 | #define EN_ACLK_G3D 0x0800 |
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| 167 | #define EN_PCLK_G3D 0x0900 |
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| 168 | #define EN_SCLK_G3D 0x0a00 |
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| 169 | #define EN_IP_G3D 0x0b00 |
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| 170 | #define CLKOUT_CMU_G3D 0x0c00 |
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| 171 | #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 |
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| 172 | #define G3DCLK_STOPCTRL 0x1000 |
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| 173 | #define G3D_EMA_CTRL 0x1008 |
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| 174 | #define G3D_EMA_STATUS 0x100c |
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| 175 | |
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| 176 | /* |
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| 177 | *Registers for CMU_GSCL |
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| 178 | */ |
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| 179 | |
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| 180 | #define MUX_SEL_GSCL 0x0200 |
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| 181 | #define MUX_EN_GSCL 0x0300 |
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| 182 | #define MUX_STAT_GSCL 0x0400 |
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| 183 | #define MUX_IGNORE_GSCL 0x0500 |
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| 184 | #define DIV_GSCL 0x0600 |
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| 185 | #define DIV_STAT_GSCL 0x0700 |
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| 186 | #define EN_ACLK_GSCL 0x0800 |
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| 187 | #define EN_ACLK_GSCL_FIMC 0x0804 |
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| 188 | #define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0808 |
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| 189 | #define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 0x080c |
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| 190 | #define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 0x0810 |
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| 191 | #define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 0x0814 |
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| 192 | #define EN_PCLK_GSCL 0x0900 |
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| 193 | #define EN_PCLK_GSCL_FIMC 0x0904 |
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| 194 | #define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0908 |
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| 195 | #define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 0x090c |
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| 196 | #define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 0x0910 |
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| 197 | #define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 0x0914 |
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| 198 | #define EN_SCLK_GSCL 0x0a00 |
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| 199 | #define EN_SCLK_GSCL_FIMC 0x0a04 |
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| 200 | #define EN_IP_GSCL 0x0b00 |
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| 201 | #define EN_IP_GSCL_FIMC 0x0b04 |
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| 202 | #define EN_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 |
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| 203 | #define EN_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c |
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| 204 | #define EN_IP_GSCL_SECURE_SMMU_MSCL0 0x0b10 |
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| 205 | #define EN_IP_GSCL_SECURE_SMMU_MSCL1 0x0b14 |
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| 206 | |
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| 207 | /* |
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| 208 | *Registers for CMU_ISP |
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| 209 | */ |
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| 210 | #define MUX_SEL_ISP0 0x0200 |
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| 211 | #define MUX_SEL_ISP1 0x0204 |
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| 212 | #define MUX_ENABLE_ISP0 0x0300 |
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| 213 | #define MUX_ENABLE_ISP1 0x0304 |
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| 214 | #define MUX_STAT_ISP0 0x0400 |
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| 215 | #define MUX_STAT_ISP1 0x0404 |
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| 216 | #define MUX_IGNORE_ISP0 0x0500 |
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| 217 | #define MUX_IGNORE_ISP1 0x0504 |
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| 218 | #define DIV_ISP 0x0600 |
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| 219 | #define DIV_STAT_ISP 0x0700 |
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| 220 | #define EN_ACLK_ISP0 0x0800 |
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| 221 | #define EN_ACLK_ISP1 0x0804 |
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| 222 | #define EN_PCLK_ISP0 0x0900 |
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| 223 | #define EN_PCLK_ISP1 0x0904 |
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| 224 | #define EN_SCLK_ISP 0x0a00 |
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| 225 | #define EN_IP_ISP0 0x0b00 |
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| 226 | #define EN_IP_ISP1 0x0b04 |
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| 227 | |
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| 228 | /* |
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| 229 | *Registers for CMU_KFC |
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| 230 | */ |
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| 231 | #define KFC_PLL_LOCK 0x0000 |
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| 232 | #define KFC_PLL_CON0 0x0100 |
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| 233 | #define KFC_PLL_CON1 0x0104 |
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| 234 | #define KFC_PLL_FDET 0x010c |
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| 235 | #define MUX_SEL_KFC0 0x0200 |
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| 236 | #define MUX_SEL_KFC2 0x0208 |
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| 237 | #define MUX_ENABLE_KFC0 0x0300 |
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| 238 | #define MUX_ENABLE_KFC2 0x0308 |
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| 239 | #define MUX_STAT_KFC0 0x0400 |
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| 240 | #define MUX_STAT_KFC2 0x0408 |
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| 241 | #define DIV_KFC 0x0600 |
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| 242 | #define DIV_KFC_PLL_FDET 0x0604 |
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| 243 | #define DIV_STAT_KFC 0x0700 |
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| 244 | #define DIV_STAT_KFC_PLL_FDET 0x0704 |
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| 245 | #define EN_ACLK_KFC 0x0800 |
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| 246 | #define EN_PCLK_KFC 0x0900 |
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| 247 | #define EN_SCLK_KFC 0x0a00 |
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| 248 | #define EN_IP_KFC 0x0b00 |
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| 249 | #define CLKOUT_CMU_KFC 0x0c00 |
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| 250 | #define CLKOUT_CMU_KFC_DIV_STAT 0x0c04 |
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| 251 | #define ARMCLK_STOPCTRL_KFC 0x1000 |
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| 252 | #define ARM_EMA_CTRL 0x1008 |
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| 253 | #define ARM_EMA_STATUS 0x100c |
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| 254 | #define PWR_CTRL_KFC 0x1020 |
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| 255 | #define PWR_CTRL2_KFC 0x1024 |
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| 256 | #define CLKSTOP_CTRL_KFC 0x1028 |
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| 257 | #define INTR_SPREAD_ENABLE_KFC 0x1080 |
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| 258 | #define INTR_SPREAD_USE_STANDBYWFI_KFC 0x1084 |
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| 259 | #define INTR_SPREAD_BLOCKING_DURATION_KFC 0x1088 |
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| 260 | #define CMU_KFC_SPARE0 0x2000 |
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| 261 | #define CMU_KFC_SPARE1 0x2004 |
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| 262 | #define CMU_KFC_SPARE2 0x2008 |
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| 263 | #define CMU_KFC_SPARE3 0x200c |
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| 264 | #define CMU_KFC_SPARE4 0x2010 |
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| 265 | |
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| 266 | /* |
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| 267 | *Registers for CMU_MFC |
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| 268 | */ |
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| 269 | #define MUX_SEL_MFC 0x0200 |
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| 270 | #define MUX_ENABLE_MFC 0x0300 |
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| 271 | #define MUX_STAT_MFC 0x0400 |
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| 272 | #define DIV_MFC 0x0600 |
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| 273 | #define DIV_STAT_MFC 0x0700 |
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| 274 | #define EN_ACLK_MFC 0x0800 |
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| 275 | #define EN_ACLK_SECURE_SMMU2_MFC 0x0804 |
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| 276 | #define EN_PCLK_MFC 0x0900 |
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| 277 | #define EN_PCLK_SECURE_SMMU2_MFC 0x0904 |
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| 278 | #define EN_IP_MFC 0x0b00 |
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| 279 | #define EN_IP_MFC_SECURE_SMMU2_MFC 0x0b04 |
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| 280 | |
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| 281 | /* |
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| 282 | *Registers for CMU_MIF |
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| 283 | */ |
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| 284 | #define MEM_PLL_LOCK 0x0000 |
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| 285 | #define BUS_PLL_LOCK 0x0004 |
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| 286 | #define MEDIA_PLL_LOCK 0x0008 |
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| 287 | #define MEM_PLL_CON0 0x0100 |
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| 288 | #define MEM_PLL_CON1 0x0104 |
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| 289 | #define MEM_PLL_FDET 0x010c |
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| 290 | #define BUS_PLL_CON0 0x0110 |
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| 291 | #define BUS_PLL_CON1 0x0114 |
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| 292 | #define BUS_PLL_FDET 0x011c |
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| 293 | #define MEDIA_PLL_CON0 0x0120 |
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| 294 | #define MEDIA_PLL_CON1 0x0124 |
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| 295 | #define MEDIA_PLL_FDET 0x012c |
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| 296 | #define MUX_SEL_MIF 0x0200 |
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| 297 | #define MUX_ENABLE_MIF 0x0300 |
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| 298 | #define MUX_STAT_MIF 0x0400 |
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| 299 | #define MUX_IGNORE_MIF 0x0500 |
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| 300 | #define DIV_MIF 0x0600 |
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| 301 | #define DIV_MIF_PLL_FDET 0x0604 |
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| 302 | #define DIV_STAT_MIF 0x0700 |
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| 303 | #define DIV_STAT_MIF_PLL_FDET 0x0704 |
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| 304 | #define EN_ACLK_MIF 0x0800 |
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| 305 | #define EN_ACLK_MIF_SECURE_DREX1_TZ 0x0804 |
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| 306 | #define EN_ACLK_MIF_SECURE_DREX0_TZ 0x0808 |
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| 307 | #define EN_ACLK_MIF_SECURE_INTMEM 0x080c |
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| 308 | #define EN_PCLK_MIF 0x0900 |
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| 309 | #define EN_PCLK_MIF_SECURE_MONOCNT 0x0904 |
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| 310 | #define EN_PCLK_MIF_SECURE_RTC_APBIF 0x0908 |
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| 311 | #define EN_PCLK_MIF_SECURE_DREX1_TZ 0x090c |
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| 312 | #define EN_PCLK_MIF_SECURE_DREX0_TZ 0x0910 |
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| 313 | #define EN_SCLK_MIF 0x0a00 |
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| 314 | #define EN_IP_MIF 0x0b00 |
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| 315 | #define EN_IP_MIF_SECURE_MONOCNT 0x0b04 |
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| 316 | #define EN_IP_MIF_SECURE_RTC_APBIF 0x0b08 |
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| 317 | #define EN_IP_MIF_SECURE_DREX1_TZ 0x0b0c |
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| 318 | #define EN_IP_MIF_SECURE_DREX0_TZ 0x0b10 |
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| 319 | #define EN_IP_MIF_SECURE_INTEMEM 0x0b14 |
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| 320 | #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 |
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| 321 | #define DREX_FREQ_CTRL 0x1000 |
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| 322 | #define PAUSE 0x1004 |
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| 323 | #define DDRPHY_LOCK_CTRL 0x1008 |
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| 324 | #define CLKOUT_CMU_MIF 0xcb00 |
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| 325 | |
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| 326 | /* |
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| 327 | *Registers for CMU_PERI |
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| 328 | */ |
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| 329 | #define MUX_SEL_PERI 0x0200 |
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| 330 | #define MUX_SEL_PERI1 0x0204 |
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| 331 | #define MUX_ENABLE_PERI 0x0300 |
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| 332 | #define MUX_ENABLE_PERI1 0x0304 |
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| 333 | #define MUX_STAT_PERI 0x0400 |
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| 334 | #define MUX_STAT_PERI1 0x0404 |
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| 335 | #define MUX_IGNORE_PERI 0x0500 |
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| 336 | #define MUX_IGNORE_PERI1 0x0504 |
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| 337 | #define DIV_PERI 0x0600 |
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| 338 | #define DIV_STAT_PERI 0x0700 |
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| 339 | #define EN_PCLK_PERI0 0x0800 |
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| 340 | #define EN_PCLK_PERI1 0x0804 |
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| 341 | #define EN_PCLK_PERI2 0x0808 |
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| 342 | #define EN_PCLK_PERI3 0x080c |
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| 343 | #define EN_PCLK_PERI_SECURE_CHIPID 0x0810 |
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| 344 | #define EN_PCLK_PERI_SECURE_PROVKEY0 0x0814 |
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| 345 | #define EN_PCLK_PERI_SECURE_PROVKEY1 0x0818 |
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| 346 | #define EN_PCLK_PERI_SECURE_SECKEY 0x081c |
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| 347 | #define EN_PCLK_PERI_SECURE_ANTIRBKCNT 0x0820 |
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| 348 | #define EN_PCLK_PERI_SECURE_TOP_RTC 0x0824 |
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| 349 | #define EN_PCLK_PERI_SECURE_TZPC 0x0828 |
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| 350 | #define EN_SCLK_PERI 0x0a00 |
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| 351 | #define EN_SCLK_PERI_SECURE_TOP_RTC 0x0a04 |
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| 352 | #define EN_IP_PERI0 0x0b00 |
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| 353 | #define EN_IP_PERI1 0x0b04 |
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| 354 | #define EN_IP_PERI2 0x0b08 |
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| 355 | #define EN_IP_PERI_SECURE_CHIPID 0x0b0c |
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| 356 | #define EN_IP_PERI_SECURE_PROVKEY0 0x0b10 |
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| 357 | #define EN_IP_PERI_SECURE_PROVKEY1 0x0b14 |
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| 358 | #define EN_IP_PERI_SECURE_SECKEY 0x0b18 |
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| 359 | #define EN_IP_PERI_SECURE_ANTIRBKCNT 0x0b1c |
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| 360 | #define EN_IP_PERI_SECURE_TOP_RTC 0x0b20 |
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| 361 | #define EN_IP_PERI_SECURE_TZPC 0x0b24 |
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| 362 | |
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| 363 | /* |
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| 364 | *Registers for CMU_TOP |
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| 365 | */ |
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| 366 | #define DISP_PLL_LOCK 0x0000 |
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| 367 | #define AUD_PLL_LOCK 0x0004 |
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| 368 | #define DISP_PLL_CON0 0x0100 |
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| 369 | #define DISP_PLL_CON1 0x0104 |
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| 370 | #define DISP_PLL_FDET 0x0108 |
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| 371 | #define AUD_PLL_CON0 0x0110 |
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| 372 | #define AUD_PLL_CON1 0x0114 |
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| 373 | #define AUD_PLL_CON2 0x0118 |
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| 374 | #define AUD_PLL_FDET 0x011c |
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| 375 | #define MUX_SEL_TOP_PLL0 0x0200 |
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| 376 | #define MUX_SEL_TOP_MFC 0x0204 |
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| 377 | #define MUX_SEL_TOP_G2D 0x0208 |
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| 378 | #define MUX_SEL_TOP_GSCL 0x020c |
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| 379 | #define MUX_SEL_TOP_ISP10 0x0214 |
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| 380 | #define MUX_SEL_TOP_ISP11 0x0218 |
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| 381 | #define MUX_SEL_TOP_DISP0 0x021c |
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| 382 | #define MUX_SEL_TOP_DISP1 0x0220 |
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| 383 | #define MUX_SEL_TOP_BUS 0x0224 |
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| 384 | #define MUX_SEL_TOP_PERI0 0x0228 |
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| 385 | #define MUX_SEL_TOP_PERI1 0x022c |
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| 386 | #define MUX_SEL_TOP_FSYS 0x0230 |
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| 387 | #define MUX_ENABLE_TOP_PLL0 0x0300 |
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| 388 | #define MUX_ENABLE_TOP_MFC 0x0304 |
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| 389 | #define MUX_ENABLE_TOP_G2D 0x0308 |
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| 390 | #define MUX_ENABLE_TOP_GSCL 0x030c |
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| 391 | #define MUX_ENABLE_TOP_ISP10 0x0314 |
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| 392 | #define MUX_ENABLE_TOP_ISP11 0x0318 |
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| 393 | #define MUX_ENABLE_TOP_DISP0 0x031c |
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| 394 | #define MUX_ENABLE_TOP_DISP1 0x0320 |
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| 395 | #define MUX_ENABLE_TOP_BUS 0x0324 |
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| 396 | #define MUX_ENABLE_TOP_PERI0 0x0328 |
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| 397 | #define MUX_ENABLE_TOP_PERI1 0x032c |
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| 398 | #define MUX_ENABLE_TOP_FSYS 0x0330 |
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| 399 | #define MUX_STAT_TOP_PLL0 0x0400 |
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| 400 | #define MUX_STAT_TOP_MFC 0x0404 |
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| 401 | #define MUX_STAT_TOP_G2D 0x0408 |
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| 402 | #define MUX_STAT_TOP_GSCL 0x040c |
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| 403 | #define MUX_STAT_TOP_ISP10 0x0414 |
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| 404 | #define MUX_STAT_TOP_ISP11 0x0418 |
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| 405 | #define MUX_STAT_TOP_DISP0 0x041c |
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| 406 | #define MUX_STAT_TOP_DISP1 0x0420 |
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| 407 | #define MUX_STAT_TOP_BUS 0x0424 |
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| 408 | #define MUX_STAT_TOP_PERI0 0x0428 |
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| 409 | #define MUX_STAT_TOP_PERI1 0x042c |
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| 410 | #define MUX_STAT_TOP_FSYS 0x0430 |
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| 411 | #define MUX_IGNORE_TOP_PLL0 0x0500 |
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| 412 | #define MUX_IGNORE_TOP_MFC 0x0504 |
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| 413 | #define MUX_IGNORE_TOP_G2D 0x0508 |
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| 414 | #define MUX_IGNORE_TOP_GSCL 0x050c |
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| 415 | #define MUX_IGNORE_TOP_ISP10 0x0514 |
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| 416 | #define MUX_IGNORE_TOP_ISP11 0x0518 |
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| 417 | #define MUX_IGNORE_TOP_DISP0 0x051c |
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| 418 | #define MUX_IGNORE_TOP_DISP1 0x0520 |
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| 419 | #define MUX_IGNORE_TOP_BUS 0x0524 |
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| 420 | #define MUX_IGNORE_TOP_PERI0 0x0528 |
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| 421 | #define MUX_IGNORE_TOP_PERI1 0x052c |
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| 422 | #define MUX_IGNORE_TOP_FSYS 0x0530 |
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| 423 | #define DIV_TOP_G2D_MFC 0x0600 |
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| 424 | #define DIV_TOP_GSCL_ISP0 0x0604 |
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| 425 | #define DIV_TOP_ISP10 0x0608 |
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| 426 | #define DIV_TOP_ISP11 0x060c |
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| 427 | #define DIV_TOP_DISP 0x0610 |
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| 428 | #define DIV_TOP_BUS 0x0614 |
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| 429 | #define DIV_TOP_PERI0 0x0618 |
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| 430 | #define DIV_TOP_PERI1 0x061c |
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| 431 | #define DIV_TOP_PERI2 0x0620 |
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| 432 | #define DIV_TOP_FSYS0 0x0624 |
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| 433 | #define DIV_TOP_FSYS1 0x0628 |
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| 434 | #define DIV_TOP_HPM 0x062c |
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| 435 | #define DIV_TOP_PLL_FDET 0x0630 |
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| 436 | #define DIV_STAT_TOP_G2D_MFC 0x0700 |
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| 437 | #define DIV_STAT_TOP_GSCL_ISP0 0x0704 |
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| 438 | #define DIV_STAT_TOP_ISP10 0x0708 |
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| 439 | #define DIV_STAT_TOP_ISP11 0x070c |
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| 440 | #define DIV_STAT_TOP_DISP 0x0710 |
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| 441 | #define DIV_STAT_TOP_BUS 0x0714 |
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| 442 | #define DIV_STAT_TOP_PERI0 0x0718 |
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| 443 | #define DIV_STAT_TOP_PERI1 0x071c |
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| 444 | #define DIV_STAT_TOP_PERI2 0x0720 |
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| 445 | #define DIV_STAT_TOP_FSYS0 0x0724 |
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| 446 | #define DIV_STAT_TOP_FSYS1 0x0728 |
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| 447 | #define DIV_STAT_TOP_HPM 0x072c |
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| 448 | #define DIV_STAT_TOP_PLL_FDET 0x0730 |
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| 449 | #define EN_ACLK_TOP 0x0800 |
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| 450 | #define EN_SCLK_TOP 0x0a00 |
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| 451 | #define EN_IP_TOP 0x0b00 |
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| 452 | #define CLKOUT_CMU_TOP 0x0c00 |
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| 453 | #define CLKOUT_CMU_TOP_DIV_STAT 0x0c04 |
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| 454 | |
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| 455 | #endif /*__CLK_EXYNOS5260_H */ |
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| 456 | |
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| 457 | |
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