| 1 | // SPDX-License-Identifier: GPL-2.0-only |
|---|---|
| 2 | /* |
| 3 | * Copyright (C) 2012 ST Microelectronics |
| 4 | * Viresh Kumar <vireshk@kernel.org> |
| 5 | * |
| 6 | * SPEAr clk - Common routines |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk-provider.h> |
| 10 | #include <linux/types.h> |
| 11 | #include "clk.h" |
| 12 | |
| 13 | long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, |
| 14 | unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, |
| 15 | int *index) |
| 16 | { |
| 17 | unsigned long prev_rate, rate = 0; |
| 18 | |
| 19 | for (*index = 0; *index < rtbl_cnt; (*index)++) { |
| 20 | prev_rate = rate; |
| 21 | rate = calc_rate(hw, parent_rate, *index); |
| 22 | if (drate < rate) { |
| 23 | /* previous clock was best */ |
| 24 | if (*index) { |
| 25 | rate = prev_rate; |
| 26 | (*index)--; |
| 27 | } |
| 28 | break; |
| 29 | } |
| 30 | } |
| 31 | |
| 32 | if ((*index) == rtbl_cnt) |
| 33 | (*index)--; |
| 34 | |
| 35 | return rate; |
| 36 | } |
| 37 |