| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright 2016 Maxime Ripard |
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| 4 | * |
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| 5 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _CCU_SUN50I_A64_H_ |
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| 9 | #define _CCU_SUN50I_A64_H_ |
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| 10 | |
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| 11 | #include <dt-bindings/clock/sun50i-a64-ccu.h> |
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| 12 | #include <dt-bindings/reset/sun50i-a64-ccu.h> |
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| 13 | |
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| 14 | #define CLK_OSC_12M 0 |
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| 15 | #define CLK_PLL_CPUX 1 |
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| 16 | #define CLK_PLL_AUDIO_BASE 2 |
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| 17 | #define CLK_PLL_AUDIO 3 |
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| 18 | #define CLK_PLL_AUDIO_2X 4 |
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| 19 | #define CLK_PLL_AUDIO_4X 5 |
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| 20 | #define CLK_PLL_AUDIO_8X 6 |
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| 21 | |
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| 22 | /* PLL_VIDEO0 exported for HDMI PHY */ |
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| 23 | |
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| 24 | #define CLK_PLL_VIDEO0_2X 8 |
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| 25 | #define CLK_PLL_VE 9 |
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| 26 | #define CLK_PLL_DDR0 10 |
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| 27 | |
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| 28 | /* PLL_PERIPH0 exported for PRCM */ |
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| 29 | |
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| 30 | #define CLK_PLL_PERIPH0_2X 12 |
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| 31 | #define CLK_PLL_PERIPH1 13 |
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| 32 | #define CLK_PLL_PERIPH1_2X 14 |
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| 33 | #define CLK_PLL_VIDEO1 15 |
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| 34 | #define CLK_PLL_GPU 16 |
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| 35 | #define CLK_PLL_MIPI 17 |
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| 36 | #define CLK_PLL_HSIC 18 |
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| 37 | #define CLK_PLL_DE 19 |
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| 38 | #define CLK_PLL_DDR1 20 |
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| 39 | #define CLK_AXI 22 |
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| 40 | #define CLK_APB 23 |
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| 41 | #define CLK_AHB1 24 |
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| 42 | #define CLK_APB1 25 |
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| 43 | #define CLK_APB2 26 |
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| 44 | #define CLK_AHB2 27 |
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| 45 | |
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| 46 | /* All the bus gates are exported */ |
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| 47 | |
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| 48 | /* The first bunch of module clocks are exported */ |
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| 49 | |
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| 50 | #define CLK_USB_OHCI0_12M 90 |
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| 51 | |
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| 52 | #define CLK_USB_OHCI1_12M 92 |
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| 53 | |
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| 54 | /* All the DRAM gates are exported */ |
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| 55 | |
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| 56 | /* And the DSI and GPU module clock is exported */ |
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| 57 | |
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| 58 | #define CLK_NUMBER (CLK_GPU + 1) |
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| 59 | |
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| 60 | #endif /* _CCU_SUN50I_A64_H_ */ |
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| 61 | |
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