| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright 2016 Maxime Ripard |
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| 4 | * |
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| 5 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _CCU_SUN5I_H_ |
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| 9 | #define _CCU_SUN5I_H_ |
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| 10 | |
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| 11 | #include <dt-bindings/clock/sun5i-ccu.h> |
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| 12 | #include <dt-bindings/reset/sun5i-ccu.h> |
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| 13 | |
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| 14 | /* The HOSC is exported */ |
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| 15 | #define CLK_PLL_CORE 2 |
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| 16 | #define CLK_PLL_AUDIO_BASE 3 |
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| 17 | #define CLK_PLL_AUDIO 4 |
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| 18 | #define CLK_PLL_AUDIO_2X 5 |
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| 19 | #define CLK_PLL_AUDIO_4X 6 |
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| 20 | #define CLK_PLL_AUDIO_8X 7 |
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| 21 | #define CLK_PLL_VIDEO0 8 |
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| 22 | |
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| 23 | /* The PLL_VIDEO0_2X is exported for HDMI */ |
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| 24 | |
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| 25 | #define CLK_PLL_VE 10 |
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| 26 | #define CLK_PLL_DDR_BASE 11 |
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| 27 | #define CLK_PLL_DDR 12 |
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| 28 | #define CLK_PLL_DDR_OTHER 13 |
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| 29 | #define CLK_PLL_PERIPH 14 |
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| 30 | #define CLK_PLL_VIDEO1 15 |
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| 31 | |
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| 32 | /* The PLL_VIDEO1_2X is exported for HDMI */ |
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| 33 | /* The CPU clock is exported */ |
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| 34 | |
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| 35 | #define CLK_AXI 18 |
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| 36 | #define CLK_AHB 19 |
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| 37 | #define CLK_APB0 20 |
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| 38 | #define CLK_APB1 21 |
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| 39 | #define CLK_DRAM_AXI 22 |
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| 40 | |
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| 41 | /* AHB gates are exported */ |
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| 42 | /* APB0 gates are exported */ |
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| 43 | /* APB1 gates are exported */ |
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| 44 | /* Modules clocks are exported */ |
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| 45 | /* USB clocks are exported */ |
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| 46 | /* GPS clock is exported */ |
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| 47 | /* DRAM gates are exported */ |
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| 48 | /* More display modules clocks are exported */ |
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| 49 | |
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| 50 | #define CLK_TCON_CH1_SCLK 91 |
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| 51 | |
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| 52 | /* The rest of the module clocks are exported */ |
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| 53 | |
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| 54 | #define CLK_NUMBER (CLK_IEP + 1) |
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| 55 | |
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| 56 | #endif /* _CCU_SUN5I_H_ */ |
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| 57 | |
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