| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _CCU_SUN8I_R40_H_ |
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| 7 | #define _CCU_SUN8I_R40_H_ |
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| 8 | |
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| 9 | #include <dt-bindings/clock/sun8i-r40-ccu.h> |
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| 10 | #include <dt-bindings/reset/sun8i-r40-ccu.h> |
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| 11 | |
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| 12 | #define CLK_OSC_12M 0 |
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| 13 | #define CLK_PLL_CPU 1 |
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| 14 | #define CLK_PLL_AUDIO_BASE 2 |
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| 15 | #define CLK_PLL_AUDIO 3 |
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| 16 | #define CLK_PLL_AUDIO_2X 4 |
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| 17 | #define CLK_PLL_AUDIO_4X 5 |
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| 18 | #define CLK_PLL_AUDIO_8X 6 |
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| 19 | |
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| 20 | /* PLL_VIDEO0 is exported */ |
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| 21 | |
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| 22 | #define CLK_PLL_VIDEO0_2X 8 |
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| 23 | #define CLK_PLL_VE 9 |
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| 24 | #define CLK_PLL_DDR0 10 |
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| 25 | #define CLK_PLL_PERIPH0 11 |
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| 26 | #define CLK_PLL_PERIPH0_SATA 12 |
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| 27 | #define CLK_PLL_PERIPH0_2X 13 |
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| 28 | #define CLK_PLL_PERIPH1 14 |
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| 29 | #define CLK_PLL_PERIPH1_2X 15 |
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| 30 | |
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| 31 | /* PLL_VIDEO1 is exported */ |
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| 32 | |
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| 33 | #define CLK_PLL_VIDEO1_2X 17 |
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| 34 | #define CLK_PLL_SATA 18 |
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| 35 | #define CLK_PLL_SATA_OUT 19 |
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| 36 | #define CLK_PLL_GPU 20 |
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| 37 | #define CLK_PLL_MIPI 21 |
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| 38 | #define CLK_PLL_DE 22 |
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| 39 | #define CLK_PLL_DDR1 23 |
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| 40 | |
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| 41 | /* The CPU clock is exported */ |
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| 42 | |
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| 43 | #define CLK_AXI 25 |
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| 44 | #define CLK_AHB1 26 |
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| 45 | #define CLK_APB1 27 |
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| 46 | #define CLK_APB2 28 |
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| 47 | |
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| 48 | /* All the bus gates are exported */ |
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| 49 | |
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| 50 | /* The first bunch of module clocks are exported */ |
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| 51 | |
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| 52 | #define CLK_DRAM 132 |
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| 53 | |
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| 54 | /* All the DRAM gates are exported */ |
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| 55 | |
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| 56 | /* Some more module clocks are exported */ |
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| 57 | |
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| 58 | #define CLK_NUMBER (CLK_OUTB + 1) |
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| 59 | |
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| 60 | #endif /* _CCU_SUN8I_R40_H_ */ |
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| 61 | |
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