1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
4 | * |
5 | * Based on ccu-sun8i-h3.c, which is: |
6 | * Copyright (c) 2016 Maxime Ripard. All rights reserved. |
7 | */ |
8 | |
9 | #include <linux/clk-provider.h> |
10 | #include <linux/io.h> |
11 | #include <linux/module.h> |
12 | #include <linux/of.h> |
13 | #include <linux/platform_device.h> |
14 | |
15 | #include "ccu_common.h" |
16 | #include "ccu_reset.h" |
17 | |
18 | #include "ccu_div.h" |
19 | #include "ccu_gate.h" |
20 | #include "ccu_mp.h" |
21 | #include "ccu_mult.h" |
22 | #include "ccu_nk.h" |
23 | #include "ccu_nkm.h" |
24 | #include "ccu_nkmp.h" |
25 | #include "ccu_nm.h" |
26 | #include "ccu_phase.h" |
27 | |
28 | #include "ccu-sun8i-v3s.h" |
29 | |
30 | static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu" , |
31 | "osc24M" , 0x000, |
32 | 8, 5, /* N */ |
33 | 4, 2, /* K */ |
34 | 0, 2, /* M */ |
35 | 16, 2, /* P */ |
36 | BIT(31), /* gate */ |
37 | BIT(28), /* lock */ |
38 | 0); |
39 | |
40 | /* |
41 | * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from |
42 | * the base (2x, 4x and 8x), and one variable divider (the one true |
43 | * pll audio). |
44 | * |
45 | * With sigma-delta modulation for fractional-N on the audio PLL, |
46 | * we have to use specific dividers. This means the variable divider |
47 | * can no longer be used, as the audio codec requests the exact clock |
48 | * rates we support through this mechanism. So we now hard code the |
49 | * variable divider to 1. This means the clock rates will no longer |
50 | * match the clock names. |
51 | */ |
52 | #define SUN8I_V3S_PLL_AUDIO_REG 0x008 |
53 | |
54 | static struct ccu_sdm_setting pll_audio_sdm_table[] = { |
55 | { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, |
56 | { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, |
57 | }; |
58 | |
59 | static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base" , |
60 | "osc24M" , 0x008, |
61 | 8, 7, /* N */ |
62 | 0, 5, /* M */ |
63 | pll_audio_sdm_table, BIT(24), |
64 | 0x284, BIT(31), |
65 | BIT(31), /* gate */ |
66 | BIT(28), /* lock */ |
67 | CLK_SET_RATE_UNGATE); |
68 | |
69 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video" , |
70 | "osc24M" , 0x0010, |
71 | 8, 7, /* N */ |
72 | 0, 4, /* M */ |
73 | BIT(24), /* frac enable */ |
74 | BIT(25), /* frac select */ |
75 | 270000000, /* frac rate 0 */ |
76 | 297000000, /* frac rate 1 */ |
77 | BIT(31), /* gate */ |
78 | BIT(28), /* lock */ |
79 | 0); |
80 | |
81 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve" , |
82 | "osc24M" , 0x0018, |
83 | 8, 7, /* N */ |
84 | 0, 4, /* M */ |
85 | BIT(24), /* frac enable */ |
86 | BIT(25), /* frac select */ |
87 | 270000000, /* frac rate 0 */ |
88 | 297000000, /* frac rate 1 */ |
89 | BIT(31), /* gate */ |
90 | BIT(28), /* lock */ |
91 | 0); |
92 | |
93 | static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0" , |
94 | "osc24M" , 0x020, |
95 | 8, 5, /* N */ |
96 | 4, 2, /* K */ |
97 | 0, 2, /* M */ |
98 | BIT(31), /* gate */ |
99 | BIT(28), /* lock */ |
100 | 0); |
101 | |
102 | static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0" , |
103 | "osc24M" , 0x028, |
104 | 8, 5, /* N */ |
105 | 4, 2, /* K */ |
106 | BIT(31), /* gate */ |
107 | BIT(28), /* lock */ |
108 | 2, /* post-div */ |
109 | 0); |
110 | |
111 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp" , |
112 | "osc24M" , 0x002c, |
113 | 8, 7, /* N */ |
114 | 0, 4, /* M */ |
115 | BIT(24), /* frac enable */ |
116 | BIT(25), /* frac select */ |
117 | 270000000, /* frac rate 0 */ |
118 | 297000000, /* frac rate 1 */ |
119 | BIT(31), /* gate */ |
120 | BIT(28), /* lock */ |
121 | 0); |
122 | |
123 | static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1" , |
124 | "osc24M" , 0x044, |
125 | 8, 5, /* N */ |
126 | 4, 2, /* K */ |
127 | BIT(31), /* gate */ |
128 | BIT(28), /* lock */ |
129 | 2, /* post-div */ |
130 | 0); |
131 | |
132 | static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1" , |
133 | "osc24M" , 0x04c, |
134 | 8, 7, /* N */ |
135 | 0, 2, /* M */ |
136 | BIT(31), /* gate */ |
137 | BIT(28), /* lock */ |
138 | 0); |
139 | |
140 | static const char * const cpu_parents[] = { "osc32k" , "osc24M" , |
141 | "pll-cpu" , "pll-cpu" }; |
142 | static SUNXI_CCU_MUX(cpu_clk, "cpu" , cpu_parents, |
143 | 0x050, 16, 2, CLK_IS_CRITICAL); |
144 | |
145 | static SUNXI_CCU_M(axi_clk, "axi" , "cpu" , 0x050, 0, 2, 0); |
146 | |
147 | static const char * const ahb1_parents[] = { "osc32k" , "osc24M" , |
148 | "axi" , "pll-periph0" }; |
149 | static const struct ccu_mux_var_prediv ahb1_predivs[] = { |
150 | { .index = 3, .shift = 6, .width = 2 }, |
151 | }; |
152 | static struct ccu_div ahb1_clk = { |
153 | .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), |
154 | |
155 | .mux = { |
156 | .shift = 12, |
157 | .width = 2, |
158 | |
159 | .var_predivs = ahb1_predivs, |
160 | .n_var_predivs = ARRAY_SIZE(ahb1_predivs), |
161 | }, |
162 | |
163 | .common = { |
164 | .reg = 0x054, |
165 | .features = CCU_FEATURE_VARIABLE_PREDIV, |
166 | .hw.init = CLK_HW_INIT_PARENTS("ahb1" , |
167 | ahb1_parents, |
168 | &ccu_div_ops, |
169 | 0), |
170 | }, |
171 | }; |
172 | |
173 | static struct clk_div_table apb1_div_table[] = { |
174 | { .val = 0, .div = 2 }, |
175 | { .val = 1, .div = 2 }, |
176 | { .val = 2, .div = 4 }, |
177 | { .val = 3, .div = 8 }, |
178 | { /* Sentinel */ }, |
179 | }; |
180 | static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1" , "ahb1" , |
181 | 0x054, 8, 2, apb1_div_table, 0); |
182 | |
183 | static const char * const apb2_parents[] = { "osc32k" , "osc24M" , |
184 | "pll-periph0" , "pll-periph0" }; |
185 | static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2" , apb2_parents, 0x058, |
186 | 0, 5, /* M */ |
187 | 16, 2, /* P */ |
188 | 24, 2, /* mux */ |
189 | 0); |
190 | |
191 | static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" }; |
192 | static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { |
193 | { .index = 1, .div = 2 }, |
194 | }; |
195 | static struct ccu_mux ahb2_clk = { |
196 | .mux = { |
197 | .shift = 0, |
198 | .width = 1, |
199 | .fixed_predivs = ahb2_fixed_predivs, |
200 | .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), |
201 | }, |
202 | |
203 | .common = { |
204 | .reg = 0x05c, |
205 | .features = CCU_FEATURE_FIXED_PREDIV, |
206 | .hw.init = CLK_HW_INIT_PARENTS("ahb2" , |
207 | ahb2_parents, |
208 | &ccu_mux_ops, |
209 | 0), |
210 | }, |
211 | }; |
212 | |
213 | static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce" , "ahb1" , |
214 | 0x060, BIT(5), 0); |
215 | static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma" , "ahb1" , |
216 | 0x060, BIT(6), 0); |
217 | static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0" , "ahb1" , |
218 | 0x060, BIT(8), 0); |
219 | static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1" , "ahb1" , |
220 | 0x060, BIT(9), 0); |
221 | static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2" , "ahb1" , |
222 | 0x060, BIT(10), 0); |
223 | static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram" , "ahb1" , |
224 | 0x060, BIT(14), 0); |
225 | static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac" , "ahb2" , |
226 | 0x060, BIT(17), 0); |
227 | static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer" , "ahb1" , |
228 | 0x060, BIT(19), 0); |
229 | static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0" , "ahb1" , |
230 | 0x060, BIT(20), 0); |
231 | static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg" , "ahb1" , |
232 | 0x060, BIT(24), 0); |
233 | static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0" , "ahb1" , |
234 | 0x060, BIT(26), 0); |
235 | static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0" , "ahb1" , |
236 | 0x060, BIT(29), 0); |
237 | |
238 | static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve" , "ahb1" , |
239 | 0x064, BIT(0), 0); |
240 | static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0" , "ahb1" , |
241 | 0x064, BIT(4), 0); |
242 | static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi" , "ahb1" , |
243 | 0x064, BIT(8), 0); |
244 | static SUNXI_CCU_GATE(bus_de_clk, "bus-de" , "ahb1" , |
245 | 0x064, BIT(12), 0); |
246 | |
247 | static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec" , "apb1" , |
248 | 0x068, BIT(0), 0); |
249 | static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio" , "apb1" , |
250 | 0x068, BIT(5), 0); |
251 | static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0" , "apb1" , |
252 | 0x068, BIT(12), 0); |
253 | |
254 | static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0" , "apb2" , |
255 | 0x06c, BIT(0), 0); |
256 | static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1" , "apb2" , |
257 | 0x06c, BIT(1), 0); |
258 | static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0" , "apb2" , |
259 | 0x06c, BIT(16), 0); |
260 | static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1" , "apb2" , |
261 | 0x06c, BIT(17), 0); |
262 | static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2" , "apb2" , |
263 | 0x06c, BIT(18), 0); |
264 | |
265 | static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy" , "ahb1" , |
266 | 0x070, BIT(0), 0); |
267 | static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg" , "ahb1" , |
268 | 0x070, BIT(7), 0); |
269 | |
270 | static const char * const mod0_default_parents[] = { "osc24M" , "pll-periph0" , |
271 | "pll-periph1" }; |
272 | static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0" , mod0_default_parents, 0x088, |
273 | 0, 4, /* M */ |
274 | 16, 2, /* P */ |
275 | 24, 2, /* mux */ |
276 | BIT(31), /* gate */ |
277 | 0); |
278 | |
279 | static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample" , "mmc0" , |
280 | 0x088, 20, 3, 0); |
281 | static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output" , "mmc0" , |
282 | 0x088, 8, 3, 0); |
283 | |
284 | static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1" , mod0_default_parents, 0x08c, |
285 | 0, 4, /* M */ |
286 | 16, 2, /* P */ |
287 | 24, 2, /* mux */ |
288 | BIT(31), /* gate */ |
289 | 0); |
290 | |
291 | static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample" , "mmc1" , |
292 | 0x08c, 20, 3, 0); |
293 | static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output" , "mmc1" , |
294 | 0x08c, 8, 3, 0); |
295 | |
296 | static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2" , mod0_default_parents, 0x090, |
297 | 0, 4, /* M */ |
298 | 16, 2, /* P */ |
299 | 24, 2, /* mux */ |
300 | BIT(31), /* gate */ |
301 | 0); |
302 | |
303 | static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample" , "mmc2" , |
304 | 0x090, 20, 3, 0); |
305 | static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output" , "mmc2" , |
306 | 0x090, 8, 3, 0); |
307 | |
308 | static const char * const ce_parents[] = { "osc24M" , "pll-periph0" , }; |
309 | |
310 | static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce" , ce_parents, 0x09c, |
311 | 0, 4, /* M */ |
312 | 16, 2, /* P */ |
313 | 24, 2, /* mux */ |
314 | BIT(31), /* gate */ |
315 | 0); |
316 | |
317 | static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0" , mod0_default_parents, 0x0a0, |
318 | 0, 4, /* M */ |
319 | 16, 2, /* P */ |
320 | 24, 2, /* mux */ |
321 | BIT(31), /* gate */ |
322 | 0); |
323 | |
324 | static const char * const i2s_parents[] = { "pll-audio-8x" , "pll-audio-4x" , |
325 | "pll-audio-2x" , "pll-audio" }; |
326 | static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0" , i2s_parents, |
327 | 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); |
328 | |
329 | static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0" , "osc24M" , |
330 | 0x0cc, BIT(8), 0); |
331 | static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0" , "osc24M" , |
332 | 0x0cc, BIT(16), 0); |
333 | |
334 | static const char * const dram_parents[] = { "pll-ddr0" , "pll-ddr1" , |
335 | "pll-periph0-2x" }; |
336 | static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram" , dram_parents, |
337 | 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); |
338 | |
339 | static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve" , "dram" , |
340 | 0x100, BIT(0), 0); |
341 | static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi" , "dram" , |
342 | 0x100, BIT(1), 0); |
343 | static SUNXI_CCU_GATE(dram_ehci_clk, "dram-ehci" , "dram" , |
344 | 0x100, BIT(17), 0); |
345 | static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci" , "dram" , |
346 | 0x100, BIT(18), 0); |
347 | |
348 | static const char * const de_parents[] = { "pll-video" , "pll-periph0" }; |
349 | static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de" , de_parents, |
350 | 0x104, 0, 4, 24, 2, BIT(31), |
351 | CLK_SET_RATE_PARENT); |
352 | |
353 | static const char * const tcon_parents[] = { "pll-video" }; |
354 | static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon" , tcon_parents, |
355 | 0x118, 0, 4, 24, 3, BIT(31), 0); |
356 | |
357 | static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc" , "osc24M" , |
358 | 0x130, BIT(31), 0); |
359 | |
360 | static const char * const csi_mclk_parents[] = { "osc24M" , "pll-video" , |
361 | "pll-periph0" , "pll-periph1" }; |
362 | static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk" , csi_mclk_parents, |
363 | 0x130, 0, 5, 8, 3, BIT(15), 0); |
364 | |
365 | static const char * const csi1_sclk_parents[] = { "pll-video" , "pll-isp" }; |
366 | static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk" , csi1_sclk_parents, |
367 | 0x134, 16, 4, 24, 3, BIT(31), 0); |
368 | |
369 | static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk" , csi_mclk_parents, |
370 | 0x134, 0, 5, 8, 3, BIT(15), 0); |
371 | |
372 | static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve" , "pll-ve" , |
373 | 0x13c, 16, 3, BIT(31), 0); |
374 | |
375 | static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig" , "pll-audio" , |
376 | 0x140, BIT(31), CLK_SET_RATE_PARENT); |
377 | static SUNXI_CCU_GATE(avs_clk, "avs" , "osc24M" , |
378 | 0x144, BIT(31), 0); |
379 | |
380 | static const char * const mbus_parents[] = { "osc24M" , "pll-periph0-2x" , |
381 | "pll-ddr" }; |
382 | static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus" , mbus_parents, |
383 | 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); |
384 | |
385 | static const char * const mipi_csi_parents[] = { "pll-video" , "pll-periph0" , |
386 | "pll-isp" }; |
387 | static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi" , mipi_csi_parents, |
388 | 0x16c, 0, 3, 24, 2, BIT(31), 0); |
389 | |
390 | static struct ccu_common *sun8i_v3s_ccu_clks[] = { |
391 | &pll_cpu_clk.common, |
392 | &pll_audio_base_clk.common, |
393 | &pll_video_clk.common, |
394 | &pll_ve_clk.common, |
395 | &pll_ddr0_clk.common, |
396 | &pll_periph0_clk.common, |
397 | &pll_isp_clk.common, |
398 | &pll_periph1_clk.common, |
399 | &pll_ddr1_clk.common, |
400 | &cpu_clk.common, |
401 | &axi_clk.common, |
402 | &ahb1_clk.common, |
403 | &apb1_clk.common, |
404 | &apb2_clk.common, |
405 | &ahb2_clk.common, |
406 | &bus_ce_clk.common, |
407 | &bus_dma_clk.common, |
408 | &bus_mmc0_clk.common, |
409 | &bus_mmc1_clk.common, |
410 | &bus_mmc2_clk.common, |
411 | &bus_dram_clk.common, |
412 | &bus_emac_clk.common, |
413 | &bus_hstimer_clk.common, |
414 | &bus_spi0_clk.common, |
415 | &bus_otg_clk.common, |
416 | &bus_ehci0_clk.common, |
417 | &bus_ohci0_clk.common, |
418 | &bus_ve_clk.common, |
419 | &bus_tcon0_clk.common, |
420 | &bus_csi_clk.common, |
421 | &bus_de_clk.common, |
422 | &bus_codec_clk.common, |
423 | &bus_pio_clk.common, |
424 | &bus_i2s0_clk.common, |
425 | &bus_i2c0_clk.common, |
426 | &bus_i2c1_clk.common, |
427 | &bus_uart0_clk.common, |
428 | &bus_uart1_clk.common, |
429 | &bus_uart2_clk.common, |
430 | &bus_ephy_clk.common, |
431 | &bus_dbg_clk.common, |
432 | &mmc0_clk.common, |
433 | &mmc0_sample_clk.common, |
434 | &mmc0_output_clk.common, |
435 | &mmc1_clk.common, |
436 | &mmc1_sample_clk.common, |
437 | &mmc1_output_clk.common, |
438 | &mmc2_clk.common, |
439 | &mmc2_sample_clk.common, |
440 | &mmc2_output_clk.common, |
441 | &ce_clk.common, |
442 | &spi0_clk.common, |
443 | &i2s0_clk.common, |
444 | &usb_phy0_clk.common, |
445 | &usb_ohci0_clk.common, |
446 | &dram_clk.common, |
447 | &dram_ve_clk.common, |
448 | &dram_csi_clk.common, |
449 | &dram_ohci_clk.common, |
450 | &dram_ehci_clk.common, |
451 | &de_clk.common, |
452 | &tcon_clk.common, |
453 | &csi_misc_clk.common, |
454 | &csi0_mclk_clk.common, |
455 | &csi1_sclk_clk.common, |
456 | &csi1_mclk_clk.common, |
457 | &ve_clk.common, |
458 | &ac_dig_clk.common, |
459 | &avs_clk.common, |
460 | &mbus_clk.common, |
461 | &mipi_csi_clk.common, |
462 | }; |
463 | |
464 | static const struct clk_hw *clk_parent_pll_audio[] = { |
465 | &pll_audio_base_clk.common.hw |
466 | }; |
467 | |
468 | /* We hardcode the divider to 1 for SDM support */ |
469 | static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio" , |
470 | clk_parent_pll_audio, |
471 | 1, 1, CLK_SET_RATE_PARENT); |
472 | static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x" , |
473 | clk_parent_pll_audio, |
474 | 2, 1, CLK_SET_RATE_PARENT); |
475 | static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x" , |
476 | clk_parent_pll_audio, |
477 | 1, 1, CLK_SET_RATE_PARENT); |
478 | static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x" , |
479 | clk_parent_pll_audio, |
480 | 1, 2, CLK_SET_RATE_PARENT); |
481 | static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x" , |
482 | &pll_periph0_clk.common.hw, |
483 | 1, 2, 0); |
484 | |
485 | static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { |
486 | .hws = { |
487 | [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, |
488 | [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, |
489 | [CLK_PLL_AUDIO] = &pll_audio_clk.hw, |
490 | [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, |
491 | [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, |
492 | [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, |
493 | [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, |
494 | [CLK_PLL_VE] = &pll_ve_clk.common.hw, |
495 | [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, |
496 | [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, |
497 | [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, |
498 | [CLK_PLL_ISP] = &pll_isp_clk.common.hw, |
499 | [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, |
500 | [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, |
501 | [CLK_CPU] = &cpu_clk.common.hw, |
502 | [CLK_AXI] = &axi_clk.common.hw, |
503 | [CLK_AHB1] = &ahb1_clk.common.hw, |
504 | [CLK_APB1] = &apb1_clk.common.hw, |
505 | [CLK_APB2] = &apb2_clk.common.hw, |
506 | [CLK_AHB2] = &ahb2_clk.common.hw, |
507 | [CLK_BUS_CE] = &bus_ce_clk.common.hw, |
508 | [CLK_BUS_DMA] = &bus_dma_clk.common.hw, |
509 | [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, |
510 | [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, |
511 | [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, |
512 | [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, |
513 | [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, |
514 | [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, |
515 | [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, |
516 | [CLK_BUS_OTG] = &bus_otg_clk.common.hw, |
517 | [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, |
518 | [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, |
519 | [CLK_BUS_VE] = &bus_ve_clk.common.hw, |
520 | [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, |
521 | [CLK_BUS_CSI] = &bus_csi_clk.common.hw, |
522 | [CLK_BUS_DE] = &bus_de_clk.common.hw, |
523 | [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, |
524 | [CLK_BUS_PIO] = &bus_pio_clk.common.hw, |
525 | [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, |
526 | [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, |
527 | [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, |
528 | [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, |
529 | [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, |
530 | [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw, |
531 | [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, |
532 | [CLK_MMC0] = &mmc0_clk.common.hw, |
533 | [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, |
534 | [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, |
535 | [CLK_MMC1] = &mmc1_clk.common.hw, |
536 | [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, |
537 | [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, |
538 | [CLK_MMC2] = &mmc2_clk.common.hw, |
539 | [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, |
540 | [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, |
541 | [CLK_CE] = &ce_clk.common.hw, |
542 | [CLK_SPI0] = &spi0_clk.common.hw, |
543 | [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, |
544 | [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, |
545 | [CLK_DRAM] = &dram_clk.common.hw, |
546 | [CLK_DRAM_VE] = &dram_ve_clk.common.hw, |
547 | [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, |
548 | [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw, |
549 | [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw, |
550 | [CLK_DE] = &de_clk.common.hw, |
551 | [CLK_TCON0] = &tcon_clk.common.hw, |
552 | [CLK_CSI_MISC] = &csi_misc_clk.common.hw, |
553 | [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, |
554 | [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, |
555 | [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, |
556 | [CLK_VE] = &ve_clk.common.hw, |
557 | [CLK_AC_DIG] = &ac_dig_clk.common.hw, |
558 | [CLK_AVS] = &avs_clk.common.hw, |
559 | [CLK_MBUS] = &mbus_clk.common.hw, |
560 | [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, |
561 | }, |
562 | .num = CLK_PLL_DDR1 + 1, |
563 | }; |
564 | |
565 | static struct clk_hw_onecell_data sun8i_v3_hw_clks = { |
566 | .hws = { |
567 | [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, |
568 | [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, |
569 | [CLK_PLL_AUDIO] = &pll_audio_clk.hw, |
570 | [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, |
571 | [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, |
572 | [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, |
573 | [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, |
574 | [CLK_PLL_VE] = &pll_ve_clk.common.hw, |
575 | [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, |
576 | [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, |
577 | [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, |
578 | [CLK_PLL_ISP] = &pll_isp_clk.common.hw, |
579 | [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, |
580 | [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, |
581 | [CLK_CPU] = &cpu_clk.common.hw, |
582 | [CLK_AXI] = &axi_clk.common.hw, |
583 | [CLK_AHB1] = &ahb1_clk.common.hw, |
584 | [CLK_APB1] = &apb1_clk.common.hw, |
585 | [CLK_APB2] = &apb2_clk.common.hw, |
586 | [CLK_AHB2] = &ahb2_clk.common.hw, |
587 | [CLK_BUS_CE] = &bus_ce_clk.common.hw, |
588 | [CLK_BUS_DMA] = &bus_dma_clk.common.hw, |
589 | [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, |
590 | [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, |
591 | [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, |
592 | [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, |
593 | [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, |
594 | [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, |
595 | [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, |
596 | [CLK_BUS_OTG] = &bus_otg_clk.common.hw, |
597 | [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, |
598 | [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, |
599 | [CLK_BUS_VE] = &bus_ve_clk.common.hw, |
600 | [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, |
601 | [CLK_BUS_CSI] = &bus_csi_clk.common.hw, |
602 | [CLK_BUS_DE] = &bus_de_clk.common.hw, |
603 | [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, |
604 | [CLK_BUS_PIO] = &bus_pio_clk.common.hw, |
605 | [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, |
606 | [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, |
607 | [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, |
608 | [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, |
609 | [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, |
610 | [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, |
611 | [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw, |
612 | [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, |
613 | [CLK_MMC0] = &mmc0_clk.common.hw, |
614 | [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, |
615 | [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, |
616 | [CLK_MMC1] = &mmc1_clk.common.hw, |
617 | [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, |
618 | [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, |
619 | [CLK_MMC2] = &mmc2_clk.common.hw, |
620 | [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, |
621 | [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, |
622 | [CLK_CE] = &ce_clk.common.hw, |
623 | [CLK_SPI0] = &spi0_clk.common.hw, |
624 | [CLK_I2S0] = &i2s0_clk.common.hw, |
625 | [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, |
626 | [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, |
627 | [CLK_DRAM] = &dram_clk.common.hw, |
628 | [CLK_DRAM_VE] = &dram_ve_clk.common.hw, |
629 | [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, |
630 | [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw, |
631 | [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw, |
632 | [CLK_DE] = &de_clk.common.hw, |
633 | [CLK_TCON0] = &tcon_clk.common.hw, |
634 | [CLK_CSI_MISC] = &csi_misc_clk.common.hw, |
635 | [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, |
636 | [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, |
637 | [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, |
638 | [CLK_VE] = &ve_clk.common.hw, |
639 | [CLK_AC_DIG] = &ac_dig_clk.common.hw, |
640 | [CLK_AVS] = &avs_clk.common.hw, |
641 | [CLK_MBUS] = &mbus_clk.common.hw, |
642 | [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, |
643 | }, |
644 | .num = CLK_I2S0 + 1, |
645 | }; |
646 | |
647 | static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { |
648 | [RST_USB_PHY0] = { 0x0cc, BIT(0) }, |
649 | |
650 | [RST_MBUS] = { 0x0fc, BIT(31) }, |
651 | |
652 | [RST_BUS_CE] = { 0x2c0, BIT(5) }, |
653 | [RST_BUS_DMA] = { 0x2c0, BIT(6) }, |
654 | [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, |
655 | [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, |
656 | [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, |
657 | [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, |
658 | [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, |
659 | [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, |
660 | [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, |
661 | [RST_BUS_OTG] = { 0x2c0, BIT(24) }, |
662 | [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, |
663 | [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, |
664 | |
665 | [RST_BUS_VE] = { 0x2c4, BIT(0) }, |
666 | [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, |
667 | [RST_BUS_CSI] = { 0x2c4, BIT(8) }, |
668 | [RST_BUS_DE] = { 0x2c4, BIT(12) }, |
669 | [RST_BUS_DBG] = { 0x2c4, BIT(31) }, |
670 | |
671 | [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, |
672 | |
673 | [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, |
674 | |
675 | [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, |
676 | [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, |
677 | [RST_BUS_UART0] = { 0x2d8, BIT(16) }, |
678 | [RST_BUS_UART1] = { 0x2d8, BIT(17) }, |
679 | [RST_BUS_UART2] = { 0x2d8, BIT(18) }, |
680 | }; |
681 | |
682 | static struct ccu_reset_map sun8i_v3_ccu_resets[] = { |
683 | [RST_USB_PHY0] = { 0x0cc, BIT(0) }, |
684 | |
685 | [RST_MBUS] = { 0x0fc, BIT(31) }, |
686 | |
687 | [RST_BUS_CE] = { 0x2c0, BIT(5) }, |
688 | [RST_BUS_DMA] = { 0x2c0, BIT(6) }, |
689 | [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, |
690 | [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, |
691 | [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, |
692 | [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, |
693 | [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, |
694 | [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, |
695 | [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, |
696 | [RST_BUS_OTG] = { 0x2c0, BIT(24) }, |
697 | [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, |
698 | [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, |
699 | |
700 | [RST_BUS_VE] = { 0x2c4, BIT(0) }, |
701 | [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, |
702 | [RST_BUS_CSI] = { 0x2c4, BIT(8) }, |
703 | [RST_BUS_DE] = { 0x2c4, BIT(12) }, |
704 | [RST_BUS_DBG] = { 0x2c4, BIT(31) }, |
705 | |
706 | [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, |
707 | |
708 | [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, |
709 | [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, |
710 | |
711 | [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, |
712 | [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, |
713 | [RST_BUS_UART0] = { 0x2d8, BIT(16) }, |
714 | [RST_BUS_UART1] = { 0x2d8, BIT(17) }, |
715 | [RST_BUS_UART2] = { 0x2d8, BIT(18) }, |
716 | }; |
717 | |
718 | static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = { |
719 | .ccu_clks = sun8i_v3s_ccu_clks, |
720 | .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks), |
721 | |
722 | .hw_clks = &sun8i_v3s_hw_clks, |
723 | |
724 | .resets = sun8i_v3s_ccu_resets, |
725 | .num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets), |
726 | }; |
727 | |
728 | static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = { |
729 | .ccu_clks = sun8i_v3s_ccu_clks, |
730 | .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks), |
731 | |
732 | .hw_clks = &sun8i_v3_hw_clks, |
733 | |
734 | .resets = sun8i_v3_ccu_resets, |
735 | .num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets), |
736 | }; |
737 | |
738 | static int sun8i_v3s_ccu_probe(struct platform_device *pdev) |
739 | { |
740 | const struct sunxi_ccu_desc *desc; |
741 | void __iomem *reg; |
742 | u32 val; |
743 | |
744 | desc = of_device_get_match_data(dev: &pdev->dev); |
745 | if (!desc) |
746 | return -EINVAL; |
747 | |
748 | reg = devm_platform_ioremap_resource(pdev, index: 0); |
749 | if (IS_ERR(ptr: reg)) |
750 | return PTR_ERR(ptr: reg); |
751 | |
752 | /* Force the PLL-Audio-1x divider to 1 */ |
753 | val = readl(addr: reg + SUN8I_V3S_PLL_AUDIO_REG); |
754 | val &= ~GENMASK(19, 16); |
755 | writel(val, addr: reg + SUN8I_V3S_PLL_AUDIO_REG); |
756 | |
757 | return devm_sunxi_ccu_probe(dev: &pdev->dev, reg, desc); |
758 | } |
759 | |
760 | static const struct of_device_id sun8i_v3s_ccu_ids[] = { |
761 | { |
762 | .compatible = "allwinner,sun8i-v3-ccu" , |
763 | .data = &sun8i_v3_ccu_desc, |
764 | }, |
765 | { |
766 | .compatible = "allwinner,sun8i-v3s-ccu" , |
767 | .data = &sun8i_v3s_ccu_desc, |
768 | }, |
769 | { } |
770 | }; |
771 | |
772 | static struct platform_driver sun8i_v3s_ccu_driver = { |
773 | .probe = sun8i_v3s_ccu_probe, |
774 | .driver = { |
775 | .name = "sun8i-v3s-ccu" , |
776 | .suppress_bind_attrs = true, |
777 | .of_match_table = sun8i_v3s_ccu_ids, |
778 | }, |
779 | }; |
780 | module_platform_driver(sun8i_v3s_ccu_driver); |
781 | |
782 | MODULE_IMPORT_NS(SUNXI_CCU); |
783 | MODULE_LICENSE("GPL" ); |
784 | |