| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> |
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| 4 | * |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef _CCU_SUNIV_F1C100S_H_ |
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| 8 | #define _CCU_SUNIV_F1C100S_H_ |
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| 9 | |
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| 10 | #include <dt-bindings/clock/suniv-ccu-f1c100s.h> |
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| 11 | #include <dt-bindings/reset/suniv-ccu-f1c100s.h> |
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| 12 | |
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| 13 | #define CLK_PLL_CPU 0 |
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| 14 | #define CLK_PLL_AUDIO_BASE 1 |
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| 15 | #define CLK_PLL_AUDIO 2 |
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| 16 | #define CLK_PLL_AUDIO_2X 3 |
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| 17 | #define CLK_PLL_AUDIO_4X 4 |
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| 18 | #define CLK_PLL_AUDIO_8X 5 |
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| 19 | #define CLK_PLL_VIDEO 6 |
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| 20 | #define CLK_PLL_VIDEO_2X 7 |
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| 21 | #define CLK_PLL_VE 8 |
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| 22 | #define CLK_PLL_DDR0 9 |
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| 23 | #define CLK_PLL_PERIPH 10 |
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| 24 | |
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| 25 | /* CPU clock is exported */ |
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| 26 | |
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| 27 | #define CLK_AHB 12 |
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| 28 | #define CLK_APB 13 |
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| 29 | |
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| 30 | /* All bus gates, DRAM gates and mod clocks are exported */ |
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| 31 | |
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| 32 | #define CLK_NUMBER (CLK_IR + 1) |
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| 33 | |
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| 34 | #endif /* _CCU_SUNIV_F1C100S_H_ */ |
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| 35 | |
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