| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Clocks for ux500 platforms |
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| 4 | * |
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| 5 | * Copyright (C) 2012 ST-Ericsson SA |
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| 6 | * Author: Ulf Hansson <ulf.hansson@linaro.org> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __UX500_CLK_H |
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| 10 | #define __UX500_CLK_H |
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| 11 | |
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| 12 | #include <linux/device.h> |
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| 13 | #include <linux/types.h> |
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| 14 | |
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| 15 | struct clk; |
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| 16 | struct clk_hw; |
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| 17 | |
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| 18 | struct clk *clk_reg_prcc_pclk(const char *name, |
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| 19 | const char *parent_name, |
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| 20 | resource_size_t phy_base, |
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| 21 | u32 cg_sel, |
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| 22 | unsigned long flags); |
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| 23 | |
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| 24 | struct clk *clk_reg_prcc_kclk(const char *name, |
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| 25 | const char *parent_name, |
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| 26 | resource_size_t phy_base, |
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| 27 | u32 cg_sel, |
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| 28 | unsigned long flags); |
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| 29 | |
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| 30 | struct clk_hw *clk_reg_prcmu_scalable(const char *name, |
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| 31 | const char *parent_name, |
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| 32 | u8 cg_sel, |
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| 33 | unsigned long rate, |
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| 34 | unsigned long flags); |
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| 35 | |
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| 36 | struct clk_hw *clk_reg_prcmu_gate(const char *name, |
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| 37 | const char *parent_name, |
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| 38 | u8 cg_sel, |
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| 39 | unsigned long flags); |
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| 40 | |
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| 41 | struct clk_hw *clk_reg_prcmu_scalable_rate(const char *name, |
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| 42 | const char *parent_name, |
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| 43 | u8 cg_sel, |
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| 44 | unsigned long rate, |
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| 45 | unsigned long flags); |
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| 46 | |
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| 47 | struct clk_hw *clk_reg_prcmu_rate(const char *name, |
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| 48 | const char *parent_name, |
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| 49 | u8 cg_sel, |
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| 50 | unsigned long flags); |
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| 51 | |
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| 52 | struct clk_hw *clk_reg_prcmu_opp_gate(const char *name, |
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| 53 | const char *parent_name, |
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| 54 | u8 cg_sel, |
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| 55 | unsigned long flags); |
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| 56 | |
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| 57 | struct clk_hw *clk_reg_prcmu_opp_volt_scalable(const char *name, |
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| 58 | const char *parent_name, |
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| 59 | u8 cg_sel, |
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| 60 | unsigned long rate, |
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| 61 | unsigned long flags); |
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| 62 | |
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| 63 | struct clk_hw *clk_reg_prcmu_clkout(const char *name, |
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| 64 | const char * const *parent_names, |
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| 65 | int num_parents, |
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| 66 | u8 source, u8 divider); |
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| 67 | |
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| 68 | struct clk *clk_reg_sysctrl_gate(struct device *dev, |
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| 69 | const char *name, |
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| 70 | const char *parent_name, |
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| 71 | u16 reg_sel, |
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| 72 | u8 reg_mask, |
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| 73 | u8 reg_bits, |
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| 74 | unsigned long enable_delay_us, |
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| 75 | unsigned long flags); |
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| 76 | |
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| 77 | struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, |
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| 78 | const char *name, |
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| 79 | const char *parent_name, |
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| 80 | u16 reg_sel, |
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| 81 | u8 reg_mask, |
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| 82 | u8 reg_bits, |
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| 83 | unsigned long rate, |
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| 84 | unsigned long enable_delay_us, |
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| 85 | unsigned long flags); |
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| 86 | |
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| 87 | struct clk *clk_reg_sysctrl_set_parent(struct device *dev, |
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| 88 | const char *name, |
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| 89 | const char **parent_names, |
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| 90 | u8 num_parents, |
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| 91 | u16 *reg_sel, |
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| 92 | u8 *reg_mask, |
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| 93 | u8 *reg_bits, |
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| 94 | unsigned long flags); |
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| 95 | |
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| 96 | #endif /* __UX500_CLK_H */ |
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| 97 | |
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