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1/*
2 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
11 * programmed to go from @count to @limit and optionally interrupt.
12 * We've designated TIMER0 for clockevents and TIMER1 for clocksource
13 *
14 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
15 * which are suitable for UP and SMP based clocksources respectively
16 */
17
18#include <linux/interrupt.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/clocksource.h>
22#include <linux/clockchips.h>
23#include <linux/cpu.h>
24#include <linux/of.h>
25#include <linux/of_irq.h>
26#include <linux/sched_clock.h>
27
28#include <soc/arc/timers.h>
29#include <soc/arc/mcip.h>
30
31
32static unsigned long arc_timer_freq;
33
34static int noinline arc_get_timer_clk(struct device_node *node)
35{
36 struct clk *clk;
37 int ret;
38
39 clk = of_clk_get(node, 0);
40 if (IS_ERR(clk)) {
41 pr_err("timer missing clk\n");
42 return PTR_ERR(clk);
43 }
44
45 ret = clk_prepare_enable(clk);
46 if (ret) {
47 pr_err("Couldn't enable parent clk\n");
48 return ret;
49 }
50
51 arc_timer_freq = clk_get_rate(clk);
52
53 return 0;
54}
55
56/********** Clock Source Device *********/
57
58#ifdef CONFIG_ARC_TIMERS_64BIT
59
60static u64 arc_read_gfrc(struct clocksource *cs)
61{
62 unsigned long flags;
63 u32 l, h;
64
65 /*
66 * From a programming model pov, there seems to be just one instance of
67 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's
68 * an instance PER ARC CORE (not per cluster), and there are dedicated
69 * hardware decode logic (per core) inside ARConnect to handle
70 * simultaneous read/write accesses from cores via those two registers.
71 * So several concurrent commands to ARConnect are OK if they are
72 * trying to access two different sub-components (like GFRC,
73 * inter-core interrupt, etc...). HW also supports simultaneously
74 * accessing GFRC by multiple cores.
75 * That's why it is safe to disable hard interrupts on the local CPU
76 * before access to GFRC instead of taking global MCIP spinlock
77 * defined in arch/arc/kernel/mcip.c
78 */
79 local_irq_save(flags);
80
81 __mcip_cmd(CMD_GFRC_READ_LO, 0);
82 l = read_aux_reg(ARC_REG_MCIP_READBACK);
83
84 __mcip_cmd(CMD_GFRC_READ_HI, 0);
85 h = read_aux_reg(ARC_REG_MCIP_READBACK);
86
87 local_irq_restore(flags);
88
89 return (((u64)h) << 32) | l;
90}
91
92static notrace u64 arc_gfrc_clock_read(void)
93{
94 return arc_read_gfrc(NULL);
95}
96
97static struct clocksource arc_counter_gfrc = {
98 .name = "ARConnect GFRC",
99 .rating = 400,
100 .read = arc_read_gfrc,
101 .mask = CLOCKSOURCE_MASK(64),
102 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
103};
104
105static int __init arc_cs_setup_gfrc(struct device_node *node)
106{
107 struct mcip_bcr mp;
108 int ret;
109
110 READ_BCR(ARC_REG_MCIP_BCR, mp);
111 if (!mp.gfrc) {
112 pr_warn("Global-64-bit-Ctr clocksource not detected\n");
113 return -ENXIO;
114 }
115
116 ret = arc_get_timer_clk(node);
117 if (ret)
118 return ret;
119
120 sched_clock_register(arc_gfrc_clock_read, 64, arc_timer_freq);
121
122 return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
123}
124TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
125
126#define AUX_RTC_CTRL 0x103
127#define AUX_RTC_LOW 0x104
128#define AUX_RTC_HIGH 0x105
129
130static u64 arc_read_rtc(struct clocksource *cs)
131{
132 unsigned long status;
133 u32 l, h;
134
135 /*
136 * hardware has an internal state machine which tracks readout of
137 * low/high and updates the CTRL.status if
138 * - interrupt/exception taken between the two reads
139 * - high increments after low has been read
140 */
141 do {
142 l = read_aux_reg(AUX_RTC_LOW);
143 h = read_aux_reg(AUX_RTC_HIGH);
144 status = read_aux_reg(AUX_RTC_CTRL);
145 } while (!(status & _BITUL(31)));
146
147 return (((u64)h) << 32) | l;
148}
149
150static notrace u64 arc_rtc_clock_read(void)
151{
152 return arc_read_rtc(NULL);
153}
154
155static struct clocksource arc_counter_rtc = {
156 .name = "ARCv2 RTC",
157 .rating = 350,
158 .read = arc_read_rtc,
159 .mask = CLOCKSOURCE_MASK(64),
160 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
161};
162
163static int __init arc_cs_setup_rtc(struct device_node *node)
164{
165 struct bcr_timer timer;
166 int ret;
167
168 READ_BCR(ARC_REG_TIMERS_BCR, timer);
169 if (!timer.rtc) {
170 pr_warn("Local-64-bit-Ctr clocksource not detected\n");
171 return -ENXIO;
172 }
173
174 /* Local to CPU hence not usable in SMP */
175 if (IS_ENABLED(CONFIG_SMP)) {
176 pr_warn("Local-64-bit-Ctr not usable in SMP\n");
177 return -EINVAL;
178 }
179
180 ret = arc_get_timer_clk(node);
181 if (ret)
182 return ret;
183
184 write_aux_reg(AUX_RTC_CTRL, 1);
185
186 sched_clock_register(arc_rtc_clock_read, 64, arc_timer_freq);
187
188 return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
189}
190TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
191
192#endif
193
194/*
195 * 32bit TIMER1 to keep counting monotonically and wraparound
196 */
197
198static u64 arc_read_timer1(struct clocksource *cs)
199{
200 return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);
201}
202
203static notrace u64 arc_timer1_clock_read(void)
204{
205 return arc_read_timer1(NULL);
206}
207
208static struct clocksource arc_counter_timer1 = {
209 .name = "ARC Timer1",
210 .rating = 300,
211 .read = arc_read_timer1,
212 .mask = CLOCKSOURCE_MASK(32),
213 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
214};
215
216static int __init arc_cs_setup_timer1(struct device_node *node)
217{
218 int ret;
219
220 /* Local to CPU hence not usable in SMP */
221 if (IS_ENABLED(CONFIG_SMP))
222 return -EINVAL;
223
224 ret = arc_get_timer_clk(node);
225 if (ret)
226 return ret;
227
228 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
229 write_aux_reg(ARC_REG_TIMER1_CNT, 0);
230 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
231
232 sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq);
233
234 return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
235}
236
237/********** Clock Event Device *********/
238
239static int arc_timer_irq;
240
241/*
242 * Arm the timer to interrupt after @cycles
243 * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
244 */
245static void arc_timer_event_setup(unsigned int cycles)
246{
247 write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
248 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
249
250 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
251}
252
253
254static int arc_clkevent_set_next_event(unsigned long delta,
255 struct clock_event_device *dev)
256{
257 arc_timer_event_setup(delta);
258 return 0;
259}
260
261static int arc_clkevent_set_periodic(struct clock_event_device *dev)
262{
263 /*
264 * At X Hz, 1 sec = 1000ms -> X cycles;
265 * 10ms -> X / 100 cycles
266 */
267 arc_timer_event_setup(arc_timer_freq / HZ);
268 return 0;
269}
270
271static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
272 .name = "ARC Timer0",
273 .features = CLOCK_EVT_FEAT_ONESHOT |
274 CLOCK_EVT_FEAT_PERIODIC,
275 .rating = 300,
276 .set_next_event = arc_clkevent_set_next_event,
277 .set_state_periodic = arc_clkevent_set_periodic,
278};
279
280static irqreturn_t timer_irq_handler(int irq, void *dev_id)
281{
282 /*
283 * Note that generic IRQ core could have passed @evt for @dev_id if
284 * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
285 */
286 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
287 int irq_reenable = clockevent_state_periodic(evt);
288
289 /*
290 * 1. ACK the interrupt
291 * - For ARC700, any write to CTRL reg ACKs it, so just rewrite
292 * Count when [N]ot [H]alted bit.
293 * - For HS3x, it is a bit subtle. On taken count-down interrupt,
294 * IP bit [3] is set, which needs to be cleared for ACK'ing.
295 * The write below can only update the other two bits, hence
296 * explicitly clears IP bit
297 * 2. Re-arm interrupt if periodic by writing to IE bit [0]
298 */
299 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
300
301 evt->event_handler(evt);
302
303 return IRQ_HANDLED;
304}
305
306
307static int arc_timer_starting_cpu(unsigned int cpu)
308{
309 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
310
311 evt->cpumask = cpumask_of(smp_processor_id());
312
313 clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
314 enable_percpu_irq(arc_timer_irq, 0);
315 return 0;
316}
317
318static int arc_timer_dying_cpu(unsigned int cpu)
319{
320 disable_percpu_irq(arc_timer_irq);
321 return 0;
322}
323
324/*
325 * clockevent setup for boot CPU
326 */
327static int __init arc_clockevent_setup(struct device_node *node)
328{
329 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
330 int ret;
331
332 arc_timer_irq = irq_of_parse_and_map(node, 0);
333 if (arc_timer_irq <= 0) {
334 pr_err("clockevent: missing irq\n");
335 return -EINVAL;
336 }
337
338 ret = arc_get_timer_clk(node);
339 if (ret) {
340 pr_err("clockevent: missing clk\n");
341 return ret;
342 }
343
344 /* Needs apriori irq_set_percpu_devid() done in intc map function */
345 ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
346 "Timer0 (per-cpu-tick)", evt);
347 if (ret) {
348 pr_err("clockevent: unable to request irq\n");
349 return ret;
350 }
351
352 ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
353 "clockevents/arc/timer:starting",
354 arc_timer_starting_cpu,
355 arc_timer_dying_cpu);
356 if (ret) {
357 pr_err("Failed to setup hotplug state\n");
358 return ret;
359 }
360 return 0;
361}
362
363static int __init arc_of_timer_init(struct device_node *np)
364{
365 static int init_count = 0;
366 int ret;
367
368 if (!init_count) {
369 init_count = 1;
370 ret = arc_clockevent_setup(np);
371 } else {
372 ret = arc_cs_setup_timer1(np);
373 }
374
375 return ret;
376}
377TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
378

Warning: That file was not part of the compilation database. It may have many parsing errors.