1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // |
3 | // Copyright 2016 Freescale Semiconductor, Inc. |
4 | // Copyright 2017 NXP |
5 | |
6 | #include <linux/clk.h> |
7 | #include <linux/clockchips.h> |
8 | #include <linux/clocksource.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/interrupt.h> |
11 | #include <linux/sched_clock.h> |
12 | |
13 | #include "timer-of.h" |
14 | |
15 | #define TPM_PARAM 0x4 |
16 | #define TPM_PARAM_WIDTH_SHIFT 16 |
17 | #define TPM_PARAM_WIDTH_MASK (0xff << 16) |
18 | #define TPM_SC 0x10 |
19 | #define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3) |
20 | #define TPM_SC_CMOD_DIV_DEFAULT 0x3 |
21 | #define TPM_SC_CMOD_DIV_MAX 0x7 |
22 | #define TPM_SC_TOF_MASK (0x1 << 7) |
23 | #define TPM_CNT 0x14 |
24 | #define TPM_MOD 0x18 |
25 | #define TPM_STATUS 0x1c |
26 | #define TPM_STATUS_CH0F BIT(0) |
27 | #define TPM_C0SC 0x20 |
28 | #define TPM_C0SC_CHIE BIT(6) |
29 | #define TPM_C0SC_MODE_SHIFT 2 |
30 | #define TPM_C0SC_MODE_MASK 0x3c |
31 | #define TPM_C0SC_MODE_SW_COMPARE 0x4 |
32 | #define TPM_C0SC_CHF_MASK (0x1 << 7) |
33 | #define TPM_C0V 0x24 |
34 | |
35 | static int counter_width __ro_after_init; |
36 | static void __iomem *timer_base __ro_after_init; |
37 | |
38 | static inline void tpm_timer_disable(void) |
39 | { |
40 | unsigned int val; |
41 | |
42 | /* channel disable */ |
43 | val = readl(addr: timer_base + TPM_C0SC); |
44 | val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE); |
45 | writel(val, addr: timer_base + TPM_C0SC); |
46 | } |
47 | |
48 | static inline void tpm_timer_enable(void) |
49 | { |
50 | unsigned int val; |
51 | |
52 | /* channel enabled in sw compare mode */ |
53 | val = readl(addr: timer_base + TPM_C0SC); |
54 | val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) | |
55 | TPM_C0SC_CHIE; |
56 | writel(val, addr: timer_base + TPM_C0SC); |
57 | } |
58 | |
59 | static inline void tpm_irq_acknowledge(void) |
60 | { |
61 | writel(TPM_STATUS_CH0F, addr: timer_base + TPM_STATUS); |
62 | } |
63 | |
64 | static inline unsigned long tpm_read_counter(void) |
65 | { |
66 | return readl(addr: timer_base + TPM_CNT); |
67 | } |
68 | |
69 | #if defined(CONFIG_ARM) |
70 | static struct delay_timer tpm_delay_timer; |
71 | |
72 | static unsigned long tpm_read_current_timer(void) |
73 | { |
74 | return tpm_read_counter(); |
75 | } |
76 | |
77 | static u64 notrace tpm_read_sched_clock(void) |
78 | { |
79 | return tpm_read_counter(); |
80 | } |
81 | #endif |
82 | |
83 | static int tpm_set_next_event(unsigned long delta, |
84 | struct clock_event_device *evt) |
85 | { |
86 | unsigned long next, now; |
87 | |
88 | next = tpm_read_counter(); |
89 | next += delta; |
90 | writel(val: next, addr: timer_base + TPM_C0V); |
91 | now = tpm_read_counter(); |
92 | |
93 | /* |
94 | * NOTE: We observed in a very small probability, the bus fabric |
95 | * contention between GPU and A7 may results a few cycles delay |
96 | * of writing CNT registers which may cause the min_delta event got |
97 | * missed, so we need add a ETIME check here in case it happened. |
98 | */ |
99 | return (int)(next - now) <= 0 ? -ETIME : 0; |
100 | } |
101 | |
102 | static int tpm_set_state_oneshot(struct clock_event_device *evt) |
103 | { |
104 | tpm_timer_enable(); |
105 | |
106 | return 0; |
107 | } |
108 | |
109 | static int tpm_set_state_shutdown(struct clock_event_device *evt) |
110 | { |
111 | tpm_timer_disable(); |
112 | |
113 | return 0; |
114 | } |
115 | |
116 | static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id) |
117 | { |
118 | struct clock_event_device *evt = dev_id; |
119 | |
120 | tpm_irq_acknowledge(); |
121 | |
122 | evt->event_handler(evt); |
123 | |
124 | return IRQ_HANDLED; |
125 | } |
126 | |
127 | static struct timer_of to_tpm = { |
128 | .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, |
129 | .clkevt = { |
130 | .name = "i.MX TPM Timer" , |
131 | .rating = 200, |
132 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ, |
133 | .set_state_shutdown = tpm_set_state_shutdown, |
134 | .set_state_oneshot = tpm_set_state_oneshot, |
135 | .set_next_event = tpm_set_next_event, |
136 | .cpumask = cpu_possible_mask, |
137 | }, |
138 | .of_irq = { |
139 | .handler = tpm_timer_interrupt, |
140 | .flags = IRQF_TIMER, |
141 | }, |
142 | .of_clk = { |
143 | .name = "per" , |
144 | }, |
145 | }; |
146 | |
147 | static int __init tpm_clocksource_init(void) |
148 | { |
149 | #if defined(CONFIG_ARM) |
150 | tpm_delay_timer.read_current_timer = &tpm_read_current_timer; |
151 | tpm_delay_timer.freq = timer_of_rate(&to_tpm) >> 3; |
152 | register_current_timer_delay(&tpm_delay_timer); |
153 | |
154 | sched_clock_register(tpm_read_sched_clock, counter_width, |
155 | timer_of_rate(&to_tpm) >> 3); |
156 | #endif |
157 | |
158 | return clocksource_mmio_init(timer_base + TPM_CNT, |
159 | "imx-tpm" , |
160 | timer_of_rate(to: &to_tpm) >> 3, |
161 | to_tpm.clkevt.rating, |
162 | counter_width, |
163 | clocksource_mmio_readl_up); |
164 | } |
165 | |
166 | static void __init tpm_clockevent_init(void) |
167 | { |
168 | clockevents_config_and_register(dev: &to_tpm.clkevt, |
169 | freq: timer_of_rate(to: &to_tpm) >> 3, |
170 | min_delta: 300, |
171 | GENMASK(counter_width - 1, |
172 | 1)); |
173 | } |
174 | |
175 | static int __init tpm_timer_init(struct device_node *np) |
176 | { |
177 | struct clk *ipg; |
178 | int ret; |
179 | |
180 | ipg = of_clk_get_by_name(np, name: "ipg" ); |
181 | if (IS_ERR(ptr: ipg)) { |
182 | pr_err("tpm: failed to get ipg clk\n" ); |
183 | return -ENODEV; |
184 | } |
185 | /* enable clk before accessing registers */ |
186 | ret = clk_prepare_enable(clk: ipg); |
187 | if (ret) { |
188 | pr_err("tpm: ipg clock enable failed (%d)\n" , ret); |
189 | clk_put(clk: ipg); |
190 | return ret; |
191 | } |
192 | |
193 | ret = timer_of_init(np, to: &to_tpm); |
194 | if (ret) |
195 | return ret; |
196 | |
197 | timer_base = timer_of_base(to: &to_tpm); |
198 | |
199 | counter_width = (readl(addr: timer_base + TPM_PARAM) |
200 | & TPM_PARAM_WIDTH_MASK) >> TPM_PARAM_WIDTH_SHIFT; |
201 | /* use rating 200 for 32-bit counter and 150 for 16-bit counter */ |
202 | to_tpm.clkevt.rating = counter_width == 0x20 ? 200 : 150; |
203 | |
204 | /* |
205 | * Initialize tpm module to a known state |
206 | * 1) Counter disabled |
207 | * 2) TPM counter operates in up counting mode |
208 | * 3) Timer Overflow Interrupt disabled |
209 | * 4) Channel0 disabled |
210 | * 5) DMA transfers disabled |
211 | */ |
212 | /* make sure counter is disabled */ |
213 | writel(val: 0, addr: timer_base + TPM_SC); |
214 | /* TOF is W1C */ |
215 | writel(TPM_SC_TOF_MASK, addr: timer_base + TPM_SC); |
216 | writel(val: 0, addr: timer_base + TPM_CNT); |
217 | /* CHF is W1C */ |
218 | writel(TPM_C0SC_CHF_MASK, addr: timer_base + TPM_C0SC); |
219 | |
220 | /* |
221 | * increase per cnt, |
222 | * div 8 for 32-bit counter and div 128 for 16-bit counter |
223 | */ |
224 | writel(TPM_SC_CMOD_INC_PER_CNT | |
225 | (counter_width == 0x20 ? |
226 | TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX), |
227 | addr: timer_base + TPM_SC); |
228 | |
229 | /* set MOD register to maximum for free running mode */ |
230 | writel(GENMASK(counter_width - 1, 0), addr: timer_base + TPM_MOD); |
231 | |
232 | tpm_clockevent_init(); |
233 | |
234 | return tpm_clocksource_init(); |
235 | } |
236 | TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm" , tpm_timer_init); |
237 | |