1/*
2 * Mediatek SoCs General-Purpose Timer handling.
3 *
4 * Copyright (C) 2014 Matthias Brugger
5 *
6 * Matthias Brugger <matthias.bgg@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21#include <linux/clockchips.h>
22#include <linux/clocksource.h>
23#include <linux/interrupt.h>
24#include <linux/irqreturn.h>
25#include <linux/sched_clock.h>
26#include <linux/slab.h>
27#include "timer-of.h"
28
29#define TIMER_CLK_EVT (1)
30#define TIMER_CLK_SRC (2)
31
32#define TIMER_SYNC_TICKS (3)
33
34/* gpt */
35#define GPT_IRQ_EN_REG 0x00
36#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
37#define GPT_IRQ_ACK_REG 0x08
38#define GPT_IRQ_ACK(val) BIT((val) - 1)
39
40#define GPT_CTRL_REG(val) (0x10 * (val))
41#define GPT_CTRL_OP(val) (((val) & 0x3) << 4)
42#define GPT_CTRL_OP_ONESHOT (0)
43#define GPT_CTRL_OP_REPEAT (1)
44#define GPT_CTRL_OP_FREERUN (3)
45#define GPT_CTRL_CLEAR (2)
46#define GPT_CTRL_ENABLE (1)
47#define GPT_CTRL_DISABLE (0)
48
49#define GPT_CLK_REG(val) (0x04 + (0x10 * (val)))
50#define GPT_CLK_SRC(val) (((val) & 0x1) << 4)
51#define GPT_CLK_SRC_SYS13M (0)
52#define GPT_CLK_SRC_RTC32K (1)
53#define GPT_CLK_DIV1 (0x0)
54#define GPT_CLK_DIV2 (0x1)
55
56#define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
57#define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
58
59/* system timer */
60#define SYST_BASE (0x40)
61
62#define SYST_CON (SYST_BASE + 0x0)
63#define SYST_VAL (SYST_BASE + 0x4)
64
65#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
66#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
67
68/*
69 * SYST_CON_EN: Clock enable. Shall be set to
70 * - Start timer countdown.
71 * - Allow timeout ticks being updated.
72 * - Allow changing interrupt functions.
73 *
74 * SYST_CON_IRQ_EN: Set to allow interrupt.
75 *
76 * SYST_CON_IRQ_CLR: Set to clear interrupt.
77 */
78#define SYST_CON_EN BIT(0)
79#define SYST_CON_IRQ_EN BIT(1)
80#define SYST_CON_IRQ_CLR BIT(4)
81
82static void __iomem *gpt_sched_reg __read_mostly;
83
84static void mtk_syst_ack_irq(struct timer_of *to)
85{
86 /* Clear and disable interrupt */
87 writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
88}
89
90static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
91{
92 struct clock_event_device *clkevt = dev_id;
93 struct timer_of *to = to_timer_of(clkevt);
94
95 mtk_syst_ack_irq(to);
96 clkevt->event_handler(clkevt);
97
98 return IRQ_HANDLED;
99}
100
101static int mtk_syst_clkevt_next_event(unsigned long ticks,
102 struct clock_event_device *clkevt)
103{
104 struct timer_of *to = to_timer_of(clkevt);
105
106 /* Enable clock to allow timeout tick update later */
107 writel(SYST_CON_EN, SYST_CON_REG(to));
108
109 /*
110 * Write new timeout ticks. Timer shall start countdown
111 * after timeout ticks are updated.
112 */
113 writel(ticks, SYST_VAL_REG(to));
114
115 /* Enable interrupt */
116 writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));
117
118 return 0;
119}
120
121static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
122{
123 /* Disable timer */
124 writel(0, SYST_CON_REG(to_timer_of(clkevt)));
125
126 return 0;
127}
128
129static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
130{
131 return mtk_syst_clkevt_shutdown(clkevt);
132}
133
134static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
135{
136 return 0;
137}
138
139static u64 notrace mtk_gpt_read_sched_clock(void)
140{
141 return readl_relaxed(gpt_sched_reg);
142}
143
144static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
145{
146 u32 val;
147
148 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
149 writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
150 GPT_CTRL_REG(timer));
151}
152
153static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
154 unsigned long delay, u8 timer)
155{
156 writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
157}
158
159static void mtk_gpt_clkevt_time_start(struct timer_of *to,
160 bool periodic, u8 timer)
161{
162 u32 val;
163
164 /* Acknowledge interrupt */
165 writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
166
167 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
168
169 /* Clear 2 bit timer operation mode field */
170 val &= ~GPT_CTRL_OP(0x3);
171
172 if (periodic)
173 val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
174 else
175 val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);
176
177 writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
178 timer_of_base(to) + GPT_CTRL_REG(timer));
179}
180
181static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
182{
183 mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);
184
185 return 0;
186}
187
188static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
189{
190 struct timer_of *to = to_timer_of(clk);
191
192 mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
193 mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
194 mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
195
196 return 0;
197}
198
199static int mtk_gpt_clkevt_next_event(unsigned long event,
200 struct clock_event_device *clk)
201{
202 struct timer_of *to = to_timer_of(clk);
203
204 mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
205 mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
206 mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
207
208 return 0;
209}
210
211static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
212{
213 struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
214 struct timer_of *to = to_timer_of(clkevt);
215
216 /* Acknowledge timer0 irq */
217 writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
218 clkevt->event_handler(clkevt);
219
220 return IRQ_HANDLED;
221}
222
223static void
224__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
225{
226 writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
227 timer_of_base(to) + GPT_CTRL_REG(timer));
228
229 writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
230 timer_of_base(to) + GPT_CLK_REG(timer));
231
232 writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
233
234 writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
235 timer_of_base(to) + GPT_CTRL_REG(timer));
236}
237
238static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
239{
240 u32 val;
241
242 /* Disable all interrupts */
243 writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
244
245 /* Acknowledge all spurious pending interrupts */
246 writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
247
248 val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
249 writel(val | GPT_IRQ_ENABLE(timer),
250 timer_of_base(to) + GPT_IRQ_EN_REG);
251}
252
253static struct timer_of to = {
254 .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
255
256 .clkevt = {
257 .name = "mtk-clkevt",
258 .rating = 300,
259 .cpumask = cpu_possible_mask,
260 },
261
262 .of_irq = {
263 .flags = IRQF_TIMER | IRQF_IRQPOLL,
264 },
265};
266
267static int __init mtk_syst_init(struct device_node *node)
268{
269 int ret;
270
271 to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
272 to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
273 to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
274 to.clkevt.tick_resume = mtk_syst_clkevt_resume;
275 to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
276 to.of_irq.handler = mtk_syst_handler;
277
278 ret = timer_of_init(node, &to);
279 if (ret)
280 goto err;
281
282 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
283 TIMER_SYNC_TICKS, 0xffffffff);
284
285 return 0;
286err:
287 timer_of_cleanup(&to);
288 return ret;
289}
290
291static int __init mtk_gpt_init(struct device_node *node)
292{
293 int ret;
294
295 to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
296 to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
297 to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
298 to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
299 to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
300 to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
301 to.of_irq.handler = mtk_gpt_interrupt;
302
303 ret = timer_of_init(node, &to);
304 if (ret)
305 goto err;
306
307 /* Configure clock source */
308 mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
309 clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
310 node->name, timer_of_rate(&to), 300, 32,
311 clocksource_mmio_readl_up);
312 gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
313 sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
314
315 /* Configure clock event */
316 mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
317 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
318 TIMER_SYNC_TICKS, 0xffffffff);
319
320 mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
321
322 return 0;
323err:
324 timer_of_cleanup(&to);
325 return ret;
326}
327TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
328TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
329