1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * (c) 2003-2006 Advanced Micro Devices, Inc. |
4 | */ |
5 | |
6 | struct powernow_k8_data { |
7 | unsigned int cpu; |
8 | |
9 | u32 numps; /* number of p-states */ |
10 | u32 batps; /* number of p-states supported on battery */ |
11 | |
12 | /* these values are constant when the PSB is used to determine |
13 | * vid/fid pairings, but are modified during the ->target() call |
14 | * when ACPI is used */ |
15 | u32 rvo; /* ramp voltage offset */ |
16 | u32 irt; /* isochronous relief time */ |
17 | u32 vidmvs; /* usable value calculated from mvs */ |
18 | u32 vstable; /* voltage stabilization time, units 20 us */ |
19 | u32 plllock; /* pll lock time, units 1 us */ |
20 | u32 exttype; /* extended interface = 1 */ |
21 | |
22 | /* keep track of the current fid / vid or pstate */ |
23 | u32 currvid; |
24 | u32 currfid; |
25 | |
26 | /* the powernow_table includes all frequency and vid/fid pairings: |
27 | * fid are the lower 8 bits of the index, vid are the upper 8 bits. |
28 | * frequency is in kHz */ |
29 | struct cpufreq_frequency_table *powernow_table; |
30 | |
31 | /* the acpi table needs to be kept. it's only available if ACPI was |
32 | * used to determine valid frequency/vid/fid states */ |
33 | struct acpi_processor_performance acpi_data; |
34 | |
35 | /* we need to keep track of associated cores, but let cpufreq |
36 | * handle hotplug events - so just point at cpufreq pol->cpus |
37 | * structure */ |
38 | struct cpumask *available_cores; |
39 | }; |
40 | |
41 | /* processor's cpuid instruction support */ |
42 | #define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */ |
43 | #define CPUID_XFAM 0x0ff00000 /* extended family */ |
44 | #define CPUID_XFAM_K8 0 |
45 | #define CPUID_XMOD 0x000f0000 /* extended model */ |
46 | #define CPUID_XMOD_REV_MASK 0x000c0000 |
47 | #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */ |
48 | #define CPUID_USE_XFAM_XMOD 0x00000f00 |
49 | #define CPUID_GET_MAX_CAPABILITIES 0x80000000 |
50 | #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 |
51 | #define P_STATE_TRANSITION_CAPABLE 6 |
52 | |
53 | /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */ |
54 | /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ |
55 | /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */ |
56 | /* the register number is placed in ecx, and the data is returned in edx:eax. */ |
57 | |
58 | #define MSR_FIDVID_CTL 0xc0010041 |
59 | #define MSR_FIDVID_STATUS 0xc0010042 |
60 | |
61 | /* Field definitions within the FID VID Low Control MSR : */ |
62 | #define MSR_C_LO_INIT_FID_VID 0x00010000 |
63 | #define MSR_C_LO_NEW_VID 0x00003f00 |
64 | #define MSR_C_LO_NEW_FID 0x0000003f |
65 | #define MSR_C_LO_VID_SHIFT 8 |
66 | |
67 | /* Field definitions within the FID VID High Control MSR : */ |
68 | #define MSR_C_HI_STP_GNT_TO 0x000fffff |
69 | |
70 | /* Field definitions within the FID VID Low Status MSR : */ |
71 | #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */ |
72 | #define MSR_S_LO_MAX_RAMP_VID 0x3f000000 |
73 | #define MSR_S_LO_MAX_FID 0x003f0000 |
74 | #define MSR_S_LO_START_FID 0x00003f00 |
75 | #define MSR_S_LO_CURRENT_FID 0x0000003f |
76 | |
77 | /* Field definitions within the FID VID High Status MSR : */ |
78 | #define MSR_S_HI_MIN_WORKING_VID 0x3f000000 |
79 | #define MSR_S_HI_MAX_WORKING_VID 0x003f0000 |
80 | #define MSR_S_HI_START_VID 0x00003f00 |
81 | #define MSR_S_HI_CURRENT_VID 0x0000003f |
82 | #define MSR_C_HI_STP_GNT_BENIGN 0x00000001 |
83 | |
84 | /* |
85 | * There are restrictions frequencies have to follow: |
86 | * - only 1 entry in the low fid table ( <=1.4GHz ) |
87 | * - lowest entry in the high fid table must be >= 2 * the entry in the |
88 | * low fid table |
89 | * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry |
90 | * in the low fid table |
91 | * - the parts can only step at <= 200 MHz intervals, odd fid values are |
92 | * supported in revision G and later revisions. |
93 | * - lowest frequency must be >= interprocessor hypertransport link speed |
94 | * (only applies to MP systems obviously) |
95 | */ |
96 | |
97 | /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */ |
98 | #define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */ |
99 | #define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */ |
100 | |
101 | #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */ |
102 | #define HI_VCOFREQ_TABLE_BOTTOM 1600 |
103 | |
104 | #define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */ |
105 | |
106 | #define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */ |
107 | #define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */ |
108 | |
109 | #define MIN_FREQ 800 /* Min and max freqs, per spec */ |
110 | #define MAX_FREQ 5000 |
111 | |
112 | #define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */ |
113 | #define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */ |
114 | |
115 | #define VID_OFF 0x3f |
116 | |
117 | #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */ |
118 | |
119 | #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */ |
120 | |
121 | #define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */ |
122 | #define VST_UNITS_20US 20 /* Voltage Stabilization Time is in units of 20us */ |
123 | |
124 | /* |
125 | * Most values of interest are encoded in a single field of the _PSS |
126 | * entries: the "control" value. |
127 | */ |
128 | |
129 | #define IRT_SHIFT 30 |
130 | #define RVO_SHIFT 28 |
131 | #define EXT_TYPE_SHIFT 27 |
132 | #define PLL_L_SHIFT 20 |
133 | #define MVS_SHIFT 18 |
134 | #define VST_SHIFT 11 |
135 | #define VID_SHIFT 6 |
136 | #define IRT_MASK 3 |
137 | #define RVO_MASK 3 |
138 | #define EXT_TYPE_MASK 1 |
139 | #define PLL_L_MASK 0x7f |
140 | #define MVS_MASK 3 |
141 | #define VST_MASK 0x7f |
142 | #define VID_MASK 0x1f |
143 | #define FID_MASK 0x1f |
144 | #define EXT_VID_MASK 0x3f |
145 | #define EXT_FID_MASK 0x3f |
146 | |
147 | |
148 | /* |
149 | * Version 1.4 of the PSB table. This table is constructed by BIOS and is |
150 | * to tell the OS's power management driver which VIDs and FIDs are |
151 | * supported by this particular processor. |
152 | * If the data in the PSB / PST is wrong, then this driver will program the |
153 | * wrong values into hardware, which is very likely to lead to a crash. |
154 | */ |
155 | |
156 | #define PSB_ID_STRING "AMDK7PNOW!" |
157 | #define PSB_ID_STRING_LEN 10 |
158 | |
159 | #define PSB_VERSION_1_4 0x14 |
160 | |
161 | struct psb_s { |
162 | u8 signature[10]; |
163 | u8 tableversion; |
164 | u8 flags1; |
165 | u16 vstable; |
166 | u8 flags2; |
167 | u8 num_tables; |
168 | u32 cpuid; |
169 | u8 plllocktime; |
170 | u8 maxfid; |
171 | u8 maxvid; |
172 | u8 numps; |
173 | }; |
174 | |
175 | /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */ |
176 | struct pst_s { |
177 | u8 fid; |
178 | u8 vid; |
179 | }; |
180 | |
181 | static int core_voltage_pre_transition(struct powernow_k8_data *data, |
182 | u32 reqvid, u32 regfid); |
183 | static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid); |
184 | static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid); |
185 | |
186 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); |
187 | |
188 | static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); |
189 | |